JP3096640B2 - Semiconductor device and display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a thin film transistor
The present invention relates to a semiconductor device such as a thin film transistor (Thin Film Transistor) and a display device such as a liquid crystal display (LCD).

[0002]

2. Description of the Related Art In recent years, active matrix type LCDs have been developed.
As a pixel driving element (pixel driving transistor),
A thin film transistor (hereinafter, referred to as polycrystalline silicon TF) using a polycrystalline silicon film formed on a transparent insulating substrate as an active layer.
T).

Polycrystalline silicon TFTs have the advantage of higher mobility and higher driving capability than thin film transistors using an amorphous silicon film for the active layer. Therefore, if a polycrystalline silicon TFT is used, a high-performance LCD can be realized, and not only a pixel portion (display portion) but also a peripheral drive circuit (driver portion) can be integrally formed on the same substrate.

In such a polycrystalline silicon TFT, as a method of forming a polycrystalline silicon film as an active layer, a method of directly depositing a polycrystalline silicon film on a substrate, or a method of forming an amorphous silicon film on a substrate. Later, there is a method of polycrystallizing it. Among them, the method of directly depositing a polycrystalline silicon film on a substrate is a relatively simple process of depositing at a high temperature using, for example, a CVD method.

In order to polycrystallize an amorphous silicon film after it has been deposited, a solid phase growth method is generally used. This solid-phase growth method is a method in which a polycrystalline silicon film is obtained by performing a heat treatment on an amorphous silicon film so as to be polycrystallized in a solid state. An example of a method for manufacturing a polycrystalline silicon TFT will be described with reference to FIGS.

Step A (see FIG. 16): An amorphous silicon film is formed on an insulating substrate (for example, quartz glass) 51 by using a normal low-pressure CVD method, and is further heated in a nitrogen (N ₂ ) atmosphere. By performing a heat treatment at about 900 ° C., the amorphous silicon film is solid-phase grown to form a polycrystalline silicon film 5.
Form 2 In order to use the polycrystalline silicon film 52 as an active layer of a thin film transistor, the polycrystalline silicon film 52 is processed into a predetermined shape by a photolithography technique and a dry etching technique by an RIE method.

On the polycrystalline silicon film 52, a decompression C
A silicon oxide film as the gate insulating film 53 is deposited by using the VD method. Step B (see FIG. 17): After depositing a polycrystalline silicon film on the gate insulating film 53 by a low pressure CVD method, an impurity is implanted into the polycrystalline silicon film, and a heat treatment is performed to activate the impurity. .

Next, after a silicon oxide film 54 is deposited on the polycrystalline silicon film by a normal pressure CVD method, the polycrystalline silicon film and the silicon film are deposited by a photolithography technique and a dry etching technique by an RIE method. The oxide film 54 is processed into a predetermined shape. The polycrystalline silicon film is used as a gate electrode 55. Next, using the gate electrode 55 and the silicon oxide film 54 as a mask, impurities are implanted into the polycrystalline silicon film 52 by a self-alignment technique to form source / drain regions 56.

Finally, heat treatment is further performed to activate the impurities as the source / drain regions 56. Such a method is called a high temperature process because a high temperature of about 900 ° C. is used at the time of solid phase growth or activation of impurities. Further, development using a low-temperature process using a laser beam annealing method, an RTA method, or the like for the heat treatment is also becoming active.

[0010]

In the conventional example, there is a problem that the heat generated by the heat treatment is not effectively used, for example, the activation of impurities is not performed well. The present invention relates to a semiconductor device and a display device, and solves such a problem.

[0011]

Means for Solving the Problems The invention according to claim 1
Is a display device in which multiple semiconductor elements are integrated on a substrate.
A plurality of semiconductor elements each having a heat absorbing film;
A plurality of second semiconductor elements having no first semiconductor element and no heat absorbing film.
A semiconductor element on the substrate, including a semiconductor element
In accordance with the distribution of
A relatively large number of the second semiconductor elements
Integrated in the area where the semiconductor element is relatively few.
The first semiconductor element is relatively integrated.
You.

According to a second aspect of the present invention, there is provided a pixel section and a peripheral driver.
Driver integrated type with moving circuit part formed on the same substrate
In the display device, a heat absorbing film formed on the substrate,
A semiconductor film formed on the heat absorbing film;
Gate electrode formed on the film with the gate insulating film interposed
And an impurity region formed in the semiconductor film.
A semiconductor switching element is connected to a pixel drive in the pixel section.
Operating element and peripheral driving circuit in the peripheral driving circuit section
Heat sink located in the peripheral drive circuit section.
The heat absorption effect of the heat absorption film of the pixel portion
It is adjusted to be lower than the heat absorption effect.
You.

According to a third aspect of the present invention, there is provided a pixel unit and a peripheral driver.
Driver integrated type with moving circuit part formed on the same substrate
13. The display device according to claim 1, wherein the pixel driver is provided in the pixel portion.
A driving element and a peripheral drive provided in the peripheral drive circuit section.
A driving circuit element, wherein the pixel driving element and
Peripheral drive circuit elements consist of semiconductor switching elements
And the semiconductor switching element is formed on the substrate.
The heat absorbing film formed, and a semiconductor formed on the heat absorbing film.
Body film and a gate insulating film formed on the semiconductor film
Gate electrode and impurities formed in the semiconductor film
A region, and the heat absorbing film provided in the pixel portion.
Of the area or thickness of the semiconductor film,
The semiconductor of the heat absorbing film provided in the peripheral drive circuit unit
Larger than the ratio of area or film thickness to body membrane
It is set as follows. The invention as set forth in claim 4 is
The area of the heat absorption film in the pixel portion is equal to the entire pixel portion.
It is set to be 0.01 to 60% of the area
It is.

According to a fifth aspect of the present invention, there is provided a peripheral drive circuit section.
The area of the heat absorbing film in the
It is set to be 0.01 to 60% of the area
It is.

According to a sixth aspect of the present invention, there is provided the heat absorbing film according to the first aspect.
The area is 0.01 to 60% of the area of the entire substrate.
Is set as follows.

According to a seventh aspect of the present invention, the substrate comprises a liquid
Of a pair of substrates provided opposite each other with the
This is one of the substrates.

[0017] According to the invention described in claim 8, a plurality of substrates are provided on a substrate.
A display device in which semiconductor elements are integrated, wherein the plurality of semiconductor devices are integrated.
Plural first semiconductor elements in which the semiconductor element has a heat absorbing film
And a plurality of second semiconductor elements having no heat absorbing film,
According to the distribution state of the semiconductor element on the substrate
Where the semiconductor elements are relatively dense
The second semiconductor element is relatively integrated, and
The first semiconductor element is provided at a place where the number of conductive elements is relatively small.
Are relatively integrated.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION One embodiment that embodies the present invention
This will be described with reference to FIGS.

Step 1 (see FIG. 1): quartz glass or aluminum-free
On a substrate 1 such as potash glass, a sputtering method is used.
Tungsten silicide (WSix) film 2 (thickness 1000
Å, but can be adjusted in the range of 50 to 2000Å))
To form In the sputtering method, a W silicide alloy
Use Get.

Stoichiometric set of W silicide (WSi _x )
The composition is X = 2, but the composition of the alloy target is X> 2.
Set.

This is because the composition of the W silicide film 2 becomes X = 2.
Close, very high tensile stress during subsequent heat treatment
Cracks occur in the W silicide film 2 or peeling occurs.
This is because there is a risk of separation.

However, the resistance value of W silicide is the case where X = 2.
To the extent that cracks and peeling do not occur
Need to set the upper limit of X.

Step 2 (see FIG. 2): The W silicide film
2 using lithography technology and etching technology
Polycrystalline silicon as the active layer of the transistor described
Process into the same pattern. Step 3 (see FIG. 3): the substrate 1 and the W silicide film 2
To cover the _TwoInsulating thin film 3 such as or SiN
It is formed by a CVD method, a sputtering method, or the like. Specifically
Uses non-alkali glass as the substrate 1 and has a surface
Forming temperature of 350 ° C. by normal pressure or low pressure CVD method
With a thickness of 3000-5000Å_TwoForm a film
You.

The thickness of the SiO ₂ film, impurities in the substrate 1 by heat treatment or the like and the beam irradiation in the subsequent step is necessary thickness so as not to diffuse into the upper layer through the SiO ₂ film, 10
The range of 00 to 6000 is appropriate, and
The diffusion prevention effect is good when it is set to Å.
The most suitable range is from 00 to 5000 °. Also,
When SiN is used as the insulating thin film 3, the film thickness is suitably in the range of 1000 to 5000 °,
The diffusion prevention effect is good when the temperature is set to 5000 °, and the most suitable range is 2000 to 3000 °.

Step 4 (see FIG. 4): On the insulating thin film 3, an amorphous silicon film 4a (thickness: 500 °) is formed. When the amorphous silicon film 4a is used as an active layer of a TFT, if the active layer is too thick, the off current of the polycrystalline silicon TFT increases, and if it is too thin, the on current decreases. The thickness of the crystalline silicon film 4a is
The range of 400 to 800 ° is appropriate, and the characteristics are good when the temperature is set to 500 to 700 °, among which 500 to 600 °.
Is most suitable.

The method of forming the amorphous silicon film 4a is as follows. Method using low-pressure CVD: In order to form a silicon film by low-pressure CVD, thermal decomposition of monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ) is used. When monosilane is used, it becomes amorphous at a processing temperature of 550 ° C. or lower, and becomes polycrystalline at a processing temperature of 620 ° C. or higher. At 550 to 620 ° C., the amount of amorphous containing microcrystals increases, and the lower the temperature, the closer to amorphous and the number of microcrystals decreases. Therefore, the amount of microcrystals in the amorphous silicon film 4a can be adjusted only by changing the temperature condition.

Method using plasma CVD method: In order to form an amorphous silicon film by plasma CVD method, thermal decomposition of monosilane or disilane in plasma is used.
In an actual process, the above-described method is employed to form an amorphous silicon film containing no microcrystal under the conditions of gas used: monosilane, temperature: 350 ° C. Step 5 (see FIG. 5): The surface of the amorphous silicon film 4a is scanned with a KrF excimer laser beam having a wavelength of λ = 248 nm to perform an annealing process, thereby obtaining an amorphous silicon film 4a.
Is melted and recrystallized to form a polycrystalline silicon thin film 4.

Laser conditions at this time are as follows: annealing atmosphere: 1 × 10 ⁻⁴ Pa or less, substrate temperature: room temperature to 600 ° C.
Irradiation energy density: 100 to 500 mJ / cm ² , scanning speed: 1 to 10 mm / sec (actually, 0.1 to 1
(Scanning is possible at a speed in the range of 00 mm / sec). As the laser beam, Xe having a wavelength λ = 308 nm is used.
A Cl excimer laser may be used. The laser conditions at this time were as follows: annealing atmosphere: 1 × 10 ⁻⁴ Pa or less, substrate temperature: room temperature to 600 ° C., irradiation energy density: 100
５００500 mJ / cm ² , scanning speed: 1-10 mm / sec
c (actually, scanning at a speed in the range of 0.1 to 100 mm / sec) is possible.

Further, an ArF excimer laser having a wavelength λ = 193 nm may be used. The laser conditions in this case are as follows: annealing atmosphere: 1 × 10 ⁻⁴ Pa or less, substrate temperature:
Room temperature to 600 ° C, irradiation energy density: 100 to 500
mJ / cm ² , scanning speed: 1 to 10 mm / sec. Regardless of which laser beam is used, the grain size of polycrystalline silicon increases in proportion to the irradiation energy density and the number of times of irradiation, so if the energy density is adjusted so that a desired grain size can be obtained. Good.

In this embodiment, a high-throughput laser irradiation method is used for the excimer laser annealing. That is, in FIG. 14, 101 is a KrF excimer laser, 102 is a reflecting mirror that reflects the laser beam from the laser 101, 103 is a laser that processes the laser beam from the reflecting mirror 102 into a predetermined state and irradiates the substrate 1 with the laser beam. It is a beam control optical system.

In such a configuration, the high-throughput laser irradiation method refers to the laser beam control optical system 103.
A method of irradiating a laser beam processed into a sheet shape (150 mm × 0.5 mm) by superimposing multiple pulses, completely synchronizing stage scanning and pulse laser irradiation, and irradiating laser with extremely high precision overlap By doing so, the throughput is increased.

Step 6 (see FIG. 6): To use the polycrystalline silicon film 4 as an active layer of a thin film transistor,
The polycrystalline silicon film 4 is processed into a predetermined shape by a photolithography technique or a dry etching technique by an RIE method. Then, an LTO film (Low Temperature) as a gate insulating film is formed on the polycrystalline silicon film 4 by a low pressure CVD method using a load lock type low pressure CVD apparatus.
Oxide (silicon oxide film) 5 (thickness 1000 °) is formed.

Step 7 (see FIG. 7): The gate insulating film 5
An amorphous silicon film (film thickness 2)
000 °) 6a is deposited. This amorphous silicon film 6a
Is doped at the time of its formation with an impurity (arsenic or phosphorus for N-type or boron for P-type), but may be deposited in a non-doped state and then implanted. Next, using a sputtering method, the tungsten silicide on amorphous silicon film 6a (WSi _x) layer 6b (thickness 1000 Å)
To form

After a silicon oxide film 7 is deposited on the W silicide film 6b by the normal pressure CVD method, the polycrystalline silicon film 6a, W The silicide film 6b and the silicon oxide film 7 are processed into a predetermined shape. The amorphous silicon film 6a is used as the gate electrode 6 having a polycide structure together with the W silicide film 6b.

Step 8 (see FIG. 8): the gate insulating film 5
A silicon oxide film is deposited on the silicon oxide film 7 by a normal pressure CVD method, and the silicon oxide film is etched back anisotropically to form the gate electrode 6 and the silicon oxide film 7.
Side wall 8 is formed on the side of. Then, an acceleration voltage of 80 KeV and a dose of 3
Under the condition of × 10 ¹³ cm ^-2 , phosphorus (P) ions are implanted as impurities to form low-concentration impurity regions 9a.

Step 9 (see FIG. 9): The sidewalls 8 and the silicon oxide film 7 are covered with a resist 10, and the polycrystalline silicon film 4 is again applied to the polycrystalline silicon film 4 by a self-alignment technique using the resist 10 as a mask, at an acceleration voltage of 80 KeV and a dose. Quantity 1 ×
The source / drain region 9 having an LDD (Lightly Doped Drain) structure is formed by implanting phosphorus (P) ions as impurities under the condition of 10 ¹⁵ cm ^-2 to form a high-concentration impurity region 9b.

Step 10 (see FIG. 10): In this state, R
Rapid heating by TA (Rapid Thermal Annealing) method is performed. That is, in FIG. 15, reference numeral 105 denotes a light source for emitting sheet-like annealing light, which is constituted by a set of a xenon (Xe) arc lamp 106 and a reflecting mirror 107 surrounding the same, which are vertically opposed to each other. I have. 10
8, 108 are rollers for transporting the substrate 1;
Is a preheater for preheating, and 110 is an auxiliary heater for preventing the heated substrate from being rapidly cooled and cracking.

In such a configuration, after the substrate 1 is preheated by the preheater 106, the sheet-shaped annealing light source 1
05 and heat-treat. The RTA conditions at this time are:
Heat source: Xe arc lamp, temperature: 700 to 950 ° C. (pyrometer), atmosphere: N ₂ , time: 1 to 3 seconds.
Heating by the RTA method uses a high temperature, but can be completed in a very short time, so that there is no fear that the substrate 1 is deformed.

If there is a concern about suddenly applying a high temperature to the substrate 1, the RTA may be performed a plurality of times. That is, the time of each time is set to 1 to 3 seconds, and the temperature is set to 400 ° C. for the first time to 700 to 950 for the last time for each time.
The temperature is increased stepwise as in ° C. More specifically,
In a nitrogen (N ₂ ) atmosphere, heating may be performed, for example, in six steps, and the processing temperature may be set to increase stepwise for each step. For example, first time (first time): 400 ° C. (pyrometer value, the same applies hereinafter) → second time: 500 ° C. → third time:
550 ° C. → 4th time: 600 ° C. → 5th time: 650 ° C. → final time (6th time): 700 ° C., and gradually raise the temperature. Thereby, it is possible to prevent the substrate from being warped or damaged. Each processing time is, for example, 1 to 3 seconds.

The temperature can be adjusted by turning on the Xe arc lamp for the first time, using the heat of the preheater, and changing the power of the Xe arc lamp in the range of 1 KW to 7 KW for the second and subsequent times. . Since the light heat of the Xe arc lamp is more strongly absorbed in the amorphous portion and the silicide portion than in the polycrystalline portion, only the necessary portion can be mainly heated, and the (gate) wiring has low resistance. Suitable for activation and activation of impurities. Also, as described later, W
Heating using the silicide film 2 can also be performed effectively.

The rapid heating activates the impurities in the source / drain regions 9 and polycrystallizes the amorphous silicon film 6a. Further, the polycrystalline silicon film 6a and the W silicide film 6b The sheet resistance of the gate electrode 6 having a polycide structure is about 20 to 22
Ω / □. The sheet resistance of the activated source / drain region 6 is also 1 to 1.5 k for the n-type.
Ω / □, 1-1.2 kΩ / □ for p-type, equivalent to high-temperature heat treatment by a diffusion furnace used in a high-temperature process.

Particularly, in this embodiment, the polycrystalline silicon film 4
In response to this, a W silicide film 2 is formed underneath. The W silicide film 2 has a function of absorbing the heat of the RTA, and the impurity of the polycrystalline silicon film 4 is activated also by the radiant heat from the W silicide film 2 that has absorbed the heat. That is, the polycrystalline silicon film 4 is directly and indirectly heated by the heat from the Xe arc lamp and the radiant heat from the W silicide film 2, so that the entire polycrystalline silicon film 4 is uniformly heated and activated. Is performed well without variation.

The size of the W silicide film 2 is basically
It may be the same as or larger than the polycrystalline silicon film 4, but it is more preferable to adjust the area so as to correspond to the large description of the pattern in the plane. That is, in the integrated semiconductor device, since the density of the pattern occurs on the substrate, if the W silicide film 2 is provided evenly on each transistor, the heat absorption rate per unit area varies depending on the location, and the uniform heat treatment is performed. In some cases, the temperature at a location where the W silicide film 2 is concentrated becomes extremely high, and the substrate 1 may be deformed. Therefore, if the density per unit area of the heat absorbing film arranged in the lower layer is made substantially constant irrespective of the pattern formed in the upper layer, the bias of the temperature distribution at the time of activation by RTA is eliminated. be able to. Specifically, in a driver-integrated LCD panel, the density of transistors in the pixel portion is lower than that in the driver portion.
W silicide film 2 corresponding to transistor in driver section
Is made smaller than that of the pixel portion, the temperature distribution of the entire substrate 1 becomes substantially uniform.

In the case of an LCD panel, the circuit area is about 1
It is preferable to adjust so that 0% becomes the W silicide film 2. By this step, the polycrystalline silicon TFT (TF
T: Thin Film Transistor (A) is formed. Next, the polycrystalline silicon TFT manufactured as described above
L having a transmission type configuration using (A) as a pixel driving element
The configuration of the pixel portion of the CD will be described with reference to FIG.

Step: Prior to forming the interlayer insulating film 11,
ITO is formed on the pixel area of the substrate 1 by sputtering.
(Indium Tin Oxide) storage electrode 12 of storage capacitor
To form Step: An insulating film 13 is formed on the entire surface of the device. As a material of the insulating film 13, a silicon oxide film, a silicate glass, a silicon nitride film, or the like is used.
The VD method or the PVD method is used.

Next, a contact hole for contacting the source / drain electrode 14 is formed in the insulating film 13, an ITO film is formed by sputtering on the entire surface of the device including the contact hole, and the ITO film is patterned. Thus, the display electrode 15 is formed. Step: A transparent insulating substrate 1 on which a polycrystalline silicon TFT (A) is formed and a transparent insulating substrate 17 having a common electrode 16 formed on the surface thereof are opposed to each other, and a liquid crystal is sealed between the substrates 1 and 17. Thus, a liquid crystal layer 18 is formed. As a result, the pixel portion of the LCD is completed.

Next, FIG. 12 shows a block diagram of an active matrix type LCD in this embodiment. In the pixel section 19, each scanning line (gate wiring) G1... Gn, Gn + 1.
m and each data line (drain wiring) D1... Dn, Dn + 1. Each gate line and each drain line are orthogonal to each other, and the pixel 20 is provided at the orthogonal portion. Each gate wiring is connected to a gate driver 21 so that a gate signal (scan signal) is applied. Each drain wiring is connected to a drain driver (data driver) 22, and a data signal (video signal) is applied. A peripheral drive circuit section 23 is configured by these drivers 21 and 22.

An LCD in which at least one of the drivers 21 and 22 is formed on the same substrate as the pixel section 19 is generally a driver integrated type (driver built-in type).
It is called LCD. Note that the gate driver 21 may be provided at both ends of the pixel unit 19 in some cases. Further, the drain driver 22 may be provided on both sides of the pixel portion 19 in some cases.

The switching element of the peripheral drive circuit section 23 also uses a polycrystalline silicon TFT prepared by the same manufacturing method as that of the polycrystalline silicon TFT (A), and is used for producing the polycrystalline silicon TFT (A). In parallel, they are formed on the same substrate. The polycrystalline silicon TFT for the peripheral drive circuit section 23 employs a normal single drain structure instead of an LDD structure (of course, it may have an LDD structure).

The polycrystalline silicon TFT of the peripheral drive circuit section 23 is formed in a CMOS structure,
The size of each of the drivers 21 and 22 is reduced. FIG. 13 shows an equivalent circuit of the pixel 20 provided at a portion orthogonal to the gate line Gn and the drain line Dn.

The pixel 20 has a TFT as a pixel driving element.
(Same as the thin film transistor A), a liquid crystal cell LC, and an auxiliary procedure CS. The gate of the TFT is connected to the gate wiring Gn, and the drain of the TFT is connected to the drain wiring Dn. And the source of the TFT is
The display electrode (pixel electrode) of the liquid crystal cell LC is connected to an auxiliary capacitance (storage capacitance or additional capacitance) CS.

The liquid crystal cell LC and the auxiliary capacitance CS constitute a signal storage element. The voltage Vcom is applied to the common electrode (the electrode on the opposite side of the display electrode) of the liquid crystal cell LC. On the other hand, in the auxiliary capacitance CS, a constant voltage VR is applied to the electrode on the side opposite to the side connected to the source of the TFT. The common electrode of the liquid crystal cell LC is an electrode that is literally common to all the pixels 20. Further, a capacitance is formed between the display electrode and the common electrode of the liquid crystal cell LC. Incidentally, in the auxiliary capacitance CS,
The electrode on the side opposite to the side connected to the source of the TFT may be connected to the adjacent gate line Gn + 1 in some cases.

In the pixel 20 configured as described above,
When a positive voltage is applied to the gate of the TFT by setting the gate line Gn to a positive voltage, the TFT turns on. Then, the capacitance of the liquid crystal cell LC and the auxiliary capacitance CS are charged by the data signal applied to the drain wiring Dn. Conversely, when the gate line Gn is set to a negative voltage and a negative voltage is applied to the gate of the TFT, the TFT is turned off, and the voltage applied to the drain line Dn at that time changes the capacitance and the auxiliary capacitance of the liquid crystal cell LC. And CS. In this manner, by supplying a data signal to be written to the pixel 20 to the drain wiring and controlling the voltage of the gate wiring, the pixel 20 can hold an arbitrary data signal. The liquid crystal cell L according to the data signal held by the pixel 20
The transmittance of C changes, and an image is displayed.

Here, important characteristics of the pixel 20 include a writing characteristic and a holding characteristic. What is required for the writing characteristics is that a desired video signal voltage is sufficiently written to the signal storage elements (the liquid crystal cell LC and the auxiliary capacitance CS) within a unit time determined by the specifications of the pixel portion 19. Is that it can be done. What is required for the holding characteristic is whether or not the video signal voltage once written in the signal storage element can be held for a required time.

The auxiliary capacitance CS is provided to increase the capacitance of the signal storage element to improve the writing characteristics and the holding characteristics. That is, the liquid crystal cell LC
However, due to its structure, there is a limit to the increase in capacitance. Therefore, the shortage of the capacitance of the liquid crystal cell LC is compensated for by the auxiliary capacitance CS. Here, FIG. 18 is a plan view showing a region where a W silicide film 62 which is a heat absorbing film is provided.

As shown in the figure, the W silicide film 62 is provided in substantially the same region as the polycrystalline silicon film 64 (indicated by hatching in the figure). In the figure, 74 is a source / drain electrode, 75 is a pixel electrode, 80 is a drain line, and 81 is a gate line. In the peripheral drive circuit section,
Since the semiconductor film is denser than the pixel portion, the heat absorbing film is preferably provided with a smaller size in the semiconductor film region.

FIG. 19 is a plan view showing another example of the heat absorbing film according to the present invention. Referring to FIG.
Is provided only in the portion of the channel portion 64a (shown by hatching in the figure) of the polycrystalline silicon film. In the integrated semiconductor device, as described above, since the density of the pattern occurs on the substrate as described above, if the W silicide film 62 is provided evenly on each transistor, the heat absorption rate per unit area varies depending on the location and the uniformity. Heat treatment cannot be performed, and the temperature at the location where the W silicide film 62 is concentrated becomes extremely high, so that the substrate 61 may be deformed.

Therefore, if the density per unit area of the heat absorbing film 62 arranged in the lower layer is made substantially constant irrespective of the pattern formed in the upper layer, the temperature distribution in the case of activation by RTA can be improved. The bias can be eliminated. In a driver-integrated LCD panel as in the present embodiment, the density of the transistors (A) in the pixel section 19 is lower than that in the peripheral drive circuit section 23, and therefore, the W corresponding to the transistor (A) in the peripheral drive circuit section 23 is low . By making the area of the silicide film 62 smaller than that of the pixel portion, the temperature distribution of the entire substrate 61 becomes substantially uniform.

In the LCD panel, the peripheral driving circuit 23
Does not require a light-transmitting property, the adjustment range of the size of the W silicide film 62 in this portion is from 0 to the peripheral drive circuit unit 2.
Up to all three areas are possible. FIG. 20 is a plan view for explaining the area ratio of the heat absorbing film in the pixel portion, the peripheral driving circuit portion, and other regions.

As described above, it is preferable that the heat absorbing film is provided substantially uniformly over the entire substrate 61. Pixel section 2
0, it is preferably 0.01% to 60% of the area of the entire circuit section, more preferably 10% to 50%.
It is preferably from 0.01% to 60%, more preferably from 10% to 50%. In the region 25 other than the pixel portion 20 and the peripheral drive circuit portion 24, the total area is 0.01%.
% To 60%, more preferably 10% to 50%.

In the above embodiment, the size of the W silicide film 2 may be basically the same as or larger than that of the polycrystalline silicon film 4, but corresponds to the size of the pattern in the plane. It is more preferable that the area be adjusted so as to have a predetermined area. Further, in the LCD panel, since the peripheral drive circuit section 23 does not need to have a light-transmitting property, the adjustment range of the size of the W silicide film 2 in this portion can be from 0 to the entire area of the peripheral drive circuit section 23.

In addition to the method of changing the area of the W silicide film 2, there is a method of changing the film thickness. When W silicide is used, the film thickness is 200 ° to 1000 °, and more preferably, the region where the density of the semiconductor element is high is 200 ° to 300 °.
{The region where the density of the semiconductor element is low is 400Å to 600Å.
When amorphous silicon is used, 1000Å
４4000 °, more preferably 2,000Å-3
000. In any case, the thickness of the high-density region may be about half the thickness of the low-density region.

As described above, the polycrystalline silicon TFT manufactured according to the present embodiment can be performed by a so-called low-temperature process, and uses a high-quality polycrystalline silicon film as an active layer. According to experiments performed by the present inventors, the mobility μn of the n-channel MOS-type polycrystalline silicon TFT is 200 cm ² / VS or more, and the mobility μp of the p-channel MOS-type polycrystalline silicon TFT is 150 cm ² / V. V
It has been found that a transistor with a high performance of S or higher can be realized.

[0064] In such a high-performance TFT, for ^{example, μn = 50cm 2 / V ·} S, μp = 20cm 2 / V ·
It is fully applicable to an NTSC television signal display LCD panel requiring S, and μn = 50 cm ² / V ·
S, μp = 20 cm ² / V · S, threshold voltage: 2 V
(N channel), -5V (p channel), S value (Sub-th
characteristics (reshold swing): 0.2 V / decade and an on / off ratio of 1 × 10 ⁷ can be obtained.

The higher the mobility, the higher the driving capability of the TFT. Therefore, the size of the TFT can be reduced, and the size (W / L = 34) of a conventional transistor using amorphous silicon as an active layer. / 10 μm).
/ 8 or less (W / L = 8/5 μm). Further, since the active layer is a high-quality active layer, the leakage current when the transistor is turned off is small, and the area of the auxiliary capacitance can be reduced to 1/3 or less.

More specifically, the size is 2.4 type, the pixel pitch is 50.0 (H) μm × 150 (V) μm, and the number of pixels is:
230,000 dots (320 × 3 (RGB) × 240), which has a high aperture ratio of 55% (1.5 times the conventional ratio) while having three times or more high-density pixels compared to the conventional panel. Can be obtained, and high luminance can be realized. The above embodiment may be modified as follows, and the same operation and effect can be obtained in such a case.

1) Instead of the W silicide film 2, a semiconductor film such as an amorphous silicon film or a polycrystalline silicon film is used. These silicon films may be doped with impurities. As described above, by using a conductive film or a semiconductor film, by applying a voltage to this heat absorbing film, the TF
When T is operated as a four-terminal device like a MOS transistor used for an LSI, the threshold voltage can be controlled, and when a glass substrate is used,
Since the ions in the substrate are electrostatically shielded, deterioration of the characteristics of the transistor due to the ions in the glass substrate and adverse effects on the TFT due to the potential formed by the movable ions can be prevented.

2) Instead of the W silicide film 2, MoSi
₂ , refractory metal silicide such as TiSi ₂ , TaSi ₂ , CoSi ₂ and others, W, Mo, Co, Cr, Ti, T
A high melting point metal such as a may be used. Further, when the operating temperature is low (about 450 ° C. or lower), a so-called low melting point metal such as Al or Au may be used. Since these metal films including the W silicide film have a property of blocking light, they have the following effects.

A) Since the scattering of light is prevented and unnecessary light which tries to enter the liquid crystal cell obliquely is blocked, the contrast as an LCD device is increased. b) Since the light entering the TFT is blocked, the leakage current due to the light is reduced, the characteristics as the TFT are improved, and the deterioration of the TFT itself due to the light is prevented.

3) In step 4, the amorphous silicon film is formed by a low pressure CVD method using, for example, a monosilane gas.
Deposit at a temperature of 580 ° C. Thereby, the amorphous silicon film 4a becomes a film containing microcrystals. When the amorphous silicon film containing microcrystals is polycrystallized by a solid phase growth method, the mobility is slightly lowered by the reduction of the crystal grain size, but the crystal growth can be completed in a short time.

4) In the step 4, the amorphous silicon film 4
a is normal pressure C regardless of the reduced pressure CVD method or the plasma CVD method.
VD method, photo-excited CVD method, vapor deposition method, EB (Electron Bea
m) It is formed by any one of a group consisting of a vapor deposition method, an MBE (Molecular Beam Epitaxy) method, and a sputtering method. 5) The portion corresponding to the channel region of the polycrystalline silicon film 4 is doped with impurities to control the threshold voltage (Vth) of the polycrystalline silicon TFT. In a polycrystalline silicon TFT formed by the solid-phase growth method, the threshold voltage of an N-channel transistor tends to shift in the depletion direction, and the threshold voltage of a P-channel transistor tends to shift in the enhancement direction. Further, when the hydrogenation treatment is performed, the tendency becomes more remarkable. In order to suppress the shift of the threshold voltage, the channel region may be doped with an impurity.

6) The following steps are performed in place of the step 5. Step 5a: By performing heat treatment in a nitrogen (N ₂ ) atmosphere at a temperature of about 600 ° C. for about 20 hours using an electric furnace,
The polycrystalline silicon film 4 is formed by solid-phase growth of the amorphous silicon film 4a. 7) The polycrystalline silicon film 4 formed in the step 5a has many defects such as dislocations in the crystal constituting the film, and there is a possibility that an amorphous portion may remain between the crystals. There is much fear.

Therefore, after the step 5a, the substrate 1 is rapidly heated by the RTA method or the laser annealing method to improve the film quality of the polycrystalline silicon film 2. 8) PVD other than the sputtering method in Steps 1 and 7
Methods (vacuum deposition, ion plating, ion beam deposition, cluster ion beam, etc.)
Is used to form W silicide films 2 and 6b. Also in this case, for the same reason as in the case of the above-described sputtering, setting the composition of the W silicide (WSi _X) to X> 2.

9) In the steps 1 and 7, the CVD method
To form W silicide films 2 and 6b. Its source
As the gas, tungsten hexafluoride (WF₆) And Shira
(SiH_Four) May be used. The deposition temperature is 350-
It should be around 450 ° C. In this case, too,
W silicide (WS
i _X) Is set so that X> 2. CVD method is PVD method
W silicide film due to better step coverage than
Can be made more uniform.

10) The present invention is applicable not only to a planar type but also to a polycrystalline silicon TFT having any structure such as an inverted planar type, a staggered type and an inverted staggered type. 11) The present invention is applied not only to polycrystalline silicon TFTs but also to insulated gate semiconductor devices in general. In addition, photoelectric conversion elements such as solar cells and optical sensors, bipolar transistors, and static induction transistors (SITs)
or) for any semiconductor device using a polycrystalline silicon film.

[0076]

According to the present invention, the following excellent effects can be obtained. 1) Due to the presence of the heat absorbing film, an activated state of the impurity region is uniform and a semiconductor device of excellent quality can be obtained. 2) A semiconductor device having a high-quality semiconductor film can be obtained in a short time.

3) It is possible to provide a display device such as an LCD device having excellent display performance. 4) Deformation of the substrate during heat treatment can be prevented.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining a manufacturing process according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view for explaining a manufacturing process according to one embodiment of the invention.

FIG. 3 is a cross-sectional view for explaining a manufacturing process according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view for explaining a manufacturing process according to an embodiment of the present invention.

FIG. 5 is a cross-sectional view for explaining a manufacturing process according to one embodiment of the invention.

FIG. 6 is a cross-sectional view for explaining a manufacturing process according to one embodiment of the invention.

FIG. 7 is a cross-sectional view for explaining a manufacturing process according to one embodiment of the invention.

FIG. 8 is a cross-sectional view for explaining a manufacturing process according to an embodiment of the present invention.

FIG. 9 is a cross-sectional view for explaining a manufacturing process according to one embodiment of the invention.

FIG. 10 is a cross-sectional view for explaining a manufacturing process according to one embodiment of the invention.

FIG. 11 is a schematic cross-sectional view for explaining a method for manufacturing the pixel portion of the LCD.

FIG. 12 is a block diagram of an active matrix type LCD.

FIG. 13 is an equivalent circuit diagram of a pixel.

FIG. 14 is a configuration diagram of an excimer laser annealing apparatus.

FIG. 15 is a configuration diagram of an RTA apparatus.

FIG. 16 is a cross-sectional view for explaining a manufacturing process of a conventional example.

FIG. 17 is a cross-sectional view for explaining a manufacturing process of a conventional example.

FIG. 18 is a plan view showing an example of a region where a heat absorbing film is formed in the present invention.

FIG. 19 is a plan view showing another example of a region where a heat absorbing film is formed in the present invention.

FIG. 20 is a plan view illustrating an area ratio of a heat absorbing film in a pixel portion, a peripheral driving circuit portion, and other regions on a substrate according to the present invention.

[Explanation of symbols]

 Reference Signs List 1 insulating substrate 2 W silicide film (heat absorbing film) 3 insulating thin film (insulating film) 4 polycrystalline silicon film (semiconductor film) 5 LTO film (gate insulating film) 6 gate electrode 9 impurity region A TFT (semiconductor element, semiconductor) Switching element) 62 W silicide film (heat absorption film)

Continuation of the front page (51) Int.Cl. ⁷ Identification symbol FI H01L 27/12 G02F 1/136 500 H01L 21/88 S (72) Inventor Yoshihiro Morimoto 2-5-5 Keihanhondori Moriguchi-shi, Osaka Sanyo Inside Electric Co., Ltd. (72) Inventor Kiyoshi Yoneda 2-5-1-5, Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (56) References JP-A-5-53143 (JP, A) JP-A-59- 110114 (JP, A) JP-A-6-34997 (JP, A) JP-A-2-194626 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/786 G02F 1 / 1368 H01L 21/336 H01L 27/12 H01L 21/20 H01L 21/3205

Claims (8)

(57) [Claims] 2. A semiconductor device comprising: a plurality of semiconductor elements integrated on a substrate;
A semiconductor device , wherein the plurality of semiconductor elements include a plurality of first semiconductor elements having a heat absorbing film and a plurality of second semiconductor elements not having a heat absorbing film, and a distribution of the semiconductor elements on the substrate. According to the state, the second semiconductor element is relatively integrated at a place where the semiconductor elements are relatively densely packed, and the first semiconductor element is placed at a place where the semiconductor element is relatively small. A relatively large number of integrated semiconductor devices . 2. A driver-integrated display device in which a pixel portion and a peripheral drive circuit portion are formed on the same substrate. A heat absorbing film formed on the substrate and a heat absorbing film formed on the heat absorbing film. A semiconductor switching element including a semiconductor film, a gate electrode formed on the semiconductor film via a gate insulating film, and an impurity region formed in the semiconductor film, a pixel driving element in the pixel portion; Used as a peripheral drive circuit element in the peripheral drive circuit section,
A display device, wherein the heat absorption effect of the heat absorption film located in the peripheral drive circuit portion is adjusted to be lower than the heat absorption effect of the heat absorption film located in the pixel portion . 3. A driver-integrated display device in which a pixel portion and a peripheral driving circuit portion are formed on the same substrate, wherein a pixel driving element provided in the pixel portion and a peripheral driving circuit portion are provided in the peripheral driving circuit portion. Peripheral driving circuit element, wherein the pixel driving element and the peripheral driving circuit element are configured by a semiconductor switching element, wherein the semiconductor switching element is a heat absorbing film formed on the substrate, A semiconductor film formed on the heat absorbing film, a gate electrode formed on the semiconductor film via a gate insulating film, and an impurity region formed on the semiconductor film, provided in the pixel portion. The ratio of the area or the thickness of the heat absorbing film to the semiconductor film is compared with the ratio of the area or the thickness of the heat absorbing film provided in the peripheral drive circuit portion to the semiconductor film. Setting the display device to hear. 4. An area of the heat absorbing film in the pixel portion,
The display device according to claim 3, wherein the area is set to be 0.01% to 60% of the area of the entire pixel unit. 5. The area of the heat absorbing film in the peripheral drive circuit section is 0.01 to 60% of the total area of the peripheral drive circuit section.
The display device according to claim 3, wherein the display device is set to: 6. the area of the heat absorption layer is set to be 0.01 to 60% of the area of the entire substrate 請
The display device according to claim 3 . 7. The display device according to claim 2 , wherein the substrate is one of a pair of substrates provided to face each other with a liquid crystal layer interposed therebetween. 8. A display device in which a plurality of semiconductor elements are integrated on a substrate, wherein the plurality of semiconductor elements have a plurality of first semiconductor elements having a heat absorbing film and a plurality of first semiconductor elements having no heat absorbing film. The second semiconductor element is relatively integrated at locations where the semiconductor elements are relatively dense and dense, in accordance with the distribution state of the semiconductor elements on the substrate, A display device having a relatively large number of the first semiconductor elements integrated in a place where the number of semiconductor elements is relatively small.