TW578309B - Manufacturing method of low temperature poly-silicon thin-film transistor - Google Patents

Abstract

A kind of manufacturing method of low temperature poly-silicon (LTPS) CMOS process for thin-film transistor (TFT) is provided. The method comprises forming a poly island as an N-TFT and a P-TFT on an insulative substrate; sequentially depositing a gate insulation layer and a gate metal layer on the insulative substrate; patterning the gate metal layer to form a gate metal of the N-TFT and the gate metal mask of the P-TFT; using the gate metal of the N-TFT and the gate metal mask as a mask to perform N- ion implantation step onto the poly island to form the N- region of the N-TFT; forming a resist pattern on the gate metal of the N-TFT and the gate metal mask of the P-TFT, in which a portion of the resist pattern defines the gate metal of the P-TFT, and another portion of the resist pattern covers the gate metal of the N-TFT and the adjacent portion of the gate insulation layer surface to define the LDD structure of the N-TFT; performing an N+ ion implantation on the poly island to form the source/drain (S/D) region of the N-TFT; etching the portion of the gate metal mask not covered by the resist pattern to form the gate metal of the P-TFT; using the resist pattern and the gate metal of the P-TFT as a mask to perform p+ ion implantation on the poly island to form the S/D region of the P-TFT; stripping the resist pattern; and forming the S/D metal gates of the N-TFT and the P-TFT.

Description

578309 V. Description of the invention (l) The technical field to which the invention belongs: m About a low-temperature polycrystalline silicon (LTPS) thin-film transistor technology, especially a method for improving the manufacturing process of a low-temperature polycrystalline silicon thin-film transistor. At first glance: With the rapid advancement of thin-film transistors (TFTs) manufacturing technology, liquid crystal displays (LCDs) with the advantages of lightness, thinness, power saving, and frameless rays have been widely used. Used in various electronic products such as computers, personal digital assistants (PD A), watches, notebook computers, digital cameras, digital cameras, LCD monitors, and mobile phones. Coupled with the industry's active investment in research and development and the use of large-scale production equipment, the production cost of liquid crystal displays has continued to drop, and the demand for liquid crystal displays has increased significantly. Current TFT LCDs are divided into two types: amorphous silicon (a-Si) thin film transistor liquid crystal display and poly-Si (poly-Si) thin film transistor liquid crystal display. Low Temperature Poly-Silicon (LTPS) is a new generation of thin-film transistor liquid crystal display manufacturing process. The so-called low-temperature poly-silicon (LTPS) technology mainly uses a laser annealing process (Laser Anneal) to transform a-Si films into Poly-Si thin film layer. Polycrystalline silicon's electrons move 100 times faster than amorphous silicon, which has the advantages of fast display, high brightness and high resolution; in addition,

578309

With a fast moving speed, Poly-Si can be used as a driving circuit, so peripheral driving circuits can be fabricated on a broken glass substrate to reduce its weight and meet the requirements for lightness and thinness. In addition, because the LTPS TFT integrates the driver IC in the LCD panel, it can reduce the 1C cost and reduce the rate of IC post-processing, so the yield can be improved. In the low-temperature polycrystalline silicon process, we must also take into account the component characteristics of the internal circuit of the element ... At the same time, it can improve the drive and reduce the leakage current of the pixel. A lightly doped drain is a better circuit design. It can reduce the degradation caused by thermal conduction mN or circuit, and can further reduce the leakage / melon at the rate of negative bias and the generation rate of holes and holes to maintain the characteristics of the components required to drive the LCD. Please refer to Figure-A to Figure 1K. These diagrams are the conventional technology :: t0p gate LTPS simplified process (peripheral driver schematic. ☆ In the first conventional technology, a total of / 1 first mask is used. The CM0S N-TFT to make the peripheral driving circuit has an LDD structure. As shown in FIG. 1A, first, an insulating substrate (such as glass beauty =; = Γ and an amorphous stone film layer 3 ′ The effect of Buffer 2 is ΐ Ϊ ί Ϊ 的 1 Impurities in Ϊ1 are diffused due to subsequent high-temperature processes. In turn, excimer laser technology (Excimer; el 578309) is used.

τ = 4 amorphous layer 3, which makes the amorphous silicon crystal become polycrystalline silicon and / overnight: silicon film layer 3 '. After that, a lithography etching process is performed, as shown in FIG. 1, a first photoresist pattern 4 (using a first channel mask) is used to pattern the polycrystalline silicon film layer 3 on the substrate 1 to form two FT and A poly island 5 of the P-TFT and a gate insulating layer 6 are deposited in parallel, as shown in the figure. Connect = come: N-TFT N + ion implantation steps are performed, as shown in Figure 1]), forming a resist pattern 7 (using a second mask) on the gate insulating layer 6 ^ ', where the second The photoresist pattern 7 will be located in the LDD structure and gate region of the N-TFT, the polycrystalline silicon island 5 is partially covered, and the polycrystalline silicon island 5 is partially covered in the entire P-TFT region. Then, N + ion implantation is performed on the polycrystalline silicon island 5 to form an N / TFT S / D region 8. Then, the second photoresist pattern 7 is peeled off, and a gate metal layer 9 is deposited. As shown in FIG. E ', the photolithography | worming process is performed again, and a third photoresist pattern 10 (using the third Mask), the gate metal layer 9 is patterned to form gate metal 9 of N-TFT and P-TFT, as shown in FIG. 1F. After that, the gate metal 9 is directly used as a mask to perform the N-ion implantation step to form the LDD structure 11 of the N-TFT. Then, as shown in FIG. 1G, a fourth photoresist pattern is formed (using a fourth photomask) to cover the entire N-TFT region, and a P + ion implantation step is performed on the P-TFT region to form P -S / D region 14 of the TFT. So far,

578309 V. Description of the invention (4) Asia Taxi, the master of N-TFT and P-TFT. 1, 丄 ~ Wang Yao's structure has been roughly completed. Next, the glass substrate 12 and the substrate are not shown in the figure. Then connect the metal, make the electrode 5 1, the prime region 'strip the fourth photoresist pattern 1 3, and A dielectric layer 12 is deposited on the plate 1 and covers the gate metal 9, and then a lithographic etching process is performed on the dielectric layer insulating layer 6, and a photoresist pattern is used. Fifth photomask), forming the N-TFT and p-TFT, 50 'to expose the S / D of the N-TFT and P-TFT, as shown in Figure 1, accumulate a metal layer and fill the first The interlayer hole 50 is then subjected to an etching process of the layer. A photoresist pattern (not shown, sixth = photomask) is used to form N-TFT and P-TFT S / D metal electrodes. The data line (data Hne) is connected to the image on the LCD panel and the circuit outside the panel, as shown in FIG. Process, by a photoresist pattern

Metal electrode ". Alas, deposit the exposed S / D second interlayer hole 53 of the indium difluoride, and then fill the indium tin oxide drawer '30) and fill the pass-resistance pattern f (not shown in the figure, In the process of engraving the film name, the ITO connection electrode 54 can be connected to the outer edge of the LCD panel = photomask) to form -K. B. The circuit of P is connected as shown in the figure. Please refer to Figure 2A to Figure 2. Second, the 笤 ## diagram is a conventional technique. There are 578309, invention description (5) self-aligned top gate LTPS CMOS process is different from the "first technique" process flow diagram. . In the conventional technique two, first, the phase to be formed as the N-TFT and the P-TFT in the steps of Gang-A to FIG. 1c ^ is a Si-crystalline silicon island (P〇1 yis 1 and) 5; After depositing the gate insulation, as shown in FIG. 2A, a gate metal layer 19 is deposited on the gate insulation layer 6 and then a lithography process is performed to pass a second photoresist pattern 1 7 (Using a second mask), patterning the gate metal layer 19 to form a gate metal 19 of the 1-TFT, and a gate metal cover 19 "of the P-TFT, and peeling the first Two photoresist patterns 17, as shown in FIG. 2B, in which the gate metal cover i 9t will completely cover the part of the polycrystalline silicon island 5 in the entire P-TFT region. Then, the gate is directly used. The metal 19 and the gate metal cover 9 are used as a mask to perform the N + ion implantation step to form the S / D region 18 of the N-TFT. Next, the P + TFT P + ion implantation step is performed, such as As shown in FIG. 2c, a second photoresist pattern 20 (using a third photomask) is formed on the gate metal 19 and the gate metal cover 19 ", wherein the third photoresist pattern 20 will be at p —Tft gate metal The polycrystalline silicon island 5 part in the 19 'region and the polycrystalline silicon island part 5 in the entire N-TFT region are covered, and then the gate electrode not covered by the first photoresist pattern 20 is covered. The metal cover 19 "is partially etched away, and a gate metal 19 is formed into the P-TFT, and then the polycrystalline silicon island 5 is ion-implanted to form the S / D region 24 of the P-TFT. After that, The third photoresist pattern 20 is stripped, as shown in FIG. 2D. This conventional technique 2 is performing a third light

578309 V. Description of the invention (6) ~ After the mask, the main structures of N-TFT and P-TFT have been completed. Next, using the same steps as in the foregoing FIG. 1 to FIG. 1 κ, four photomasks are used to form the S / D metal electrodes 51 and ITO connection electrodes 54 of the N-TFT and P-TFT. In the conventional technology 2, Although only a total of seven photomasks are used to make a CMOS TFT element, the N-TFT produced does not have an LDD structure. Summary of the invention: The main purpose of the present invention is to provide a method for improving the CMOS process of a low-temperature polycrystalline silicon thin film transistor, which can reduce the number of photomasks used in the CMOS process and simultaneously produce N with an LDD structure. —Mos circuit design. The invention discloses a method for fabricating a low-temperature polycrystalline silicon thin film transistor. First, a polycrystalline silicon island (Nu-TFT and P-TFT) is formed on an insulating substrate. A gate insulating layer and a gate metal layer are sequentially deposited on the insulating substrate; thereafter, the gate metal layer is patterned to form the gate metal of the N-TFT and the gate metal cover of the p_TFT, wherein, The gate metal cover completely covers the portion of the polycrystalline silicon island in the entire area. Next, the gate metal of the N-TFT and the gate metal cover are used as the cover | A N-ion implantation step is performed to form the N-region of ^ 71 ^; and then a

Page 10 578309 V. Description of the invention (7) The photoresist pattern is on the gate metal of the N-TFT and the gate metal cover of the P-TFT, and a part of the photoresist pattern defines the gate of the p-TFT Metal, and another part of the photoresist pattern covers the gate metal of the N-TFT and the surface of the adjacent gate insulating layer to define the LDD structure; then the polycrystalline silicon island N + ion implantation is performed to form the S / D region of the n-TFT, and the gate metal cover portion that is not covered by the photoresist pattern is etched to form the gate metal of the P-TFT. Next, using the photoresist pattern and the gate metal of the P-TFT as a mask, P + ion implantation is performed on the polycrystalline silicon island to form the S / D region of the P-TFT, and then the photoresist is removed Pattern; S / D metal electrodes of the N-TFT and the P-TFT are then formed. In the above manufacturing method, the step of forming the photoresist pattern on the closed metal of the N-tft and the gate metal cover of the P-TFT is performed by forming the gate metal of the N-TFT. The position of the upper photoresist pattern is symmetrical or asymmetric with the gate metal of ^ 71 ^, which can form a symmetrical or asymmetrical n / tft S / D region.

Furthermore, the present invention further discloses a manufacturing method of an LTPS CMOS that defines an N-τρ structure by an etching method. First, polycrystalline islands (poly islands) to be used as _n —ding ^ a P —TFT are formed on an insulator, and then a gate insulating layer and a gate metal layer are sequentially deposited on Second _ soil. After that, the gate metal layer is patterned.

^ t.N-TFT,: 'The TFT metal cover will be in the polycrystalline island state of the " FT region ::;

Page 11 578309

Full mask; Next, the gate metal mask of the P-TFT is used as a curtain, and the polycrystalline stone island is charged into the polycrystalline silicon / closed metal.

On the closed metal and the closed metal cover 1 = pattern on the P-TFT P-TFT area and the gate metal of the N-TFT ^ "The resistance pattern covers the entire ^ 1 generature and structure area. , The etching is not covered by the photoresist pattern, ^ ^ N-TFT ^ ^ ^ Λ Λ " ^ ^ ^ ^ # n + ^ ^ ^^ n; tf ^ t is; D ^ # v ^ ^ 1 ύ / U Area, virtue, with the ancient female light ^ pattern as the screen, facing the side of the metal shield of the two poles. 〆w, engraving the surname, so that the second idler metal shield of two: Λ into the N_m of Idle metal, at the same time define the ",", "0" structure region of the "FT." Then strip the photoresist pattern and use the n_tft gate metal as a cover I 'to perform N-ion on the polycrystalline island Planting, forming the LDD structure of the N TFT, and then forming the S / D metal electrode of the N-TFT and the p-TFT. Embodiments: Please refer to FIG. 3A to FIG. 3G, which are drawings of the present invention. The first embodiment of the CMOS fabrication method of a low temperature polycrystalline stone (LTPS) thin-film transistor is different from the schematic flowchart of the conventional technology. First, the steps are the same as those in FIG. 1A to FIG. 1 ,form Polycrystalline silicon island to be used as N-TFT and P-TFT ^ 78309

Then, the gate insulating layer 6 is deposited. Lu 6 ^ shown in Figure 3A 'deposit a closed metal layer 29 on the gate insulation 7 to make a photolithographic etching process, and then use a second photoresist pattern 27 to form a second mask of N-τΐτ), The gate metal layer 29 is patterned to form a gate metal 29 of T-, and a gate metal cover 29 "of p_TFT, and the first photoresist pattern 27 of M" It is peeled off, as shown in Figure 3B. As shown in the figure, the gate metal covers: a part of the polycrystalline silicon island 5 in the entire P-TFT region is completely covered. ^ 'Figure 2B' is a plan view of Figure 3 β. After that, the gate gold-9 and the gate metal cover 29 ″ are directly used as a mask, and an ion implantation step is performed on the polycrystalline silicon island to form an N-region 21 of the N-TFT, as shown in FIG. 3c. 〇 ran f 'N-TFT N + ion implantation step, as shown in Figure 3D, forming a second photoresist pattern 30 (using a third mask) on the gate metal 29,

And the gate metal cover 29π, wherein the third photoresist pattern 30 will be in the polysilicon island 5 part of the gate metal 2 9 'region of the p-TFT and the gate metal 2 in the ν-TFΤ 9 'and the LDD structure region of the polycrystalline silicon island 5 is partially covered (at this time, the length of the LDD structure is precisely defined), and then the polycrystalline silicon island 5 is subjected to N + ion implantation, The S / D region 28 and the LDD structure 21 of the ν-TFT are formed at the same time, as shown in FIG. 3E. Then, the gate metal cover 29π which is not covered by the third photoresist pattern 30 is partially etched away to form a gate metal 29 of the P-TFT, as shown in FIG. 3F.

Page 13 578309 V. Description of the Invention (（), and then, using the third photoresist pattern 30 and the gate metal 29 as a mask, P + ion implantation is performed on the polycrystalline silicon island 5 to form The S / D region 34 of the P-TFT is then stripped of the third photoresist pattern 30, as shown in FIG. 3G, and FIG. 3G is a plan view of FIG. 3G. It is worth noting that when performing P + ion implantation, the S / D region 28 (ie, the N + region) of the N-TFT is counter-doping. Therefore, the N + dose and The p + dose must be properly adjusted so that the N + region of the ~ -TFT will still maintain the "doping type and low resistance value characteristics" after the P + ion implantation step.

So far, the LTPS CMOS process of the present invention has been carried out (three masks are used), and the main structures of the N-TFT and P-TFT have also been roughly completed. Next, the steps are the same as the steps in FIG. 1 to FIG. 1K. Four photomasks are used to form the S / D metal electrodes 51 and ITO connection electrodes 54 of the N-TFT and P-TFT. S / D area of N-TFT: L, T:: ^ / Mingji's second and second implementation state can be implemented asymmetrically

In the second embodiment, most of the methods for manufacturing the LTPS CMOS are the same as the steps of the first embodiment of the present invention, but when the N + TFT N + ion implantation step is performed (ie, the first Three photomasks) to make the position of the third photoresist pattern 40 on the gate metal 29 of the N TFT asymmetric = the gate metal 29, as shown in FIG. The LDD structure 31 in the drain region is longer than the LDD structure 31 in the source region.

Page 14 578309 5. Description of the invention (π) "Long; In other words, the S / D region 38 of the N-TFT appears asymmetry, as shown in Figure 4B, and Figure 4B 'is a plan view of Figure 4B . In addition, please refer to FIG. 5A to FIG. 5G, which are the third embodiment of the CMOS manufacturing method of the low temperature polycrystalline silicon (LTPS) thin film transistor according to the present invention. ^ Similarly, the same polysilicon islands 5 (P0ly isiand) 5 to be used as N-TFT and P-TFT are formed by the same steps as in FIG. 1A to FIG. 1C, and the gate insulation is then deposited. Layer 6. Then, as shown in FIG. 5A, a gate metal layer 39 is deposited on the gate insulating layer 6 ', and then a photolithography process is performed, and a second photoresist pattern 37 is used (a second photomask is used). , Patterning the gate metal layer 39 to form the gate metal 39 of the P-TFT, and the first gate metal cover 39 ″ of the N-TFT, and stripping the first photoresist pattern 37, such as As shown in FIG. 5B, the gate metal cover 39π will completely cover the part of the polycrystalline silicon island 5 in the entire N-TFT region. Then, the gate metal 39 and the first gate are directly The metal cover 39 is used as a cover screen to perform a p + ion implantation step on the polycrystalline stone island to form the S / D region 44 of the P-TFT, as shown in FIG. 5C. Then, as shown in FIG. 5D As shown, a third photoresist pattern 4 5 (using a third mask) is formed on the gate metal 39 and the first gate metal mask 3 9π, wherein the second photoresist pattern 45 will be The polycrystalline island in the p-TFT region

Page 15 578309 V. Description of the invention (12) Part 5 and the gate metal 39 in the N_TFT, and the polycrystalline f island 5 part in the LDD structure area; then, it will not be covered by the third The first gate metal cover 39 covered by the photoresist pattern 45 is partially etched away to form an n_tft second gate metal cover 39 ′, where the second gate metal cover 39 ′ is The LDD structure area of the N-TFT is covered, and then N + ion implantation is performed on the polycrystalline silicon island 5 to form an N_TFTiS / D area 48, as shown in FIG. 5. Next, the third photoresist pattern is used. 45 is used as a cover screen, and an etching process is performed on the side wall (side waU) of the second gate metal cover 39, using dry engraving or wet etching technology to make the side wall of the second gate metal cover 39,. Shrink to form the gate metal 39 of the N-TFT, and also define the LDD structure region of the N-TFT in the polycrystalline stone island 5 as shown in FIG. After that, the second photoresist pattern 45 is peeled off, and N-ion implantation is performed on the polycrystalline silicon island 5 with the gate metal 39 of the N-TFT and P-TFT as a mask to form an N-TFT. The LDD structure 41 is shown in Fig. 5G. The third embodiment of the LTPS CMOS process of the present invention has been carried out (only three photomasks are used). The main structures of the N-TFT and P-TFT have been substantially completed. Similarly, in the same steps as in the foregoing FIG. 1 to FIG. 1 κ, four photomasks are used to form the S / D metal electrodes 51 and ITO connection electrodes 5 4 〇 of the N-TFT and P-TFT, and the conventional technique 1. Compared with the two, it can be seen that using the producer 578309 of the present invention 5. The invention description (13) method can reduce the number of LTPS CM0s processes of the conventional technology 1, and make a mask N- TFT. Therefore, the manufacturing method of the LTps CM0s of the present invention can reduce the cost and increase the production capacity by using the number of operations, and the operation of 提高 =: & can simultaneously improve the reliability of the driving circuit and reduce the leakage of pixels & While improving yield. One = the description is only a detailed description of the present invention through a preferred embodiment, and is not limited to the consumption of this au ', and those skilled in the art will understand, appropriate and = slight changes and adjustments will still be made The gist of the present invention does not depart from the spirit and scope of the present invention.

Page 17 578309

The drawings are simply explained. By combining the drawings with non-descriptive descriptions, the above-mentioned content and many advantages of the present invention can be understood, among which: Figures A through K are the conventional techniques-related self-alignment. The steps of the quasi-top gate LTPS CMOS process (peripheral driving circuit) are not intended. Figures 2A to 2D are the conventional self-aligned top interrogation LTPS CMOS process. Schematic diagram of the steps of the conventional technology one;

FIG. 3A to FIG. 3G are schematic diagrams of steps in a first embodiment of a CMOS manufacturing method of a low-temperature polycrystalline silicon (ltps) thin film transistor according to the present invention, which is different from the conventional technique; FIG. 3B ′ is FIG. 3 A plan view of B; FIG. 3G ′ is a plan view of FIG. 3G; FIGS. 4A to 4B ′ are a second embodiment of the CMOS manufacturing method of the low temperature polycrystalline silicon (LTps) thin film transistor of the present invention, which is different from the second embodiment Schematic diagram of the steps of the first embodiment; Figure 4B is a plan view of Figure 4B; and Figures 5A to 5G are the low temperature polycrystalline silicon ([TPS) thin film electrodes of the present invention.

The third embodiment of the CMOS fabrication method of the crystal is different from the steps in the conventional technology. Component drawing number description:

Page 578309 The diagram briefly explains the amorphous silicon film layer 3 first photoresist pattern 4 gate insulation layer 6 S / D region 8, 14, 18, gate metal layer 9, 1 9, third photoresist pattern 10 , 20, Gate metal 9 ', 19', LDD structure 11, 21 ', 41 Dielectric layer 1 2 S / D metal electrode 51 Second interlayer hole 5 3 Gate metal cover 19 ”, 29 > Area LDD structure 3 1 first gate metal cover 39π polycrystalline silicon film layer 3 'polycrystalline silicon island 5 second photoresist pattern 7, 17, 34, 44, 48 fourth photoresist pattern 1 3 first introduction Layer hole 5 0 Protective layer 5 2 ΙΤ Connection electrode 54 Ν-region 2 1 LDD structure of source region 31 ′ Second gate metal cover 3 9 ′ 27, 37 24, 28, 29, 39 30, 40, 45 29, 39,

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Claims (1)

578309 6. Scope of patent application 1. A method for manufacturing CMOS of a low temperature polycrystalline silicon (LTPS) thin film transistor, including: forming a polycrystalline silicon island (poli) to be used as an N-TFT and a P-TFT island) on an insulating substrate; sequentially depositing a gate insulating layer and a gate metal layer on the insulating substrate; patterning the intermediate metal layer to form the gate metal of the N_TFT and the P / TFT The idler metal cover, wherein the gate metal cover completely covers the part of the polycrystalline silicon island located in the entire P-TFT region; the gate metal of the N-TFT and the gate An electrode metal cover is used as a cover, and an N-ion implantation step is performed on β islands to form the N-region of the I-gawa; a photoresist pattern is formed on the gate metal of the N-TFT and The p-τί? Τ gate metal cover 'wherein a part of the photoresist pattern defines the gate metal of the p-TFT' and another part of the photoresist pattern covers the N-TFT Gate metal and adjacent gate insulation layer surfaces to define the LDD structure of the N — τ J? Τ; the polycrystalline silicon N + ion implantation was performed to form the n -TFT the S / D regions; Page 20 6. The scope of the patent application is to form the P + ion implantation using the photoresist pattern and the gate silicon island of the P-TFT, #,-, the screen, and the polycrystalline silicon to form the polycrystalline silicon. P —TFT's S / D region; stripping the photoresist pattern; and forming S / D metal electrodes of the N_TFT and the P-TFT. 2. The N + dose and P + dose as described in item 丨 of the patent application range are first passed through the method, where the area used is at the implantation step; and =, in order to make the N + TFT's N + value characteristics. N + doping type and low resistance are maintained 3. The photoresist pattern is applied to the gate metal of the N-TFT as described in item 1 of the scope of patent application. The step on the electrode metal cover is in phase with the Nm free-electrode metal; the position S / D area of the photoresist pattern on the metal.鸯 Symmetric 'so as to form a symmetrical N-TFT 578309 6. When applying for a patent, the position of the photoresist pattern formed on the open metal of the N-TFT is asymmetric to the gate of the N-TFT Metal in order to form the S / D region of the asymmetric N-TFT. 5. According to the manufacturing method described in claim 1 of the patent application scope, after forming the S / D metal electrodes of the N-TFT and the P-TFT, a step of forming an ITO connection electrode is further included. 6. The manufacturing method as described in item 1 of the scope of patent application, wherein a buffer layer is formed between the polycrystalline silicon island and the insulating substrate. 7. · A CMOS fabrication method for a low temperature polycrystalline silicon (LTPS) thin film transistor, including: forming a polycrystalline silicon island (Polily island) to be an N-TFT and a P-TFT on an insulating substrate; sequentially Depositing a gate insulating layer and a gate metal layer on the insulating substrate; patterning the gate metal layer to form a gate metal of the P-TFT and a first gate metal cover of the N-TFT, wherein The first gate metal cover completely covers the portion of the polycrystalline silicon island located in the entire N-TFT region; and the gate metal of the P-TFT and the first gate metal cover are used as the screen. Correct Page 22 578309 6. Application scope The polycrystalline silicon island is subjected to a P + ion implantation step to form the S / D region of the P-TFT; a photoresist pattern is formed on the gate metal of the P-TFT and the N- On the gate metal cover of the TFT, wherein the photoresist pattern covers the entire P-TFT region and the gate metal and LDD structure region of the N-TFT; etching the first gate not covered by the photoresist pattern The metal gate part forms the second gate metal cap of the N-TFT; N + ion implantation is performed on the polycrystalline silicon island to form the S / D region of the N-TFT; and the photoresist pattern is used as a mask , Performing an etching process on the side wall (si de wa 11) of the second gate metal cover, causing the side wall of the second gate metal cover to retract, thereby forming the gate metal of the N-TFT, and simultaneously defining The LDD structure region of the N-TFT; stripping the photoresist pattern; using the gate metal of the N-TFT as a mask, performing N-ion implantation on the polycrystalline silicon island to form the LDD structure of the N-TFT And forming an S / D metal electrode of the N-TFT and the P-TFT. Page 23 578309 6. The scope of the patent application is to carry out the manufacturing method described in item 7 of the 8-month n-f special range, in which two f's are used on the side wall of the second gate metal cover (si de wa 1 1). . 9. The manufacturing method according to item 7 of the scope of the patent application, wherein the side gate (side wal 1) of the second gate metal cover is etched by using a wet engraving technique. 10. According to the manufacturing method described in item 7 of the scope of patent application, after forming the S / D metal electrodes of the N-TFT and the P-TFT, a step of forming an IT0 connection electrode is further included.