JPS6315468A - Manufacture of thin film transistor - Google Patents

Manufacture of thin film transistor

Info

Publication number
JPS6315468A
JPS6315468A JP16030386A JP16030386A JPS6315468A JP S6315468 A JPS6315468 A JP S6315468A JP 16030386 A JP16030386 A JP 16030386A JP 16030386 A JP16030386 A JP 16030386A JP S6315468 A JPS6315468 A JP S6315468A
Authority
JP
Japan
Prior art keywords
thin film
film
transistor
oxygen plasma
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16030386A
Other languages
Japanese (ja)
Inventor
Yasushi Kubota
靖 久保田
Katsuji Iguchi
勝次 井口
Atsushi Kudo
淳 工藤
Masayoshi Koba
木場 正義
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP16030386A priority Critical patent/JPS6315468A/en
Publication of JPS6315468A publication Critical patent/JPS6315468A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Formation Of Insulating Films (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To enable the manufacture of a thin film transistor having excellent characteristics even by a low-temperature process, by applying an oxygen plasma to a gate insulation film. CONSTITUTION:A polycrystalline silicon thin film 2 is evaporated on the upper surface of a glass substrate 1, an active layer element is formed by patterning, a silicon oxide film 3 to be a gate insulation film is deposited then, annealing is applied in the atmosphere of nitrogen, and an oxygen plasma is applied onto the whole surface. After a polycrystalline silicon film 4 and AlSi film 5 are deposited subsequently, a gate 12 is formed on the silicon oxide film 3 by photolithography. By this method, the characteristics of a thin film transistor are improved.

Description

【発明の詳細な説明】 (イ)産業上の利用分野 この発明は、大画面を構成するアクティブマトリクス液
晶ディスプレイ等に応用される薄膜トランジスタの製造
方法に関するものであり、詳しくはガラスの歪点温度以
下の低温プロセスで形成する薄膜トランジスタの高性能
化を図ることができるiiI躾トランジスタの製造方法
に関する。
Detailed Description of the Invention (a) Industrial Application Field The present invention relates to a method for manufacturing thin film transistors that are applied to active matrix liquid crystal displays that constitute large screens. The present invention relates to a method for manufacturing a III-based transistor that can improve the performance of a thin film transistor formed by a low-temperature process.

(ロ)従来の技術 近年、液晶ディスプレイの大画面化、高解像度化に伴い
、その駆動方式は時分割方式から単純マトリクス方式、
更にアクティブマトリクス方式へと移行し、大容量の情
報を表示できるようになりつつある。アクティブマトリ
クス方式は致方を超える画素を有する液晶ディスプレイ
が可能であり、各画素毎にスイッヂングトランジスタを
形成するものである。
(b) Conventional technology In recent years, as liquid crystal displays have become larger and have higher resolution, their drive methods have changed from time-division to simple matrix,
In addition, there has been a shift to an active matrix method, making it possible to display large amounts of information. The active matrix method allows a liquid crystal display to have more than one pixel, and a switching transistor is formed for each pixel.

また、各種液晶ディスプレイの基板には表示能力の高い
、ツィスティッド・ネマティックモードが使えること及
びカラー化するための透過型ディスプレイが可能なこと
などの理由からガラスや石英などの透明基板が使われて
いる。
In addition, transparent substrates such as glass and quartz are used as substrates for various liquid crystal displays because of their high display performance, the ability to use twisted nematic modes, and the possibility of transmissive displays for color display. There is.

そして特に表示画面の拡大化を図る場合には、ディスプ
レイ基板に安価なガラスを使用する方が経済的に有利で
ある。したがってこの経済性を利用するためにアクティ
ブマトリクス方式の液晶ディスプレイを動作させる薄膜
トランジスタを上記ガラス基板上に安定した性能で形成
することができる技術か望まれていた。
Particularly when enlarging the display screen, it is economically advantageous to use inexpensive glass for the display substrate. Therefore, in order to take advantage of this economical efficiency, there has been a desire for a technology that can form thin film transistors for operating active matrix liquid crystal displays on the above-mentioned glass substrate with stable performance.

薄膜トランジスタの活性層としては、通常、アモルファ
スシリコンや多結晶シリコンが用いられるが、駆動回路
まで一体化して薄膜トランジスタで形成しようとする場
合には動作速度の速い多結晶シリコンが有望視されてい
る。また、多結晶シリコン薄膜トランジスタのゲート絶
#!膜には従来、1000℃前後で形成される熱酸化膜
が用いられることから、基板材料には耐熱性に優れた溶
融石英が使われていた。
Amorphous silicon or polycrystalline silicon is usually used as the active layer of a thin film transistor, but polycrystalline silicon, which has a high operating speed, is seen as promising when attempting to form a thin film transistor with a drive circuit integrated. In addition, the gate of polycrystalline silicon thin film transistors is closed! Conventionally, the film used is a thermal oxide film that is formed at around 1000 degrees Celsius, so fused silica, which has excellent heat resistance, has been used as the substrate material.

(ハ)発明が解決しようとする問題点 しかしながら、液晶ディスプレイの大画面化に伴い、溶
融石英に変えて安価なガラス基板を使用したくともガラ
スの歪点温度が550〜600℃と熱酸化膜を形成する
温度より低いため、従来の熱酸化法は使えなかった。そ
こで、より低温で絶縁膜が形成できる常圧CVD法、減
圧CVD沫、プラズマCV D法、光CVD法などが用
いられてはいるが、現状では上記の方法により形成され
た絶縁膜及びその界面の特性はPjA酸化膜に比へて劣
っており、動作特性の優れたトランジスタの形成は困難
であった。また、低温で形成したこれらの絶縁膜の特性
を改善するには900〜1000’Cの熱処理が有効で
あることが知られているが、もちろん、このような高温
の熱処理は歪点温度の低いガラス基板上での薄膜トラン
ジスタの形成には使えなかった。
(c) Problems to be solved by the invention However, as the screens of liquid crystal displays become larger, even if it is desired to use a cheaper glass substrate instead of fused silica, the strain point temperature of the glass is 550 to 600 degrees Celsius, and the thermal oxide film Conventional thermal oxidation methods could not be used because the temperature was lower than the temperature required to form . Therefore, although atmospheric pressure CVD, low pressure CVD, plasma CVD, and photoCVD methods, which can form insulating films at lower temperatures, have been used, at present, the insulating films and their interfaces formed by the above methods have been used. Its characteristics are inferior to those of the PjA oxide film, and it has been difficult to form a transistor with excellent operating characteristics. Furthermore, it is known that heat treatment at 900 to 1000'C is effective in improving the properties of these insulating films formed at low temperatures, but of course, such high temperature heat treatment is effective at improving the properties of these insulating films formed at low temperatures. It could not be used to form thin film transistors on glass substrates.

従って、高温熱処理と同等或いはそれ以上の効果をもた
らしうる低温処理方法の開発が期待されていた。
Therefore, it has been expected to develop a low-temperature treatment method that can provide effects equal to or greater than high-temperature heat treatment.

この発明は上記の事情に鑑みてなされたもので、その目
的は、大画面化が容易なガラス基板に低温プロセスによ
る高性能薄膜トランジスタを形成する方法の提供を目的
としたもので、特に多結晶シリコンを活性層とするMI
S型電界効果トランジスタにおいて、良好な特性を有す
る界面を形成することにある。
This invention was made in view of the above circumstances, and its purpose is to provide a method for forming high-performance thin film transistors using a low-temperature process on a glass substrate that can easily be made into a large screen. MI with active layer
The object of the present invention is to form an interface having good characteristics in an S-type field effect transistor.

(ニ)問題点を解決するための手段 この発明は少なくとも表面が絶縁物質である基板の一方
面に活性層を形成し、この活性層上にMIS型電界効果
トランジスタを形成する1119トランジスタの製造方
法において、 MIS型電界効果トランジスタのゲートが該トランジス
タのゲート絶縁膜上に堆積形成される前に、このゲート
絶縁膜の少なくとも前記ゲートが堆積形成される部位に
酸素プラズマを照射することを特徴とする薄膜トランジ
スタの製造方法である。
(d) Means for Solving the Problems This invention provides a method for manufacturing a 1119 transistor in which an active layer is formed on one side of a substrate whose surface is at least made of an insulating material, and an MIS field effect transistor is formed on this active layer. Before the gate of the MIS field effect transistor is deposited on the gate insulating film of the transistor, at least a portion of the gate insulating film where the gate is deposited is irradiated with oxygen plasma. This is a method for manufacturing a thin film transistor.

〈ホン作 用 この発明は、ゲート絶縁膜に酸素プラズマを照射するこ
とtこより、ガラスの歪点温度以下の低温でもゲート絶
縁膜を向上させることができるようにしたものである。
<Effects> The present invention enables the gate insulating film to be improved even at a low temperature below the strain point temperature of glass by irradiating the gate insulating film with oxygen plasma.

(へ)実施例 以下この発明り実施例を図面にて詳jボするが、この発
明が以下の実施例に限定されるものではない。
(f) Examples Examples of this invention will be described in detail below with reference to the drawings, but the invention is not limited to the following examples.

第1図a−fは、M I S型電界効果トランジスタを
形成する多結晶シリコン薄膜トランジスタの製造プロセ
スを断面で示した図である。
FIGS. 1a to 1f are cross-sectional views showing the manufacturing process of a polycrystalline silicon thin film transistor forming an MIS field effect transistor.

基板1は、絶縁物質であるパイレックスガラスを用いて
いる。まず、有機洗浄及び酸洗浄したパイレックスガラ
ス基板1上面に、真空蒸着法により多結晶シリコン酸化
膜2を蒸着する。多結晶シリコン薄膜2の形成は、基板
温度500℃、真空度3X10’ pa 1成膜速度1
人/ SeCの条件で行ない、形成された膜厚は100
0人である。この多結晶シリコン薄膜2をパターン化し
て活性層部を形成する(第り図a参照)。次いで、常圧
CVI)法により420℃でゲート絶縁膜となるシリコ
ン酸化膜3をそのi厚が500人となるまで堆積し、窒
素雰囲気中でアニールする。次いで、基板温度400℃
で30分間シリコン酸化膜3の全面に酸素プラズマを照
射する。このときの酸素プラズマの出力は150mW 
/ crjである。(第1図す参照)。次ニ前)ホと同
一の条件による真空蒸着法により、多結晶シリコン膜4
をその膜厚が500人となるまで堆積する。続いてその
上面に、スパッタ汰によりAt51膜5をその膜厚が5
000人となるまで堆積した後、フォトリソグラフィに
よりシリコン酸化B!3上にゲート12を形成する(第
1図C参照)。次に、イオン注入時の汚染防止用として
常圧CVD沫により、シリコン酸化膜6をその膜厚が5
00人となるまで堆積した後、ボロンイオノ(B÷)を
70keVで3×10  個/d注入する(第1図C参
照)。前記シリコン酸化膜6の表面をその膜厚が200
人となるまでエツチングした後、層間絶縁膜となるシリ
コン酸化膜7を常圧CVD法でその膜厚が5000Aと
なるまで堆積し、ボロン活性化のために窒素雰囲気中5
00℃で1時間アニールを行なう。続いて圧力100p
aの水素プラズマ雰囲気中350℃で30分間の水素化
を行なう。次に、ソース及びドレイン部のコンタクトホ
ール8,9を開孔しく第1図C参照)、スパッタ法でA
t Siをその膜厚が5000人となるまで堆積した後
、パターン化によりソース電極1o及びドレイン電極1
1を形成する(第1図C参照)。最後に水素雰囲気中4
40℃で30分間アニールを行ない、薄膜トランジスタ
を完成する。
The substrate 1 is made of Pyrex glass, which is an insulating material. First, a polycrystalline silicon oxide film 2 is deposited by vacuum deposition on the top surface of a Pyrex glass substrate 1 which has been organically and acid-cleaned. The polycrystalline silicon thin film 2 was formed at a substrate temperature of 500°C, a degree of vacuum of 3×10'pa, and a deposition rate of 1.
Conducted under human/SeC conditions, the film thickness formed was 100
There are 0 people. This polycrystalline silicon thin film 2 is patterned to form an active layer portion (see FIG. 1A). Next, a silicon oxide film 3, which will become a gate insulating film, is deposited at 420° C. by the normal pressure CVI method until its i thickness becomes 500 μm, and annealed in a nitrogen atmosphere. Next, the substrate temperature was 400°C.
Then, the entire surface of the silicon oxide film 3 is irradiated with oxygen plasma for 30 minutes. The output of oxygen plasma at this time is 150mW
/ crj. (See Figure 1). Polycrystalline silicon film 4 is deposited by vacuum evaporation method under the same conditions as
is deposited until the film thickness reaches 500 layers. Subsequently, an At51 film 5 is formed on the upper surface by sputtering to a thickness of 5.
000, silicon oxide B! is deposited by photolithography. A gate 12 is formed on 3 (see FIG. 1C). Next, to prevent contamination during ion implantation, the silicon oxide film 6 is grown to a thickness of 5.
After depositing up to 000 atoms, boron ions (B÷) are implanted at 3×10 2 /d at 70 keV (see FIG. 1C). The surface of the silicon oxide film 6 has a thickness of 200 mm.
After etching to form a silicon oxide layer, a silicon oxide film 7, which will become an interlayer insulating film, is deposited by atmospheric pressure CVD until the film thickness reaches 5000 Å, and then etched in a nitrogen atmosphere for boron activation.
Annealing is performed at 00°C for 1 hour. Then pressure 100p
Hydrogenation is performed in a hydrogen plasma atmosphere at 350° C. for 30 minutes. Next, the contact holes 8 and 9 in the source and drain portions are opened (see FIG. 1C) using a sputtering method.
After depositing tSi to a film thickness of 5000 nm, the source electrode 1o and the drain electrode 1 are formed by patterning.
1 (see Figure 1C). Finally, in a hydrogen atmosphere 4
Annealing is performed at 40° C. for 30 minutes to complete the thin film transistor.

なお、上記酸素プラズマの照射は、シリコン酸化膜3の
ゲート12が堆積形成される部位のみであってもよい。
Note that the oxygen plasma irradiation may be applied only to a portion of the silicon oxide film 3 where the gate 12 is deposited.

第2図は、この発明の実施例で作製した薄膜トランジス
タ(チャネル長15μ、チャネル幅20μ)のゲート電
圧−ソース電流特性を示したものである。Aはゲート絶
縁膜形成後に酸素プラズマを照射したものであり、Bは
未照射のものである。また、この時ソースに対するドレ
インの電圧は一2Vである。
FIG. 2 shows the gate voltage-source current characteristics of a thin film transistor (channel length: 15 μm, channel width: 20 μm) manufactured in an example of the present invention. A is the one that was irradiated with oxygen plasma after the gate insulating film was formed, and B is the one that was not irradiated. Further, at this time, the voltage of the drain with respect to the source is -2V.

第2図より、ゲート絶縁膜への酸素プラズマ照射によっ
て、薄膜トランジスタの特性が向上していることがわか
る。
From FIG. 2, it can be seen that the characteristics of the thin film transistor are improved by irradiating the gate insulating film with oxygen plasma.

以上のように、多結晶シリコン薄膜トランジスタのプロ
セスに酸素プラズマ照射を採用することにより、ガラス
基板上で行われる低温プロセスにおいても特性の良好な
薄膜トランジスタが形成可能となる。
As described above, by employing oxygen plasma irradiation in the process of polycrystalline silicon thin film transistors, thin film transistors with good characteristics can be formed even in a low temperature process performed on a glass substrate.

なお、この実施例では、ゲート絶縁膜の形成性として、
常圧CVD法を用いたが、この発明はこれに限らず、減
圧CVD法、プラズマCVD法、光CVD法及びこれら
の複数を組み合わせて用いてもよい。またこの実施例で
は照射するプラズマの出力を150mW / olとし
たが20061W / ojを超えると、酸化膜及び界
面が損傷し、逆に特性が悪くなる場合があり、出力は2
00mW / oj以下に抑えておくことが望ましい。
In this example, the formability of the gate insulating film is as follows:
Although the atmospheric pressure CVD method is used, the present invention is not limited thereto, and may also be used in combination with a low pressure CVD method, a plasma CVD method, a photo CVD method, or a combination of these methods. In addition, in this example, the output of the irradiated plasma was set to 150 mW/oj, but if it exceeds 20,061 W/oj, the oxide film and interface may be damaged, and the characteristics may deteriorate, so the output is 20,061 W/oj.
It is desirable to keep it below 00mW/oj.

また、この発明の効果を明確にするために下記工程によ
り単結晶シリコン基板上にMOSキャパシタを製作し、
第1表に示すように酸素プラズマを照射を行なった場合
と行なわない場合とでそれぞれの特性を測定した。
In addition, in order to clarify the effects of this invention, a MOS capacitor was manufactured on a single crystal silicon substrate by the following steps,
As shown in Table 1, the characteristics were measured with and without oxygen plasma irradiation.

第1表 いずれの点においても、酸素プラズマ照射によって特性
の向上が認められた。更に、2か月経過後の測定におい
ても、酸素プラズマ照射の試料では、未照射の試料に比
べて特性の劣化はごく僅かであった。
In all points in Table 1, improvements in properties were observed by oxygen plasma irradiation. Furthermore, even in measurements after two months, the deterioration of the characteristics of the sample irradiated with oxygen plasma was very slight compared to the sample that was not irradiated.

これらは、酸素プラズマの照射によってシリコン酸化膜
の膜質(密度、組成、原子間距離、結合角など)が熱酸
化膜に近いものになっているためで、この酸素プラズマ
照射を薄膜トランジスタのゲート絶縁膜に施せば、低湿
プロセスでも大変良好な特性を持つトランジスタが作製
可能となる。
This is because the film quality (density, composition, interatomic distance, bond angle, etc.) of the silicon oxide film becomes close to that of a thermal oxide film due to oxygen plasma irradiation. By applying this method, it is possible to manufacture transistors with very good characteristics even in a low-humidity process.

なお、MOSキャパシタは以下のようにして製作される
Note that the MOS capacitor is manufactured as follows.

まず、RCA洗浄を施したP型単結晶シリコン基板上に
、常圧CVD法により420℃で500人のシリコン酸
化膜を堆積する。次いで、窒素雰囲気中、550℃で1
時間アニールを行ない、更に、基板温度400℃で出力
150mW / cmの酸素プラズマを30分間照射す
る。次いで、このシリコン酸化膜上にA1電極を500
0人蒸着し、さらに基板裏面にもA1を5000人蒸者
する。以上によりMOSキャパシタは完成される。
First, a 500-layer silicon oxide film is deposited at 420° C. by atmospheric pressure CVD on a P-type single-crystal silicon substrate that has been subjected to RCA cleaning. Then, in a nitrogen atmosphere at 550°C for 1
Annealing is performed for a period of time, and oxygen plasma with an output of 150 mW/cm is irradiated for 30 minutes at a substrate temperature of 400°C. Next, an A1 electrode with a thickness of 500 mm was placed on this silicon oxide film.
0 person evaporates, and further 5000 people evaporates A1 on the back side of the substrate. With the above steps, the MOS capacitor is completed.

(ト)発明の効果 この発明によれば、表面が絶縁物質である基板上の薄膜
トランジスタ形成において、ゲート絶縁膜に酸素プラズ
マを照射することにより、低温プロセスでも特性の良好
な薄膜トランジスタを作製することができる。これによ
り安価なガラス基板等を用いたアクティブマトリクス・
パネルの製造が可能となり、大面積薄型ディスプレイな
どへ応用することができる。
(G) Effects of the Invention According to this invention, when forming a thin film transistor on a substrate whose surface is an insulating material, by irradiating the gate insulating film with oxygen plasma, a thin film transistor with good characteristics can be manufactured even in a low temperature process. can. This allows active matrix and
This makes it possible to manufacture panels and can be applied to large-area thin displays.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図a〜fはこの発明の一実施例を示す多結晶シリコ
ン薄膜トランジスタ製造の各プロセスにあける素子断面
図、第2図はゲート絶縁膜形成後に酸素プラズマを照射
した場合と、しない場合との薄膜トランジスタの特性を
比較した比較図である。 1・・・・・・基板(ガラス基板)、 2・・・・・・活性層(多結晶シリコン薄膜)、12・
・・・・・ゲート、 3・・・・・・ゲート絶縁膜(シリコン酸化膜)。 鍜
Figures 1a to 1f are cross-sectional views of a polycrystalline silicon thin film transistor manufactured in each process, showing an embodiment of the present invention. FIG. 2 is a comparison diagram comparing characteristics of thin film transistors. 1...Substrate (glass substrate), 2...Active layer (polycrystalline silicon thin film), 12.
...Gate, 3...Gate insulating film (silicon oxide film).雜

Claims (1)

【特許請求の範囲】 1、少なくとも表面が絶縁物質である基板の一方面に活
性層を形成し、この活性層上にMIS型電界効果トラン
ジスタを形成する薄膜トランジスタの製造方法において
、 MIS型電界効果トランジスタのゲートが該トランジス
タのゲート絶縁膜上に堆積形成される前に、このゲート
絶縁膜の少なくとも前記ゲートが堆積形成される部位に
酸素プラズマを照射することを特徴とする薄膜トランジ
スタの製造方法。
[Claims] 1. A method for manufacturing a thin film transistor, in which an active layer is formed on one side of a substrate whose surface is made of an insulating material, and an MIS field effect transistor is formed on the active layer, comprising: 1. A method for manufacturing a thin film transistor, comprising: irradiating oxygen plasma to at least a portion of the gate insulating film where the gate is deposited before the gate is deposited on the gate insulating film of the transistor.
JP16030386A 1986-07-08 1986-07-08 Manufacture of thin film transistor Pending JPS6315468A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16030386A JPS6315468A (en) 1986-07-08 1986-07-08 Manufacture of thin film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16030386A JPS6315468A (en) 1986-07-08 1986-07-08 Manufacture of thin film transistor

Publications (1)

Publication Number Publication Date
JPS6315468A true JPS6315468A (en) 1988-01-22

Family

ID=15712041

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16030386A Pending JPS6315468A (en) 1986-07-08 1986-07-08 Manufacture of thin film transistor

Country Status (1)

Country Link
JP (1) JPS6315468A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH039057A (en) * 1989-06-02 1991-01-16 Hino Motors Ltd Accelerator displacement detector
JPH0443642A (en) * 1990-06-11 1992-02-13 G T C:Kk Formation of gate insulating film
US5817549A (en) * 1994-08-31 1998-10-06 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a semiconductor device
US5840600A (en) * 1994-08-31 1998-11-24 Semiconductor Energy Laboratory Co., Ltd. Method for producing semiconductor device and apparatus for treating semiconductor device
US6150203A (en) * 1994-08-31 2000-11-21 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a semiconductor device
US6706572B1 (en) 1994-08-31 2004-03-16 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a thin film transistor using a high pressure oxidation step
US8344378B2 (en) 2009-06-26 2013-01-01 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor and method for manufacturing the same

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH039057A (en) * 1989-06-02 1991-01-16 Hino Motors Ltd Accelerator displacement detector
JPH0443642A (en) * 1990-06-11 1992-02-13 G T C:Kk Formation of gate insulating film
US5817549A (en) * 1994-08-31 1998-10-06 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a semiconductor device
US5840600A (en) * 1994-08-31 1998-11-24 Semiconductor Energy Laboratory Co., Ltd. Method for producing semiconductor device and apparatus for treating semiconductor device
US6150203A (en) * 1994-08-31 2000-11-21 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a semiconductor device
US6706572B1 (en) 1994-08-31 2004-03-16 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a thin film transistor using a high pressure oxidation step
US8344378B2 (en) 2009-06-26 2013-01-01 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor and method for manufacturing the same
US8956934B2 (en) 2009-06-26 2015-02-17 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor and method for manufacturing the same

Similar Documents

Publication Publication Date Title
US5275851A (en) Low temperature crystallization and patterning of amorphous silicon films on electrically insulating substrates
KR100191091B1 (en) Thin film transistor and its fabrication method
KR100470274B1 (en) Method of phase transition of amorphous material using a cap layer
JP3137797B2 (en) Thin film transistor and manufacturing method thereof
WO1997022141A1 (en) Method of manufacturing thin film semiconductor device, and thin film semiconductor device
JPS6315468A (en) Manufacture of thin film transistor
JPS62205664A (en) Manufacture of thin film transistor
JPH0422120A (en) Thin film semiconductor device
JPS6148979A (en) Manufacture of polycrystalline silicon thin-film transistor
JPS61263273A (en) Manufacture of thin film semiconductor device
JPS63119576A (en) Thin film transistor
JPH0888363A (en) Semiconductor device and its manufacture
JPH1197438A (en) Method for reforming silicon oxide
JPS63283068A (en) Manufacture of thin-film transistor
JPS5968975A (en) Semiconductor device and manufacture thereof
JPS63250178A (en) Manufacture of thin film semiconductor device
JPH03120872A (en) Semiconductor device and manufacture thereof
JPS63133575A (en) Thin-film transistor
JPH0462174B2 (en)
JP2837473B2 (en) Silicon thin film transistor
JPH01309379A (en) Thin-film semiconductor element
JPH113887A (en) Manufacture of thin film transistor
JPS63172469A (en) Thin film transistor
JPH03161977A (en) Thin film semiconductor device and its manufacture
JPS6379381A (en) Thin film transistor