JPH0462174B2 - - Google Patents
Info
- Publication number
- JPH0462174B2 JPH0462174B2 JP57171462A JP17146282A JPH0462174B2 JP H0462174 B2 JPH0462174 B2 JP H0462174B2 JP 57171462 A JP57171462 A JP 57171462A JP 17146282 A JP17146282 A JP 17146282A JP H0462174 B2 JPH0462174 B2 JP H0462174B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- semiconductor thin
- tft
- film
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010408 film Substances 0.000 claims description 22
- 238000000034 method Methods 0.000 claims description 19
- 239000010409 thin film Substances 0.000 claims description 17
- 239000004065 semiconductor Substances 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 229910052738 indium Inorganic materials 0.000 claims description 7
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 7
- 239000013078 crystal Substances 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 238000009792 diffusion process Methods 0.000 description 8
- 239000010410 layer Substances 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Liquid Crystal (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Description
【発明の詳細な説明】
本発明は、半導体薄膜、特に多結晶シリコン・
アモルフアスシリコンを用い、ソース電極、ドレ
イン電極としてITOの如きインジウムを有する透
明導電性膜を用いた、MOS型の薄膜トランジス
タ（以下TFTと略す。）に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor thin films, particularly polycrystalline silicon films.
The present invention relates to a MOS type thin film transistor (hereinafter abbreviated as TFT) using amorphous silicon and a transparent conductive film containing indium such as ITO as the source and drain electrodes.
本発明は真性半導体薄膜あるいはＮ型を有する
半導体薄膜を用いたMOS型のTFTに於いて、ソ
ース・ドレインとコンタクトを有する各電極がイ
ンジウムを有する透明導電性膜であり、また、イ
ンジウムが価の不純物であり、かつ、低温
（200℃以下）で溶融する性質を有ることから、前
記透明導電性膜を配線形成後、熱工程により、該
透明導電性膜よりインジウムを前記半導体薄膜に
拡散せしめ、良好なコンタクト特性を得ると共
に、Ｐ型の拡散層を形成することにより、低温で
Ｐ型を有するMOS型のTFTを形成することを目
的とする。 The present invention relates to a MOS type TFT using an intrinsic semiconductor thin film or an N-type semiconductor thin film, in which each electrode having a source/drain and a contact is a transparent conductive film containing indium. Since it is an impurity and has the property of melting at low temperatures (200 ° C. or less), after forming the wiring in the transparent conductive film, indium is diffused from the transparent conductive film into the semiconductor thin film by a thermal process, The purpose is to obtain good contact characteristics and to form a P-type MOS type TFT at a low temperature by forming a P-type diffusion layer.
半導体薄膜として多結晶シリコンを用いた
TFTの形成方法の１例を第１図に従つて説明す
る。第１図ａで、絶縁基板１００上に真性あるい
はＮ型を有する多結晶シリコン１０１を形成加工
する。しかる後、ゲート絶縁膜１０２を形成す
る。次に同図ｂのように、ゲート電極とすべく多
結晶シリコン１０３を形成、しかる後に、熱拡
散、あるいはイオン注入によりソース・ドレイン
拡散層１０４を形成する。その後層間絶縁膜１０
５をCVD法により全面に形成し、熱処理後、ソ
ース・ドレイン拡散層とソース・ドレイン電極と
のコンタクト用の窓開けをしたのが同図ｃであ
る。最後に、Al又はAl・si等のソース・ドレイ
ン電極用配線を配線形成したのが同図ｄである。
上述したTFTの製造方法は、従来のシリコン基
板に形成するMOS型トランジスタと同様であり、
従来のプロセス技術をそのまま適用できるもので
ある。しかし、この製造方法によれば、例えばゲ
ート絶縁膜形成方法として熱酸化を用いた時、
又、ソース・ドレイン拡散層形成方法として、熱
拡散を用いた時、あるいはイオン注入法を用い
て、活性化させるべくアニーリングを必要とする
時、等いずれの場合も高温（800℃〜1100℃）を
要する。以下、高温を要するTFTの製造プロセ
スを“高温プロセス”と呼ぶことにする。TFT
が高温プロセスで形成される場合、例えばTFT
を透過型のマトリツクス型液晶表示装置に適用し
た場合、TFTアレイを形成する透明絶縁基板は
高温に耐え得る材料、即ち石英基板に限られてし
まう。ところが絶縁基板として高価な石英板を使
用することは、コストの面、あるいは大面積化の
面から量産性を考える場合、非常に大きな欠点で
ある。 Using polycrystalline silicon as a semiconductor thin film
An example of a method for forming a TFT will be explained with reference to FIG. In FIG. 1A, polycrystalline silicon 101 having intrinsic or N type is formed and processed on an insulating substrate 100. As shown in FIG. After that, a gate insulating film 102 is formed. Next, as shown in FIG. 4B, polycrystalline silicon 103 is formed to serve as a gate electrode, and then source/drain diffusion layers 104 are formed by thermal diffusion or ion implantation. After that, the interlayer insulating film 10
5 was formed on the entire surface by the CVD method, and after heat treatment, a window was opened for contact between the source/drain diffusion layer and the source/drain electrode, as shown in FIG. Finally, wiring for source/drain electrodes made of Al or Al.Si is formed, as shown in Figure d.
The manufacturing method of the TFT described above is similar to that of a conventional MOS transistor formed on a silicon substrate.
Conventional process technology can be applied as is. However, according to this manufacturing method, for example, when thermal oxidation is used as a gate insulating film formation method,
In addition, when thermal diffusion is used as the source/drain diffusion layer formation method, or when ion implantation is used and annealing is required for activation, high temperatures (800°C to 1100°C) are required. It takes. Hereinafter, the TFT manufacturing process that requires high temperatures will be referred to as a "high temperature process." TFT
is formed in a high temperature process, e.g. TFT
When applied to a transmissive matrix type liquid crystal display device, the transparent insulating substrate forming the TFT array is limited to a material that can withstand high temperatures, that is, a quartz substrate. However, the use of an expensive quartz plate as an insulating substrate has a very large drawback when considering mass production from the viewpoint of cost or increasing the area.
本発明はかかる欠点を除去したTFTの製造方
法を示すものである。 The present invention provides a method for manufacturing TFTs that eliminates such drawbacks.
以下図面に従つて、本発明を説明する。第２図
は本発明によるTFTの製造方法を示す工程断面
図である。 The present invention will be explained below with reference to the drawings. FIG. 2 is a process sectional view showing the method for manufacturing a TFT according to the present invention.
第２図ａにおいて、絶縁基板、例えばガラス基
板２００上に、CVD法により真性あるいはＮ型
を有する多結晶シリコン２０１を形成加工する。
しかる後にCVD法によりゲート絶縁膜２０２を
形成する。同図ｂは、ゲート電極として、Ｎ型あ
るいはＰ型を有する多結晶シリコン２０３を形成
加工した。同図ｃは層間絶縁膜として、CVD法
によりSiO2膜、あるいはPSG膜２０５を全面に
形成した後、コンタクトホールの窓開けを行つた
ものである。同図ｄは透明導電性膜としてITO膜
２０６をスパツタリング法、あるいは蒸着法によ
り形成し、配線加工した。この時、300℃程度の
加熱スパツタ、あるいは、後工程として同程度の
熱処理を加えることにより、インジウムを多結晶
シリコン表面近傍に拡散せしめる。インジウムが
価の元素であり、またITOはそれに接する半導
体表面をＰ型化する性質を有するため、上記の製
造方法によれば、良好なコンタクトを有する、Ｐ
型のMOS型のTFTを低温で形成することができ
る。しかも、従来法のように、インオ注入、ある
いは熱拡散工程はないため工程の短縮化ができる
と共に、高温の熱工程が不用のため、安価なガラ
ス基板を絶縁基板として用いることができる。従
つて、本発明によるTFTを透過型のマトリツク
ス型液晶表示装置のスイツチング素子として適用
することにより、大幅なコスト低減が可能であ
る。 In FIG. 2a, an intrinsic or N-type polycrystalline silicon 201 is formed on an insulating substrate, for example, a glass substrate 200, by CVD.
Thereafter, a gate insulating film 202 is formed by CVD. In FIG. 1B, polycrystalline silicon 203 having N type or P type was formed and processed as a gate electrode. Figure c shows a structure in which a SiO 2 film or a PSG film 205 is formed on the entire surface as an interlayer insulating film by the CVD method, and then a contact hole is opened. In Figure d, an ITO film 206 was formed as a transparent conductive film by sputtering or vapor deposition, and wiring was processed. At this time, indium is diffused into the vicinity of the polycrystalline silicon surface by heating sputtering at about 300° C. or by applying heat treatment of the same degree as a post-process. Indium is a valent element, and ITO has the property of making the semiconductor surface in contact with it P-type.
MOS type TFTs can be formed at low temperatures. Moreover, unlike the conventional method, there is no ion implantation or thermal diffusion process, so the process can be shortened, and since a high-temperature thermal process is not required, an inexpensive glass substrate can be used as an insulating substrate. Therefore, by applying the TFT according to the present invention as a switching element of a transmissive matrix type liquid crystal display device, it is possible to significantly reduce costs.
以上の説明の如く、絶縁基板上に形成された島
状の多結晶又は非晶質の半導体薄膜、該半導体薄
膜中に形成されたソース領域とドレイン領域とチ
ヤンネル領域、チヤンネル領域と接して形成され
たゲート絶縁膜、該ゲート絶縁膜と接して形成さ
れたゲート電極、該ソース領域上に形成されたソ
ース電極、該ドレイン領域上に形成されたドレイ
ン電極から構成されてなる薄膜トランジスタにお
いて、該ソース電極及びドレイン電極は金属を含
む透明導電性膜であり、かつ該ソース領域と該ド
レイン領域は該透明導電膜中の該金属を該半導体
薄膜中に拡散させた拡散層であることにより、マ
トリツクス型の液晶表示装置に応用されるTFT
に対し、工程の短縮及びプロセスの低温化を実現
せしめる特徴を有する。 As described above, an island-shaped polycrystalline or amorphous semiconductor thin film formed on an insulating substrate, a source region, a drain region, a channel region, and a channel region formed in the semiconductor thin film are formed in contact with the channel region. A thin film transistor comprising a gate insulating film, a gate electrode formed in contact with the gate insulating film, a source electrode formed on the source region, and a drain electrode formed on the drain region. and the drain electrode are transparent conductive films containing metal, and the source region and the drain region are diffusion layers in which the metal in the transparent conductive film is diffused into the semiconductor thin film. TFT applied to liquid crystal display devices
In contrast, it has the characteristics of shortening the process and lowering the process temperature.
なお本発明の実施例では、半導体薄膜として多
結晶シリコンを用いたが、アモルフアスシリコン
あるいは他の半導体薄膜にも適用できる。 In the embodiments of the present invention, polycrystalline silicon is used as the semiconductor thin film, but the present invention can also be applied to amorphous silicon or other semiconductor thin films.
第１図は従来法によるTFTの工程断面図であ
り、第２図が本発明による工程断面図である。
２００……絶縁基板、２０１……多結晶シリコ
ン、２０２……ゲート絶縁膜、２０３……ゲート
電極、２０４……Ｐ型を有する領域、２０５……
層間絶縁膜、２０６……ITO膜。
FIG. 1 is a cross-sectional view of a TFT process according to a conventional method, and FIG. 2 is a cross-sectional view of a process according to the present invention. 200... Insulating substrate, 201... Polycrystalline silicon, 202... Gate insulating film, 203... Gate electrode, 204... Region having P type, 205...
Interlayer insulation film, 206...ITO film.
Claims (1)
製造方法において、該絶縁基板上に真性あるいは
Ｎ型の非単結晶半導体薄膜を形成する工程、該半
導体薄膜上にインジウムを含む透明導電性膜から
なるソース電極、ドレイン電極を形成する工程、
該ソース電極、ドレイン電極中の該インジウムを
該半導体薄膜中に拡散させてソース領域、ドレイ
ン領域を形成する工程からなることを特徴とする
薄膜トランジスタの製造方法。1. A method for manufacturing a thin film transistor formed on an insulating substrate, including a step of forming an intrinsic or N-type non-single crystal semiconductor thin film on the insulating substrate, and a source electrode made of a transparent conductive film containing indium on the semiconductor thin film. , a step of forming a drain electrode,
A method for manufacturing a thin film transistor, comprising the step of diffusing the indium in the source electrode and drain electrode into the semiconductor thin film to form a source region and a drain region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57171462A JPS5961183A (en) | 1982-09-30 | 1982-09-30 | Thin-film transistor and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57171462A JPS5961183A (en) | 1982-09-30 | 1982-09-30 | Thin-film transistor and its manufacture |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5961183A JPS5961183A (en) | 1984-04-07 |
| JPH0462174B2 true JPH0462174B2 (en) | 1992-10-05 |
Family
ID=15923553
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57171462A Granted JPS5961183A (en) | 1982-09-30 | 1982-09-30 | Thin-film transistor and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5961183A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0693509B2 (en) * | 1983-08-26 | 1994-11-16 | シャープ株式会社 | Thin film transistor |
| JPH07120635B2 (en) * | 1986-12-26 | 1995-12-20 | 株式会社東芝 | Method for manufacturing semiconductor device |
| JPH0391932A (en) * | 1989-09-04 | 1991-04-17 | Canon Inc | Manufacture of semiconductor device |
| US5153142A (en) * | 1990-09-04 | 1992-10-06 | Industrial Technology Research Institute | Method for fabricating an indium tin oxide electrode for a thin film transistor |
-
1982
- 1982-09-30 JP JP57171462A patent/JPS5961183A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5961183A (en) | 1984-04-07 |
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