JPH0371793B2 - - Google Patents

Info

Publication number
JPH0371793B2
JPH0371793B2 JP57143786A JP14378682A JPH0371793B2 JP H0371793 B2 JPH0371793 B2 JP H0371793B2 JP 57143786 A JP57143786 A JP 57143786A JP 14378682 A JP14378682 A JP 14378682A JP H0371793 B2 JPH0371793 B2 JP H0371793B2
Authority
JP
Japan
Prior art keywords
thin film
current
active matrix
polycrystalline silicon
liquid crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57143786A
Other languages
Japanese (ja)
Other versions
JPS5933877A (en
Inventor
Hiroyuki Ooshima
Toshimoto Kodaira
Toshihiko Mano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP57143786A priority Critical patent/JPS5933877A/en
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to FR8305592A priority patent/FR2527385B1/en
Priority to DE3348083A priority patent/DE3348083C2/de
Priority to DE3312743A priority patent/DE3312743C2/en
Priority to GB08309750A priority patent/GB2118365B/en
Priority to FR838320366A priority patent/FR2536194B1/en
Publication of JPS5933877A publication Critical patent/JPS5933877A/en
Priority to HK886/87A priority patent/HK88687A/en
Priority to US07/203,548 priority patent/US5124768A/en
Publication of JPH0371793B2 publication Critical patent/JPH0371793B2/ja
Priority to US07/828,548 priority patent/US5294555A/en
Priority to US08/320,729 priority patent/US6294796B1/en
Priority to US08/388,900 priority patent/US5554861A/en
Priority to US08/402,374 priority patent/US6242777B1/en
Priority to US08/413,369 priority patent/US5736751A/en
Priority to US08/452,370 priority patent/US5698864A/en
Granted legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/13—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body combined with thin-film or thick-film passive components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor
    • G02F2202/104—Materials and properties semiconductor poly-Si
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78666—Amorphous silicon transistors with normal-type structure, e.g. with top gate

Description

【発明の詳細な説明】 本発明は薄膜トランジスタに関する。[Detailed description of the invention] The present invention relates to thin film transistors.

近年、絶縁基板上に薄膜トランジスタを形成す
る研究が活発に行なわれている。その目的の１つ
には、安価な絶縁基板を用いた薄形デイスプレイ
の実現が挙げられる。すなわち、絶縁基板上に薄
膜トランジスタをマトリツクス状に形成し、その
スイツチング特性を応用して液晶等による薄膜デ
イスプレイを目指すものである。このようにして
構成されたアクテイブマトリツクス基板は、非常
に安価に製作できる可能性がある。 In recent years, research on forming thin film transistors on insulating substrates has been actively conducted. One of the objectives is to realize a thin display using an inexpensive insulating substrate. That is, the aim is to form thin film transistors in a matrix on an insulating substrate and apply their switching characteristics to create a thin film display using liquid crystal or the like. An active matrix substrate constructed in this manner may be manufactured at a very low cost.

薄膜トランジスタをアクテイブマトリツクス基
板に応用した場合の液晶表示装置は、一般に、上
側のガラス基板と、下側の薄膜トランジスタ基板
と、その間に封入された液晶とから構成されてお
り、前記薄膜トランジスタ基板上にマトリツクス
状に配置された液晶駆動素子を外部選択回路によ
り選択し、前記液晶駆動素子に接続された液晶駆
動電極に電圧を印加することにより、任意の文
字、図形、あるいは画像の表示を行なうものであ
る。前記薄膜トランジスタ基板の一般的な回路図
を第１図に示す。 A liquid crystal display device in which a thin film transistor is applied to an active matrix substrate is generally composed of an upper glass substrate, a lower thin film transistor substrate, and a liquid crystal sealed between them. By selecting liquid crystal drive elements arranged in a shape by an external selection circuit and applying voltage to liquid crystal drive electrodes connected to the liquid crystal drive elements, arbitrary characters, figures, or images can be displayed. . A general circuit diagram of the thin film transistor substrate is shown in FIG.

第１図ａは薄膜トランジスタ基板上の液晶駆動
素子のマトリツクス状配置図である。図中の１で
囲まれた領域が表示領域であり、その中に液晶駆
動素子２がマトリツクス状に配置されている。３
は液晶駆動素子２へのデータ線であり、４は液晶
駆動素子２へのアドレス線である。液晶駆動素子
２の回路図を第１図ｂに示す。５は薄膜トランジ
スタであり、データのスイツチングを行なう。６
はコンデンサであり、データ信号の保持用として
用いられる。７は液晶パネルであり、７−１は各
液晶駆動素子に対応して形成された駆動電極であ
り、７−２は上側ガラスパネルである。 FIG. 1a is a diagram showing a matrix arrangement of liquid crystal driving elements on a thin film transistor substrate. The area surrounded by 1 in the figure is a display area, in which liquid crystal driving elements 2 are arranged in a matrix. 3
4 is a data line to the liquid crystal driving element 2, and 4 is an address line to the liquid crystal driving element 2. A circuit diagram of the liquid crystal driving element 2 is shown in FIG. 1b. A thin film transistor 5 performs data switching. 6
is a capacitor and is used to hold data signals. 7 is a liquid crystal panel, 7-1 is a drive electrode formed corresponding to each liquid crystal drive element, and 7-2 is an upper glass panel.

以上の説明からわかるように、液晶駆動素子内
の薄膜トランジスタは、液晶に印加する電圧のデ
ータをスイツチングするために用いられ、その特
性により、アクテイブマトリツクス基板全体の性
能が決定されるといつても過言ではない。したが
つて、薄膜トランジスタは仕様を十分に満足する
ものでなくてはならない。薄膜トランジスタに要
求される特性は次のようなものが挙げられる。 As can be seen from the above explanation, the thin film transistor in the liquid crystal driving element is used to switch the voltage data applied to the liquid crystal, and its characteristics determine the performance of the entire active matrix substrate. It's not too much to say. Therefore, the thin film transistor must fully satisfy the specifications. The characteristics required of thin film transistors include the following.

(1) 薄膜トランジスタをON状態にした時、コン
デンサを充電させるために充分な電流を流すこ
とができること。(1) When the thin film transistor is turned on, sufficient current can flow to charge the capacitor.

(2) 薄膜トランジスタをOFF状態にした時、極
力、電流が流れないこと。(2) When the thin film transistor is turned off, as little current as possible should flow.

(3) 特性の安定性・再現性に優れ、十分な長期信
頼性を有していること。(3) It must have excellent stability and reproducibility of characteristics, and sufficient long-term reliability.

(1)はコンデンサへのデータの書き込み特性に関
するものである。液晶の表示はコンデンサの電位
により決定されるため、短時間にデータを完壁に
書き込むことができるように、薄膜トランジスタ
は十分大きい電流を流すことができなくてはなら
ない。このときの電流（以下、ON電流という。）
は、コンデンサの容量と書き込み時間とから定ま
り、そのON電流をクリアできるように薄膜トラ
ンジスタを製造しなくてはならない。 (1) relates to the characteristics of writing data to the capacitor. Since the liquid crystal display is determined by the potential of the capacitor, the thin film transistor must be able to flow a sufficiently large current so that data can be completely written in a short period of time. Current at this time (hereinafter referred to as ON current)
is determined by the capacitance of the capacitor and the write time, and thin film transistors must be manufactured to clear the ON current.

(2)はコンデンサに書き込まれたデータの保持特
性に関するものである。一般に、書き込まれたデ
ータは書き込み時間よりもはるかに長い時間、保
持されなくてはならない。コンデンサの静電容量
は通常1PF程度の小さい値であるため、薄膜トラ
ンジスタがOFF状態のときの電流（以下、OFF
電流という。）がわずかでも流れると、駆動電極
の電位は急激にデータ線の電位に近づき書き込ま
れたデータは正しく保持されなくなつてしまう。
したがつて、薄膜トランジスタのOFF電流は極
力小さくする必要がある。 (2) relates to the retention characteristics of data written to the capacitor. Generally, written data must be retained for a much longer time than the write time. Since the capacitance of a capacitor is usually a small value of about 1PF, the current when the thin film transistor is in the OFF state (hereinafter referred to as OFF
It's called electric current. ) flows even slightly, the potential of the drive electrode will rapidly approach the potential of the data line, and the written data will no longer be held correctly.
Therefore, it is necessary to reduce the OFF current of the thin film transistor as much as possible.

(3)はトランジスタ特性の安定性・再現性及び信
頼性に関するものである。通常、１枚のアクテイ
ブマトリツクス基板上には、数万個の薄膜トラン
ジスタが集積されるが、それらはすべて均一な特
性を有していなくてはならない。また、製造ロツ
ト間における特性の再現性も非常に重要となる。
さらに、トランジスタ特性は長期にわたつて安定
であり、十分な信頼性を有していなくてはならな
い。 (3) relates to stability, reproducibility, and reliability of transistor characteristics. Usually, tens of thousands of thin film transistors are integrated on a single active matrix substrate, but all of them must have uniform characteristics. Furthermore, the reproducibility of characteristics between production lots is also very important.
Furthermore, the transistor characteristics must be stable over a long period of time and must have sufficient reliability.

以上述べたように、アクテイブマトリツクス基
板に用いる薄膜トランジスタには、数多くの厳し
い特性が要求される。 As described above, thin film transistors used in active matrix substrates are required to meet a number of strict characteristics.

従来、薄膜トランジスタをアクテイブマトリツ
クス基板に応用する場合、半導体薄膜としては、
カドミウムセレンなどの化合物半導体、あるいは
アモルフアスシリコンなどの非晶質半導体などが
用いられてきた。しかし、現在のところ、前述の
３つの要求項目をすべて満足するものは作られて
いない。例えば、化合物半導体の場合、キヤリア
の移動度が比較的大きいため、(1)の項目は容易に
満たされるが、(2)及び(3)の項目は満たされていな
い。特に、再現性及び信頼性が著しく悪く、この
ため長い歴史を有しながらも今だに実用化されて
いない。また、非常質半導体の場合、(2)の項目は
十分満たされるが、(1)及び(3)の項目は満たされて
いない。非常質半導体では移動度が小さいため、
本質的にON電流は小さくなる。 Conventionally, when applying thin film transistors to active matrix substrates, the semiconductor thin film is
Compound semiconductors such as cadmium selenium or amorphous semiconductors such as amorphous silicon have been used. However, at present, no one has been manufactured that satisfies all three of the above-mentioned requirements. For example, in the case of compound semiconductors, the carrier mobility is relatively high, so item (1) is easily satisfied, but items (2) and (3) are not satisfied. In particular, the reproducibility and reliability are extremely poor, and for this reason, although it has a long history, it has not yet been put into practical use. In addition, in the case of non-quality semiconductors, item (2) is fully satisfied, but items (1) and (3) are not satisfied. Due to the low mobility in non-essential semiconductors,
Essentially, the ON current becomes smaller.

このように、現在のところ、優れた特性を有す
る薄膜トランジスタを用いたアクテイブマトリツ
クス基板は実現されていない。 Thus, at present, an active matrix substrate using thin film transistors with excellent characteristics has not been realized.

本発明はこのような従来の欠点を除去するもの
であり、その目的は、十分大きいON電流と十分
小さいOFF電流、及び優れた再現性と信頼性を
有する薄膜トランジスタを用いた安価なアクテイ
ブマトリツクス基板を提供することである。以
下、実施例に基づいて、本発明を詳しく説明す
る。 The present invention eliminates these conventional drawbacks, and its purpose is to provide an inexpensive active matrix substrate using thin film transistors that has sufficiently large ON current, sufficiently small OFF current, and excellent reproducibility and reliability. The goal is to provide the following. Hereinafter, the present invention will be explained in detail based on Examples.

第２図は本発明によるアクテイブマトリツクス
基板の構造を示す断面図の一例である。ここでは
簡単のため、１つの液晶駆動素子についてのみ記
してある。石英などの絶縁基板８上に多結晶シリ
コンを堆積し、これを薄膜トランジスタの半導体
母材とする。チヤネル領域は真性多結晶シリコン
９で構成され、ソース・ドレイン領域はリン、ヒ
素、ボロンなどの不純物をドープした外因性多結
晶シリコン１０，１１で構成される。ゲート絶縁
膜１２は真性多結晶シリコン９の熱酸化膜で構成
される。１３はゲート電極となるアドレス線、１
４は層間絶縁膜、１５はソース電極またはドレイ
ン電極となるデータ線、１６はドレイン電極また
はソース電極となる駆動電極である。１７はデー
タ蓄積用コンデンサのコモン電極である。層間絶
縁膜１４はコンデンサの誘電体も兼ねている。 FIG. 2 is an example of a sectional view showing the structure of an active matrix substrate according to the present invention. For simplicity, only one liquid crystal driving element is described here. Polycrystalline silicon is deposited on an insulating substrate 8 such as quartz, and this is used as a semiconductor base material of a thin film transistor. The channel region is made of intrinsic polycrystalline silicon 9, and the source/drain regions are made of extrinsic polycrystalline silicon 10 and 11 doped with impurities such as phosphorus, arsenic, and boron. The gate insulating film 12 is composed of a thermally oxidized film of intrinsic polycrystalline silicon 9. 13 is an address line serving as a gate electrode, 1
4 is an interlayer insulating film, 15 is a data line that becomes a source electrode or a drain electrode, and 16 is a drive electrode that becomes a drain electrode or a source electrode. 17 is a common electrode of a data storage capacitor. The interlayer insulating film 14 also serves as a dielectric of the capacitor.

第３図は、第２図に示したアクテイブマトリツ
クス基板の製造方法の１例を示すものである。ま
ず第３図ａのように、絶縁基板８上に真性多結晶
シリコン９を堆積した後、熱酸化を行ないゲート
絶縁膜１２を形成する。次に、第３図ｂのよう
に、ゲート電極１３及びコンデンサのコモン電極
１７を形成する。この２つの電極は、同一の導電
材料で同時に形成して構わない。次に、第３図ｃ
のように、不純物をドーブすることによりソー
ス・ドレイン領域１０，１１を形成した後、層間
絶縁膜１４を堆積し、コンタクトホールを開口す
る。ソース・ドレイン領域への不純物のドーピン
グには種々の方法があるが、熱拡散法あるいはイ
オン打込み法が一般的である。この後、第３図ｄ
のようにデータ線１５を形成し、さらに第３図ｅ
のように駆動電極１６を形成して完成される。な
お、駆動電極１６を形成した後に、データ線１５
を形成してもよい。 FIG. 3 shows an example of a method for manufacturing the active matrix substrate shown in FIG. First, as shown in FIG. 3a, after intrinsic polycrystalline silicon 9 is deposited on an insulating substrate 8, thermal oxidation is performed to form a gate insulating film 12. Next, as shown in FIG. 3b, the gate electrode 13 and the common electrode 17 of the capacitor are formed. These two electrodes may be formed simultaneously from the same conductive material. Next, Figure 3c
After forming source/drain regions 10 and 11 by doping with impurities, an interlayer insulating film 14 is deposited, and contact holes are opened. There are various methods for doping impurities into the source/drain regions, but thermal diffusion methods or ion implantation methods are common. After this, Figure 3 d
The data line 15 is formed as shown in FIG.
The driving electrode 16 is formed as shown in FIG. Note that after forming the drive electrode 16, the data line 15 is
may be formed.

第２図及び第３図に見られる本発明の特徴は、
チヤネル領域に真性多結晶シリコン薄膜を用いる
こと、及びゲート絶縁膜に真性多結晶シリコンの
熱酸化膜を用いることの２点である。以下、順を
向つて、各点について説明する。 The features of the present invention seen in FIGS. 2 and 3 are:
There are two points: using an intrinsic polycrystalline silicon thin film for the channel region, and using a thermally oxidized intrinsic polycrystalline silicon film for the gate insulating film. Each point will be explained below in order.

第１に、チヤネル領域に真性多結晶シリコン薄
膜を用いるのは、ON電流を大きくすると同時に
OFF電流を小さくするためである。すなわち、
多結晶シリコンは約10cm2／Ｖ・secという大きな
キヤリア移動度を有しているため、アクテイブマ
トリツクス基板に応用するに十分なON電流を得
ることができる。また、不純物をドープしない真
性形を用いることによりOFF電流を最小にする
ことができる。単結晶シリコンを用いる通常の
MOS型トランジスタでは、Ｎチヤネルの場合、
Ｐ型基板を、Ｐチヤネルの場合、Ｎ型基板を用
い、PN接合を利用してソース・ドレイン間の
OFF電流を低減しているが、多結晶シリコンで
は良質なPN接合が形成できず、したがつてOFF
電流を十分低減させることができない。第４図
は、本出願人の行なつた実験のデータであり、Ｎ
チヤネル薄膜トランジスタにおけるチヤネル領域
の不純物濃度とOFF電流の関係を示すグラフで
ある。不純物はボロンであり、チヤネル領域をＰ
型にすることを目的としている。ドーピングはイ
オン打込み法により、グラフの横軸はボロンのド
ーズ量、縦軸はゲート電圧がOVにおけるOFF電
流である。このグラフからわかるように、ドーズ
量が０の場合、すなわち真性多結晶シリコンを用
いた場合にOFF電流が最小となる。これは不純
物濃度が高くなるにつれてPN接合のリーク電流
が増大するためである。また、逆にチヤネル領域
をＮ型にした場合には、述べるまでもなくトラン
ジスタはデプリーシヨン型となり、OFF電流は
増大する。したがつて、真性多結晶シリコンを用
いた場合に、OFF電流は最小となる。 First, using an intrinsic polycrystalline silicon thin film in the channel region increases the ON current and at the same time
This is to reduce the OFF current. That is,
Since polycrystalline silicon has a large carrier mobility of approximately 10 cm 2 /V·sec, it is possible to obtain an ON current sufficient for application to an active matrix substrate. Furthermore, by using an intrinsic type that is not doped with impurities, the OFF current can be minimized. Ordinary using single crystal silicon
For MOS type transistors, in the case of N channel,
In the case of a P channel, an N type substrate is used to connect the source and drain between the source and drain using a PN junction.
Although the OFF current is reduced, polycrystalline silicon cannot form a high-quality PN junction, so the OFF current is
The current cannot be reduced sufficiently. Figure 4 shows data from experiments conducted by the applicant, with N
2 is a graph showing the relationship between impurity concentration in a channel region and OFF current in a channel thin film transistor. The impurity is boron, and the channel region is P
It is intended to be molded. The doping was done by ion implantation, and the horizontal axis of the graph is the boron dose, and the vertical axis is the OFF current when the gate voltage is OV. As can be seen from this graph, the OFF current is minimum when the dose is 0, that is, when intrinsic polycrystalline silicon is used. This is because the leakage current of the PN junction increases as the impurity concentration increases. On the other hand, if the channel region is made N-type, the transistor becomes a depletion type, needless to say, and the OFF current increases. Therefore, when using intrinsic polycrystalline silicon, the OFF current is minimized.

第２に、ゲート絶縁膜に真性多結晶シリコンの
熱酸化膜を用いるのは、ON電流を大きくすると
同時に、安定性、再現性、及び信頼性の優れた薄
膜トランジスタを実現するためである。すなわち
多結晶シリコンを熱酸化するには通常900℃以上
の高温での熱処理が必要となるが、この際、多結
晶シリコンの結晶粒が成長し、移動度は大幅に増
大する。また、周知の通り、熱酸化によりゲート
絶縁膜を形成した場合、外部からSiO2膜を堆積
させた場合（例えばスパツタ法や気相成長法など
による。）に比べてシリコンとその熱酸化膜との
間の界面準位を小さな値に抑制することが可能と
なり、したがつてトランジスタのスレツシヨルド
電圧を小さくすることができる。つまり、移動度
を大きくし、スレシヨルド電圧を小さくすること
により、大きなON電流が得られる。さらに、熱
酸化によりゲート絶縁膜を形成するという方法
は、通常のMOS型トランジスタを製造する場合
に取られている方法であり、安定性・再現性、及
び信頼性の優れたトランジスタを実現することが
可能となる。すなわち、常に界面準位の小さい優
れた界面を安定に形成することができ、トランジ
スタ特性の安定性・再現性が著しく向上し、ま
た、安定な材料であるシリコン及びその酸化膜を
用い、通常のシリコンテクノロジーと同じ方法に
よりその界面を形成するため、トランジスタ特性
の信頼性は飛躍的に向上する。 Second, the purpose of using a thermal oxide film of intrinsic polycrystalline silicon for the gate insulating film is to increase the ON current and at the same time realize a thin film transistor with excellent stability, reproducibility, and reliability. That is, thermal oxidation of polycrystalline silicon usually requires heat treatment at a high temperature of 900° C. or higher, but at this time, crystal grains of polycrystalline silicon grow and mobility increases significantly. In addition, as is well known, when a gate insulating film is formed by thermal oxidation, compared to when a SiO 2 film is deposited from the outside (for example, by sputtering or vapor phase growth), silicon and its thermal oxide film are It becomes possible to suppress the interface state between the two to a small value, and therefore the threshold voltage of the transistor can be reduced. In other words, by increasing the mobility and decreasing the threshold voltage, a large ON current can be obtained. Furthermore, the method of forming a gate insulating film by thermal oxidation is the method used when manufacturing ordinary MOS transistors, and it is possible to realize transistors with excellent stability, reproducibility, and reliability. becomes possible. In other words, it is possible to always stably form an excellent interface with a small interface state, and the stability and reproducibility of transistor characteristics are significantly improved. Because the interface is formed using the same method as silicon technology, the reliability of transistor characteristics is dramatically improved.

以上述べたように、本発明は優れた特性の薄膜
トランジスタを用いたアクテイブマトリツクス基
板を提供するものであるが、薄膜トランジスタの
ゲート絶縁膜として多結晶シリコンの熱酸化膜を
用いるため、どうしても900℃以上の熱工程が必
要となる。したがつて、基板としてはそのような
高温に耐え得る高融点絶縁基板（例えば石英ガラ
ス）を用いなくてはならない。一般に、石英のよ
うな高融点絶縁基板は他の低融点絶縁基板に比べ
て高価であり、製造されたアクテイブマトリツク
ス基板全体のコストを引き上げることになる。し
たがつて、コストの上昇分を他の部分のコスト低
減により吸収することが必要となる。通常、アク
テイブマトリツクス基板を製造するにあたつて
は、複雑な製造プロセスを必要とし、コストを低
減させるには製造プロセスを簡略化することが有
効である。本発明では、このような観点から製造
プロセスを簡略化するアクテイブマトリツクス基
板の構造も提供する。すなわち、データ線及び駆
動電極を同一の透明導電膜で形成する。 As described above, the present invention provides an active matrix substrate using thin film transistors with excellent characteristics, but since a thermal oxide film of polycrystalline silicon is used as the gate insulating film of the thin film transistor, it is inevitable that the A thermal process is required. Therefore, a high melting point insulating substrate (for example, quartz glass) that can withstand such high temperatures must be used as the substrate. Generally, high melting point insulating substrates such as quartz are more expensive than other low melting point insulating substrates, increasing the overall cost of the manufactured active matrix substrate. Therefore, it is necessary to absorb the increase in cost by reducing costs in other parts. Normally, manufacturing an active matrix substrate requires a complicated manufacturing process, and it is effective to simplify the manufacturing process to reduce costs. From this point of view, the present invention also provides an active matrix substrate structure that simplifies the manufacturing process. That is, the data line and the drive electrode are formed of the same transparent conductive film.

第５図は、データ線及び駆動電極を同一の透明
導電膜で形成した場合のアクテイブマトリツクス
基板の構造を示すものである。データ線１５及び
駆動電極１６は同一の透明導電膜で形成され、そ
れ以外の基本的な構造は第２図に示したものと同
じである。透明導電膜としては、酸化インジウ
ム、酸化スズ、酸化インジウムスズなどが用いら
れる。このような構造を取ることにより、第２図
ｄの工程を省略することができる。一般に半導体
デバイスを製造する上でのプロセスコストは、パ
ターニング工程（フオトエツチング工程）の占め
る比率が大きく、プロセスコストを下げるために
はパターニング工程を減少させることが最も有効
である。第２図に示した製造プロセスではパター
ニング工程を５回必要としているが、第５図に示
した構造を実現するには４回のパターニング工程
で済む。しかも、２種類の導電膜を堆積させる必
要がなく、全体として大幅な工程の簡略化が実現
される。このような工程の簡略化は、安価なアク
テイブマトリツクス基板を実現する上で極めて有
効である。 FIG. 5 shows the structure of an active matrix substrate in which data lines and drive electrodes are formed of the same transparent conductive film. The data line 15 and the drive electrode 16 are formed of the same transparent conductive film, and the other basic structure is the same as that shown in FIG. Indium oxide, tin oxide, indium tin oxide, etc. are used as the transparent conductive film. By adopting such a structure, the step shown in FIG. 2d can be omitted. Generally, the patterning process (photoetching process) accounts for a large proportion of the process cost in manufacturing semiconductor devices, and the most effective way to reduce the process cost is to reduce the number of patterning processes. Although the manufacturing process shown in FIG. 2 requires five patterning steps, four patterning steps are required to realize the structure shown in FIG. 5. Moreover, there is no need to deposit two types of conductive films, and the overall process can be significantly simplified. Such simplification of the process is extremely effective in realizing an inexpensive active matrix substrate.

以上述べたように、本発明はON電流、OFF電
流、安定性、再現性、信頼性の面で極めて優れた
特性を有する薄膜トランジスタを用いたアクテイ
ブマトリツクス基板を提供し、さらに、製造プロ
セスを簡略化することによりコストを低減させる
という優れた効果を有するものである。 As described above, the present invention provides an active matrix substrate using thin film transistors that has extremely excellent characteristics in terms of ON current, OFF current, stability, reproducibility, and reliability, and further simplifies the manufacturing process. It has the excellent effect of reducing costs by

【図面の簡単な説明】[Brief explanation of drawings]

第１図は薄膜トランジスタを用いたアクテイブ
マトリツクス基板の一般的な回路図である。第２
図は本発明によるアクテイブマトリツクス基板の
構造を示す断面図の一例である。第３図は、第２
図に示したアクテイブマトリツクス基板の製造方
法を示す図である。第４図は、Ｎチヤネル薄膜ト
ランジスタにおいて、チヤネル領域の不純物濃度
とOFF電流との関係を示すグラフである。第５
図は、データ線と駆動電極を同一の透明導電膜で
構成した場合のアクテイブマトリツクス基板の構
造を示す断面図の一例である。 FIG. 1 is a general circuit diagram of an active matrix substrate using thin film transistors. Second
The figure is an example of a sectional view showing the structure of an active matrix substrate according to the present invention. Figure 3 shows the second
FIG. 3 is a diagram showing a method of manufacturing the active matrix substrate shown in the figure. FIG. 4 is a graph showing the relationship between the impurity concentration in the channel region and the OFF current in an N-channel thin film transistor. Fifth
The figure is an example of a cross-sectional view showing the structure of an active matrix substrate in which data lines and drive electrodes are made of the same transparent conductive film.

Claims (1)

【特許請求の範囲】[Claims] １ 基板上に形成された薄膜トランジスタにおい
て、不純物がドープされていない真性多結晶シリ
コン薄膜よりなるチヤンネル領域と、該真性多結
晶シリコン薄膜を熱酸化することにより形成され
たゲート酸化膜を有することを特徴とする薄膜ト
ランジスタ。1. A thin film transistor formed on a substrate, characterized by having a channel region made of an intrinsic polycrystalline silicon thin film that is not doped with impurities, and a gate oxide film formed by thermally oxidizing the intrinsic polycrystalline silicon thin film. thin film transistor.
JP57143786A 1982-04-13 1982-08-19 Active matrix substrate Granted JPS5933877A (en)

Priority Applications (14)

Application Number Priority Date Filing Date Title
JP57143786A JPS5933877A (en) 1982-08-19 1982-08-19 Active matrix substrate
FR8305592A FR2527385B1 (en) 1982-04-13 1983-04-06 THIN FILM TRANSISTOR AND LIQUID CRYSTAL DISPLAY PANEL USING THIS TYPE OF TRANSISTOR
DE3348083A DE3348083C2 (en) 1982-04-13 1983-04-08
DE3312743A DE3312743C2 (en) 1982-04-13 1983-04-08 Thin film MOS transistor and use of the same as a switching element in an active matrix arrangement
GB08309750A GB2118365B (en) 1982-04-13 1983-04-11 A thin film mos transistor and an active matrix liquid crystal display device
FR838320366A FR2536194B1 (en) 1982-04-13 1983-12-20 THIN FILM TRANSISTOR AND LIQUID CRYSTAL DISPLAY PANEL USING THIS TYPE OF TRANSISTOR
HK886/87A HK88687A (en) 1982-04-13 1987-11-26 A thin film mos transistor and an active matrix liquid crystal display device
US07/203,548 US5124768A (en) 1982-04-13 1988-05-31 Thin film transistor and active matrix assembly including same
US07/828,548 US5294555A (en) 1982-04-13 1992-01-30 Method of manufacturing thin film transistor and active matrix assembly including same
US08/320,729 US6294796B1 (en) 1982-04-13 1994-10-11 Thin film transistors and active matrices including same
US08/388,900 US5554861A (en) 1982-04-13 1995-02-14 Thin film transistors and active matrices including the same
US08/402,374 US6242777B1 (en) 1982-04-13 1995-03-13 Field effect transistor and liquid crystal devices including the same
US08/413,369 US5736751A (en) 1982-04-13 1995-03-30 Field effect transistor having thick source and drain regions
US08/452,370 US5698864A (en) 1982-04-13 1995-05-26 Method of manufacturing a liquid crystal device having field effect transistors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57143786A JPS5933877A (en) 1982-08-19 1982-08-19 Active matrix substrate

Publications (2)

Publication Number Publication Date
JPS5933877A JPS5933877A (en) 1984-02-23
JPH0371793B2 true JPH0371793B2 (en) 1991-11-14

Family

ID=15346961

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57143786A Granted JPS5933877A (en) 1982-04-13 1982-08-19 Active matrix substrate

Country Status (1)

Country Link
JP (1) JPS5933877A (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06105317B2 (en) * 1986-02-06 1994-12-21 三菱原子燃料株式会社 Decontamination method
JPH0244317A (en) * 1988-08-05 1990-02-14 Hitachi Ltd Liquid crystal display device with auxiliary capacity
JPH06291316A (en) * 1992-02-25 1994-10-18 Semiconductor Energy Lab Co Ltd Thin film insulated gate semiconductor device and manufacture thereof
US6028333A (en) * 1991-02-16 2000-02-22 Semiconductor Energy Laboratory Co., Ltd. Electric device, matrix device, electro-optical display device, and semiconductor memory having thin-film transistors
TW222345B (en) * 1992-02-25 1994-04-11 Semicondustor Energy Res Co Ltd Semiconductor and its manufacturing method
US6709907B1 (en) 1992-02-25 2004-03-23 Semiconductor Energy Laboratory Co., Ltd. Method of fabricating a thin film transistor

Also Published As

Publication number Publication date
JPS5933877A (en) 1984-02-23

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