JPS5933877A - Active matrix substrate - Google Patents

Active matrix substrate

Info

Publication number
JPS5933877A
JPS5933877A JP57143786A JP14378682A JPS5933877A JP S5933877 A JPS5933877 A JP S5933877A JP 57143786 A JP57143786 A JP 57143786A JP 14378682 A JP14378682 A JP 14378682A JP S5933877 A JPS5933877 A JP S5933877A
Authority
JP
Japan
Prior art keywords
current
thin film
polycrystalline silicon
active matrix
matrix substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57143786A
Other languages
Japanese (ja)
Other versions
JPH0371793B2 (en
Inventor
Hiroyuki Oshima
弘之 大島
Toshimoto Kodaira
小平　寿源
Toshihiko Mano
真野　敏彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP57143786A priority Critical patent/JPS5933877A/en
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to FR8305592A priority patent/FR2527385B1/en
Priority to DE3312743A priority patent/DE3312743C2/en
Priority to DE3348083A priority patent/DE3348083C2/de
Priority to GB08309750A priority patent/GB2118365B/en
Priority to FR838320366A priority patent/FR2536194B1/en
Publication of JPS5933877A publication Critical patent/JPS5933877A/en
Priority to HK886/87A priority patent/HK88687A/en
Priority to US07/203,548 priority patent/US5124768A/en
Publication of JPH0371793B2 publication Critical patent/JPH0371793B2/ja
Priority to US07/828,548 priority patent/US5294555A/en
Priority to US08/320,729 priority patent/US6294796B1/en
Priority to US08/388,900 priority patent/US5554861A/en
Priority to US08/402,374 priority patent/US6242777B1/en
Priority to US08/413,369 priority patent/US5736751A/en
Priority to US08/452,370 priority patent/US5698864A/en
Granted legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/13—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body combined with thin-film or thick-film passive components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor
    • G02F2202/104—Materials and properties semiconductor poly-Si
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78666—Amorphous silicon transistors with normal-type structure, e.g. with top gate

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  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Nonlinear Science (AREA)
  • Liquid Crystal (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Manufacturing & Machinery (AREA)

Abstract

PURPOSE:To obtain an inexpensive active matrix substrate which uses thin film transistors having sufficiently large ON current, a sufficiently small OFF current and excellent reproducibility and reliability by employing a true polycrystalline silicon thin film on a channel region and a true polycrystalline silicon thermally oxidized film on a gate insulated film. CONSTITUTION:After a true polycrystalline silicon 9 is accumulated on an insulating substrate 8, a thermal oxidation is performed, thereby forming a gate insulated film 12. Then, a gate electrode 13 and a common electrode 17 of a condenser are formed. These two electrodes may be formed of the same conductive material simultaneously. Subsequently, after an impurity is doped to form source and drain regions 10, 11, an interlayer insulated film 14 is accumulated, and a contacting hole is opened. The doping of the impurity to the source and drain regions is performed by thermal diffusion or ion implantation. Subsequently, a gate line 15 is formed, and a drive electrode 16 is then formed to complete it. In this manner, the true polycrystalline silicon thin film is used to increase the ON current in the channel region, and the OFF current is reduced. Further, the impurity is not doped in a true shape, thereby minimizing the OFF current.

Description

【発明の詳細な説明】 本発明は薄膜トランジスタを用いたアクティブマトリッ
クス基板に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an active matrix substrate using thin film transistors.

近年、絶縁基板上に薄膜トランジスタを形成する研究が
活発に行なわれている。その目的の１つには、安価な絶
縁基板を用いた薄形ディスプレイの実現が挙げられる。In recent years, research on forming thin film transistors on insulating substrates has been actively conducted. One of the objectives is to realize a thin display using an inexpensive insulating substrate.

すなわち、絶縁基板上に薄膜トランジスタをマトリック
ス状に形成し、そのスイッチング特性を応用して液晶等
による薄形ディスプレイを目指すものである。このよう
にして構成されたアクティブマトリックス基板は、非常
に安価に製作できる可能性がある。That is, the aim is to form thin film transistors in a matrix on an insulating substrate and apply their switching characteristics to create a thin display using liquid crystal or the like. An active matrix substrate configured in this manner may be manufactured at a very low cost.

薄膜トランジスタをアクティブマトリックス基板に応用
した場合の液晶表示装置は、一般に、上側のガラス基板
と、下側の薄膜トランジスタ基板と、その間に封入され
た液晶とから構成されており、前記薄膜トランジスタ基
板上にマトリックス状に配置された液晶駆動素子を外部
選択回路により選択し、前記液晶駆動素子に接続された
液晶駆動電極に電圧を印加することにより、任意の文字
、図形、あるいは画像の表示を行なうものである。前記
薄膜トランジスタ基板の一般的な回路図を第１図に示す
。A liquid crystal display device in which a thin film transistor is applied to an active matrix substrate is generally composed of an upper glass substrate, a lower thin film transistor substrate, and a liquid crystal sealed between them. An external selection circuit selects a liquid crystal drive element arranged in the liquid crystal drive element, and a voltage is applied to a liquid crystal drive electrode connected to the liquid crystal drive element, thereby displaying arbitrary characters, figures, or images. A general circuit diagram of the thin film transistor substrate is shown in FIG.

第１図（α）は薄膜トランジスタ基板上の液晶駆動素子
のマトリックス状配置図である。図中の１で囲まれた領
域が表示領域であり、その中に液晶駆動素子２がマトリ
ックス状に配置されている。３は液晶駆動素子２へのデ
ータ線であり、４は液晶駆動素子２へのアドレス線であ
る。液晶駆動素子２の回路図を第１図Ｃｈ）に示す。５
は薄膜トランジスタであり、データのスイッチングを行
なう。６はコンデンサであり、データ信号の保持用とし
て用いられる。７は液晶パネルであり、７−１は各液晶
駆動素子に対応して形成された駆動電極であり、７−２
は上側ガラスパネルである。FIG. 1(α) is a matrix layout diagram of liquid crystal driving elements on a thin film transistor substrate. The area surrounded by 1 in the figure is the display area, and the liquid crystal drive elements 2 are arranged in a matrix within the area. 3 is a data line to the liquid crystal driving element 2, and 4 is an address line to the liquid crystal driving element 2. A circuit diagram of the liquid crystal driving element 2 is shown in FIG. 5
is a thin film transistor and performs data switching. 6 is a capacitor, which is used for holding data signals. 7 is a liquid crystal panel, 7-1 is a drive electrode formed corresponding to each liquid crystal drive element, and 7-2 is a liquid crystal panel.
is the upper glass panel.

以上の説明かられかるように、液晶駆動素子内の薄膜ト
ランジスタは、液晶に印加する電圧のデータをスイッチ
ングするために用いられ、その特性により、アクティブ
マトリックス基板全体の性能が決定されるといっても過
言ではない。しだがって、薄膜トランジスタは仕様を十
分に満足するものでなくてはならない。薄膜トランジス
タに要求される特性は次のようなものが挙げられる。As can be seen from the above explanation, the thin film transistor in the liquid crystal driving element is used to switch the voltage data applied to the liquid crystal, and its characteristics determine the performance of the entire active matrix substrate. It's not too much to say. Therefore, the thin film transistor must fully satisfy the specifications. The characteristics required of thin film transistors include the following.

（１）　　薄膜トランジスタをＯＮ状態にした時、コン
デンサを充電させるために充分な電流を流すことができ
ること。(1) When the thin film transistor is turned on, sufficient current can flow to charge the capacitor.

（２）　　薄膜トランジスタをＯＦＦ状態にした時、極
力、電流が流れないこと。(2) When the thin film transistor is turned off, as little current as possible should flow through it.

（８）特性の安定性・再現性に優れ、十分な長期信頼性
を有していること。(8) Excellent stability and reproducibility of characteristics, and sufficient long-term reliability.

（１）はコンデンサへのデータの書き込み特性に関する
ものである。液晶の表示はコンデンサの電位により決定
されるため、短時間Ｇこデータを完壁に書き込むことが
できるように、薄膜トランジスタは十分大きい電流を流
すことができなくてはならない。このときの電流（以下
、ＯＮ電流という。）は、コンデンサの容量と書き込み
時間とから定まり、そのＯＮ電流をクリアできるように
薄膜トランジスタを製造しなくてはならない。(1) relates to the characteristics of writing data to the capacitor. Since the liquid crystal display is determined by the potential of the capacitor, the thin film transistor must be able to flow a sufficiently large current so that G data can be completely written in a short period of time. The current at this time (hereinafter referred to as ON current) is determined by the capacitance of the capacitor and the write time, and the thin film transistor must be manufactured so as to be able to clear the ON current.

（２）はコンデンサに書き込まれたデータの保持特性に
関するものである。一般に、書き込まれたデータは書き
込み時間よりもはるかに長い時間、保持されなくてはな
らない。コンデンサの静電容量は通常ＩＰＦ程度の小さ
い値であるため、薄膜トランジスタがＯ’Ｆ１ｒ状態の
ときの電流（以下、ＯＦＦ電流という。）がわずかでも
流れると、駆動電極の電位は急激にデータ線の電位に近
づき書き込まれたデータは正しく保持されなくなってし
まう。したがって、薄膜トランジスタのＯＦＦ電流は極
力小さくする必要がある。(2) relates to the retention characteristics of data written to the capacitor. Generally, written data must be retained for a much longer time than the write time. The capacitance of a capacitor is usually as small as an IPF, so if even a small amount of current flows when the thin film transistor is in the O'F1r state (hereinafter referred to as OFF current), the potential of the drive electrode will suddenly change to that of the data line. As the voltage approaches the potential, written data will no longer be held correctly. Therefore, it is necessary to reduce the OFF current of the thin film transistor as much as possible.

（８）はトランジスタ特性の安定性・再現性及び信頼性
に関するものである。通常、１枚のアクティブマトリッ
クス基板上には、数万個の薄膜トランジスタが集積され
るが、それらはすべて均一な特性を有していなくてはな
らない。また、製造ロット間における特性の再現性も非
常に重要となる。さらに、トランジスタ特性は長期にわ
たって安定であり、十分な信頼性を有していなくてはな
らない以上述べたように、アクティブマトリックス基板
に用いる薄膜トランジスタには、数多くの厳しい特性が
要求される。(8) relates to stability, reproducibility, and reliability of transistor characteristics. Typically, tens of thousands of thin film transistors are integrated on a single active matrix substrate, and all of them must have uniform characteristics. Furthermore, reproducibility of characteristics between production lots is also very important. Furthermore, the transistor characteristics must be stable over a long period of time and must have sufficient reliability.As described above, thin film transistors used in active matrix substrates are required to meet a number of strict characteristics.

従来、薄膜トランジスタをアクティブマトリックス基板
に応用する場合、半導体薄膜としては、カドミウムセレ
ンなどの化合物半導体、あるいはアモルファスシリコン
などの非晶質半導体などが用いられてきた。しかし、現
在のところ、前述の３つの要求項目をすべて満足するも
のは作られていない。例えば、化合物半導体の場合、キ
ャリアの移動度が比較的大きいため、（１）の項目は容
易に満たされるが；（２）及び（８）の項目は満たされ
ていない。特に、再現性及び信頼性が著しく悪く、この
ため長い歴史を有しながらも今だに実用化されていない
。また、非晶質半導体の場合、（２）の項目は十分溝た
されるが、（１）及び（８）の項目は満たされていない
。非晶質半導体では移動度が小さいため、本質的にＯＮ
電流は小さくなる。Conventionally, when thin film transistors are applied to active matrix substrates, compound semiconductors such as cadmium selenium, or amorphous semiconductors such as amorphous silicon have been used as semiconductor thin films. However, at present, no one has been manufactured that satisfies all three of the above-mentioned requirements. For example, in the case of a compound semiconductor, since the carrier mobility is relatively high, item (1) is easily satisfied; items (2) and (8) are not satisfied. In particular, the reproducibility and reliability are extremely poor, and for this reason, although it has a long history, it has not yet been put into practical use. In addition, in the case of an amorphous semiconductor, item (2) is satisfactorily satisfied, but items (1) and (8) are not satisfied. Amorphous semiconductors have low mobility, so they are essentially ON.
The current becomes smaller.

このように、現在のところ、優れた特性を有する薄膜ト
ランジスタを用いたアクティブマトリックス基板は実現
されていない。As described above, at present, an active matrix substrate using thin film transistors having excellent characteristics has not been realized.

本発明はこのような従来の欠点を除去するものであり、
その目的は、十分大きいＯＮ電流と十分率さいＯＦＦ電
流、及び優れた再現性と信頼性を有する薄膜ｌ・ランジ
スタを用いた安価なアクティブマトリックス基板を提供
することである。以下、実施例（こ基づいて、本発明の
詳細な説明する。The present invention eliminates these conventional drawbacks,
The objective is to provide an inexpensive active matrix substrate using thin film transistors with sufficiently large ON current, sufficiently low OFF current, and excellent reproducibility and reliability. Hereinafter, the present invention will be described in detail based on Examples.

第２図は本発明によるアクティブマトリックス基板の構
造を示す断面図の一例である。ここでは簡単のため、１
つの液晶駆動繁子についてのみ記しである。石英などの
絶縁基板８上に多結晶シリコンを堆積し、これを薄膜ト
ランジスタの半導体母材とする。チャネル領域は真性多
結晶シリコン９で構成され、ソース・ドレイン領域はリ
ン、ヒ素９ボロンなどの不純物をドープした外因性多結
晶シリコン１０．１１で構成される。ゲート絶縁膜１２
は真性多結晶シリコン９の熱酸化膜で構成される。１３
はゲート電極となるアドレス線、１４は層間絶縁膜、１
５はソース電極またはドレイン電極となるデータ線、１
６はドレイン電極またはソース電極となる駆動電極であ
る。１７はデータ蓄積用コンデンサのコモン電極である
。１５絶縁膜１４はコンデンサの誘電体も兼ねている。FIG. 2 is an example of a cross-sectional view showing the structure of an active matrix substrate according to the present invention. Here, for simplicity, 1
Only the two liquid crystal driven Shigeko are described here. Polycrystalline silicon is deposited on an insulating substrate 8 such as quartz, and this is used as a semiconductor base material of a thin film transistor. The channel region is made of intrinsic polycrystalline silicon 9, and the source/drain regions are made of extrinsic polycrystalline silicon 10 and 11 doped with impurities such as phosphorus, arsenic, and boron. Gate insulating film 12
is composed of a thermally oxidized film of intrinsic polycrystalline silicon 9. 13
1 is an address line serving as a gate electrode; 14 is an interlayer insulating film;
5 is a data line that becomes a source electrode or a drain electrode; 1
Reference numeral 6 denotes a drive electrode serving as a drain electrode or a source electrode. 17 is a common electrode of a data storage capacitor. 15 The insulating film 14 also serves as the dielectric of the capacitor.

第３図は、第２図に示したアクティブマトリックス基板
の製造方法の１例を示すものである。まず第３図（α）
のように、絶縁基板８上に真性多結晶シリコン２を堆積
した後、熱酸化を行ないゲート絶縁膜１２を形成する。FIG. 3 shows an example of a method for manufacturing the active matrix substrate shown in FIG. 2. First, Figure 3 (α)
After depositing intrinsic polycrystalline silicon 2 on an insulating substrate 8, thermal oxidation is performed to form a gate insulating film 12, as shown in FIG.

次に、第３図Ｃｂ）のように、ゲート電極１３及びコン
デンサのコモン電極１７を形成する。この２つの電極は
、同一の導電材料で同時に形成して構わない。次に、第
３図（Ｃ）のように、不純物をドープすることによりソ
ース・ドレイン領域１０．１１を形成した後、層間絶縁
膜１４を堆積し、コンタクトホールを開口する。ソース
・ドレイン領域への不純物のドーピングには種々の方法
があるが、熱拡散法あるいはイオン打込み法が一般的で
ある。この後、第３図（ｄ、）のようにデータ線１５を
形成し、さらに第３１ｆｆｌ（ｉのように駆動電極１６
を形成して完成される。なお、駆動電極１６を形成した
後に、データ線１５を形成してもよい。Next, as shown in FIG. 3Cb), the gate electrode 13 and the common electrode 17 of the capacitor are formed. These two electrodes may be formed simultaneously from the same conductive material. Next, as shown in FIG. 3C, after forming source/drain regions 10.11 by doping impurities, an interlayer insulating film 14 is deposited, and contact holes are opened. There are various methods for doping impurities into the source/drain regions, but thermal diffusion methods or ion implantation methods are common. After that, the data line 15 is formed as shown in FIG. 3(d), and the drive electrode 16 is further formed as shown in FIG.
is formed and completed. Note that the data line 15 may be formed after the drive electrode 16 is formed.

第２図及び第３図に見られる本発明の特徴は、チャネル
領域に真性多結晶シリコン薄膜を用いること、及びゲー
ト絶縁膜に真性多結晶シリコンの熱酸化膜を用いること
の２点である。以下、順を向って、各点について説明す
る。The features of the present invention shown in FIGS. 2 and 3 are the use of an intrinsic polycrystalline silicon thin film for the channel region and the use of a thermally oxidized intrinsic polycrystalline silicon film for the gate insulating film. Each point will be explained below in order.

第１に、チャネル領域に真性多結晶シリコン薄膜を用い
るのは、ＯＮ電流を大きくすると同時に０１１’？電流
を小さくするためである。すなわち、多結晶シリコンは
約１０．−、！／Ｖ・度という大きなキャリア移動度を
有しているため、アクティブマトリックス基板に応用す
るに十分なＯＮ電流を得ることができる。また、不純物
をドープしない真性形を用いることによりＯ］Ｉ’Ｆｉ
Ｉ流を最小にすることができる。単結晶シリコンを用い
る通常のＭＯ８型トランジスタでは、Ｎチャネルの場合
、Ｐ型基板を、Ｐチャネルの場合、Ｎ型基板を用い、Ｐ
Ｎ接合を利用してソース・ドレイン間のＯＦＦ電流を低
減しているが、多結晶シリコンでは良質なＰＭ接合が形
成できず、したがってＯＩ’？電流を十分低減させるこ
とができない。第４図は、本出願人の行なった実験のデ
ータであり、Ｎチャネル薄膜トランジスタにおけるチャ
ネル領域の不純物濃度とＯＦＦ電流の関係を示すグラフ
である。First, using an intrinsic polycrystalline silicon thin film in the channel region increases the ON current and at the same time increases the 011'? This is to reduce the current. That is, polycrystalline silicon has approximately 10. -,! Since it has a large carrier mobility of /V°, it can obtain an ON current sufficient for application to an active matrix substrate. In addition, by using an intrinsic form that is not doped with impurities, O]I'Fi
I current can be minimized. In a normal MO8 type transistor using single crystal silicon, a P type substrate is used for an N channel, an N type substrate is used for a P channel, and a P type substrate is used for a P channel.
Although an N junction is used to reduce the OFF current between the source and drain, a good PM junction cannot be formed with polycrystalline silicon, so OI'? The current cannot be reduced sufficiently. FIG. 4 shows data from experiments conducted by the present applicant, and is a graph showing the relationship between the impurity concentration of the channel region and the OFF current in an N-channel thin film transistor.

不純物はボロンであり、チャネル領域をＰ型にすること
を目的としている。ドーピングはイオン打込み法により
、グラフの横軸はボロンのドーズ量、縦軸はゲート電圧
がＯＶにおけるＯＦＦ電流である。このグラフかられか
るように、ドーズ量が００場合、すなわち真性多結晶シ
リコンを用いた場合にＯＦＦ電流が最小となる。これは
不純物濃度が高くなるにつれてＰＮ接合のリーク電流が
増大するためである。また、逆にチャネル領域をＮ型に
した場合には、述べるまでもなくトランジスタはデプリ
ーション型となり、ＯＦ’Ｅ’電流は増大する。したが
って、真性多結晶シリコンを用いた場合に、ＯＦＦ電流
は最小となる。The impurity is boron, and the purpose is to make the channel region P type. The doping was done by ion implantation, and the horizontal axis of the graph is the boron dose, and the vertical axis is the OFF current when the gate voltage is OV. As can be seen from this graph, the OFF current is minimum when the dose is 00, that is, when intrinsic polycrystalline silicon is used. This is because the leakage current of the PN junction increases as the impurity concentration increases. On the other hand, if the channel region is made N-type, the transistor becomes a depletion type, needless to say, and the OF'E' current increases. Therefore, when intrinsic polycrystalline silicon is used, the OFF current is minimized.

第２に、ゲート絶縁膜に真性多結晶シリコンの熱酸化膜
を用いるのは、ＯＨ％、流を大きくすると同時に、安定
性、再現性、及び信頼性の優れた薄膜トランジスタを実
現するためである。すなわち多結晶シリコンを熱酸化す
るには通常９００℃以上の高温での熱処理が必要となる
が、この際、多結晶シリコンの結晶粒が成長し、移動度
は大幅に増大する。また、周知の通り、熱酸化によりゲ
ート絶縁膜を形成した場合、外部から３１０．膜全堆積
させた場合（例えばスパッタ法や気相成長法などによる
。）に比べてシリコンとその熱酸化膜との間の界面準位
を小ざな値に抑制することが可能となり、したがってト
ランジスタのスレッショルド電圧を小さくすることがで
きる。つまり、移動度を大きくし、スレショルド電圧を
小さくすることにより、大きなＯＮ電流が得られる。さ
らに、熱酸化によりゲート絶縁膜を形成するという方法
は、通常のＭＯ３型トランジスタを製造する場合に取ら
れている方法であり、安定性・再現性、及び信頼性の優
れたトランジスタを実現することが可能となる。すなわ
ち、常に界面準位の小さい優れた界面を安定に形成する
ことができ、トランジスタ特性の安定性・再現性が著し
く向上し、また、安定な材料であるシリコン及びその酸
化膜を用い、通常のシリコンテクノロジーと同じ方法に
よりその界面を形成するため、トランジスタ特性の信頼
性は飛躍的に向上する。Second, the reason why a thermally oxidized film of intrinsic polycrystalline silicon is used for the gate insulating film is to increase the OH% and current, and at the same time realize a thin film transistor with excellent stability, reproducibility, and reliability. That is, thermal oxidation of polycrystalline silicon usually requires heat treatment at a high temperature of 900° C. or higher, but at this time, crystal grains of polycrystalline silicon grow and mobility increases significantly. Furthermore, as is well known, when a gate insulating film is formed by thermal oxidation, 310. Compared to the case where the entire film is deposited (for example, by sputtering or vapor phase growth), it is possible to suppress the interface state between silicon and its thermal oxide film to a small value, and therefore the transistor The threshold voltage can be reduced. In other words, by increasing the mobility and decreasing the threshold voltage, a large ON current can be obtained. Furthermore, the method of forming the gate insulating film by thermal oxidation is the method used when manufacturing ordinary MO3 type transistors, and it is possible to realize transistors with excellent stability, reproducibility, and reliability. becomes possible. In other words, it is possible to always stably form an excellent interface with a small interface state, and the stability and reproducibility of transistor characteristics are significantly improved. Because the interface is formed using the same method as silicon technology, the reliability of transistor characteristics is dramatically improved.

以上述べたように、本発明は優れた特性の薄膜トランジ
スタを用いたアクティブマトリックス基板を提供するも
のであるが、薄膜トランジスタのゲート絶縁膜として多
結晶シリコンの熱酸化膜を用いるため、どうしても９０
０℃以上の熱工程が必要となる。したがって、基板とし
てはそのような高温に耐え得る高融点絶縁基板（例えば
石英ガラス）を用いなくてはならない。一般に、石英の
ような高融点絶縁基板は他の低融点絶縁基板に比べて高
価であり、製造されたアクティブマ）　ＩＪソックス板
全体のコストを引き上げることになる。As described above, the present invention provides an active matrix substrate using thin film transistors with excellent characteristics, but since a polycrystalline silicon thermal oxide film is used as the gate insulating film of the thin film transistor,
A thermal process at 0°C or higher is required. Therefore, a high melting point insulating substrate (for example, quartz glass) that can withstand such high temperatures must be used as the substrate. Generally, high melting point insulating substrates such as quartz are more expensive than other low melting point insulating substrates, increasing the overall cost of the manufactured active material IJ sock board.

したがって、コストの上昇分を他の部分のコスト低減に
より吸収することが必要となる。通常、アクティブマト
リックス基板を製造するにあたっては、複雑な製造プロ
セスを必要とし、コストを低減させるには製造プロセス
を簡略化することが有効である。本発明では、このよう
な観点から製造プロセスを簡略化するアクティブマトリ
ックス基板の構造も提供する。すなわち、データ線及び
駆動電極を同一の透明導電膜で形成する。Therefore, it is necessary to absorb the increase in cost by reducing costs in other parts. Normally, manufacturing an active matrix substrate requires a complicated manufacturing process, and it is effective to simplify the manufacturing process in order to reduce costs. From this perspective, the present invention also provides an active matrix substrate structure that simplifies the manufacturing process. That is, the data line and the drive electrode are formed of the same transparent conductive film.

第５図は、データ線及び駆動電極を同一の透明導電膜で
形成した場合のアクティブマトリックス基板の構造を示
すものである。データ線１５及び駆動電極１６は同一の
透明導電膜で形成され、それ以外の基本的な構造は第２
図に示したものと同じである。透明導電膜としては、酸
化インジウム、酸化スズ、酸化インジウムスズなどが用
いられる。このような構造を取ることにより、第２図（
ｄ）の工程を省略することができる。一般に半導体デバ
イスを製造する上でのプロセスコストは、パターニング
工程（フォトエツチング工程）の占める比率が大きく、
プロセスコストを下げるためにはバターニング工程を減
少させることが最も有効である。第２図に示した製造プ
ロセスではパターニング工程を５回必要としているが、
第５図に示した構造を実現するには４回のバターニング
工程で済む。しかも、２種類の導電膜を堆積させる必要
がなく、全体として大幅な工程の簡略化が実現される。FIG. 5 shows the structure of an active matrix substrate in which data lines and drive electrodes are formed of the same transparent conductive film. The data line 15 and the drive electrode 16 are formed of the same transparent conductive film, and the other basic structure is the second one.
It is the same as shown in the figure. Indium oxide, tin oxide, indium tin oxide, etc. are used as the transparent conductive film. By adopting such a structure, Figure 2 (
Step d) can be omitted. Generally, the patterning process (photoetching process) accounts for a large proportion of the process cost in manufacturing semiconductor devices.
The most effective way to reduce process costs is to reduce the number of buttering steps. The manufacturing process shown in Figure 2 requires a patterning process five times.
In order to realize the structure shown in FIG. 5, four buttering steps are required. Moreover, there is no need to deposit two types of conductive films, and the overall process can be significantly simplified.

このような工程の簡略化は、安価なアクティブマトリッ
クス基板を実現する上で極めて有効である。Such simplification of the process is extremely effective in realizing an inexpensive active matrix substrate.

以上述べたように、本発明はＯＮ％流、ＯＦＦ″電流、
安定性、再現性９信頼性の而で極めて優れた特性を有す
る薄膜トランジスタを用いたアクティブマトリックス基
板を提供し、さらに、製造プロセスを簡略化することに
よりコストを低減させるという優れた効果を有するもの
である。As described above, the present invention provides ON% current, OFF'' current,
It provides an active matrix substrate using thin film transistors that has extremely excellent characteristics in terms of stability and reproducibility, and also has the excellent effect of reducing costs by simplifying the manufacturing process. be.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は薄膜トランジスタを用いたアクティブマ）　Ｉ
Ｊソックス板の一般的な回路図である。 第２図は本発明によるアクティブマトリックス基板の構
造を示す断面図の一例である。 第６図は、第２図に示したアクティブマトリックス基板
の製造方法を示す図である。 第４図は、Ｎチャネル薄膜トランジスタにおいて、チャ
ネル領域の不純物濃度と０ＦＩＩ’電流との関係を示す
グラフである。 第５図は、データ線と駆動電極を同一の透明導電膜で構
成した場合のアクティブマトリックス基板の構造を示す
断面図の一例である。 以　　上 出願人　株式会社諏訪精工舎 代理人　弁理士　最上　　務 八〕　　　　　　　　　　　　　　　り一ノ　　　　　
　　　　　　　　　ν （Ｖ）１≦瀘Ｉ刊ＯFigure 1 shows an active material using thin film transistors)
It is a general circuit diagram of a J-socks board. FIG. 2 is an example of a cross-sectional view showing the structure of an active matrix substrate according to the present invention. FIG. 6 is a diagram showing a method of manufacturing the active matrix substrate shown in FIG. 2. FIG. 4 is a graph showing the relationship between the impurity concentration in the channel region and the 0FII' current in an N-channel thin film transistor. FIG. 5 is an example of a cross-sectional view showing the structure of an active matrix substrate in which the data lines and drive electrodes are made of the same transparent conductive film. Applicant Suwa Seikosha Co., Ltd. Agent Patent Attorney Tsumuhachi Mogami Riichino
ν (V) 1≦瀘I publication O

Claims (2)

【特許請求の範囲】[Claims] （１）　　複数本のアドレス線及び前記アドレス線と直
交する複数本のデータ線を備え、前記アドレス線と前記
データ線との各交点に薄膜トランジスタと駆動電極を有
するアクティブマトリックス基板にオイて、前記薄膜ト
ランジスタは、真性多結晶シリコン薄膜から成るチャネ
ル領域と、前記真性多結晶シリコン薄膜の熱酸化膜から
成るゲート絶縁膜を備えたことを特徴とするアクティブ
マトリックス基板。(1) An active matrix substrate is provided with a plurality of address lines and a plurality of data lines orthogonal to the address lines, and has a thin film transistor and a drive electrode at each intersection of the address line and the data line. An active matrix substrate comprising a channel region made of an intrinsic polycrystalline silicon thin film and a gate insulating film made of a thermally oxidized film of the intrinsic polycrystalline silicon thin film. （２）　前記データ線と前記駆動電極は、同一の透明導
電膜により形成されたことを特徴とする特許請求の範囲
第一項記載のアクティブマ）　ＩＪラックス板。(2) The active material IJ rack plate according to claim 1, wherein the data line and the drive electrode are formed of the same transparent conductive film.
JP57143786A 1982-04-13 1982-08-19 Active matrix substrate Granted JPS5933877A (en)

Priority Applications (14)

Application Number Priority Date Filing Date Title
JP57143786A JPS5933877A (en) 1982-08-19 1982-08-19 Active matrix substrate
FR8305592A FR2527385B1 (en) 1982-04-13 1983-04-06 THIN FILM TRANSISTOR AND LIQUID CRYSTAL DISPLAY PANEL USING THIS TYPE OF TRANSISTOR
DE3312743A DE3312743C2 (en) 1982-04-13 1983-04-08 Thin film MOS transistor and use of the same as a switching element in an active matrix arrangement
DE3348083A DE3348083C2 (en) 1982-04-13 1983-04-08
GB08309750A GB2118365B (en) 1982-04-13 1983-04-11 A thin film mos transistor and an active matrix liquid crystal display device
FR838320366A FR2536194B1 (en) 1982-04-13 1983-12-20 THIN FILM TRANSISTOR AND LIQUID CRYSTAL DISPLAY PANEL USING THIS TYPE OF TRANSISTOR
HK886/87A HK88687A (en) 1982-04-13 1987-11-26 A thin film mos transistor and an active matrix liquid crystal display device
US07/203,548 US5124768A (en) 1982-04-13 1988-05-31 Thin film transistor and active matrix assembly including same
US07/828,548 US5294555A (en) 1982-04-13 1992-01-30 Method of manufacturing thin film transistor and active matrix assembly including same
US08/320,729 US6294796B1 (en) 1982-04-13 1994-10-11 Thin film transistors and active matrices including same
US08/388,900 US5554861A (en) 1982-04-13 1995-02-14 Thin film transistors and active matrices including the same
US08/402,374 US6242777B1 (en) 1982-04-13 1995-03-13 Field effect transistor and liquid crystal devices including the same
US08/413,369 US5736751A (en) 1982-04-13 1995-03-30 Field effect transistor having thick source and drain regions
US08/452,370 US5698864A (en) 1982-04-13 1995-05-26 Method of manufacturing a liquid crystal device having field effect transistors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57143786A JPS5933877A (en) 1982-08-19 1982-08-19 Active matrix substrate

Publications (2)

Publication Number Publication Date
JPS5933877A true JPS5933877A (en) 1984-02-23
JPH0371793B2 JPH0371793B2 (en) 1991-11-14

Family

ID=15346961

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57143786A Granted JPS5933877A (en) 1982-04-13 1982-08-19 Active matrix substrate

Country Status (1)

Country Link
JP (1) JPS5933877A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62182699A (en) * 1986-02-06 1987-08-11 三菱原子燃料株式会社 Decontamination method
JPH0244317A (en) * 1988-08-05 1990-02-14 Hitachi Ltd Liquid crystal display device with auxiliary capacity
JPH06291316A (en) * 1992-02-25 1994-10-18 Semiconductor Energy Lab Co Ltd Thin film insulated gate semiconductor device and manufacture thereof
US5894151A (en) * 1992-02-25 1999-04-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having reduced leakage current
US6028333A (en) * 1991-02-16 2000-02-22 Semiconductor Energy Laboratory Co., Ltd. Electric device, matrix device, electro-optical display device, and semiconductor memory having thin-film transistors
US6709907B1 (en) 1992-02-25 2004-03-23 Semiconductor Energy Laboratory Co., Ltd. Method of fabricating a thin film transistor

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62182699A (en) * 1986-02-06 1987-08-11 三菱原子燃料株式会社 Decontamination method
JPH0244317A (en) * 1988-08-05 1990-02-14 Hitachi Ltd Liquid crystal display device with auxiliary capacity
US6028333A (en) * 1991-02-16 2000-02-22 Semiconductor Energy Laboratory Co., Ltd. Electric device, matrix device, electro-optical display device, and semiconductor memory having thin-film transistors
JPH06291316A (en) * 1992-02-25 1994-10-18 Semiconductor Energy Lab Co Ltd Thin film insulated gate semiconductor device and manufacture thereof
US5894151A (en) * 1992-02-25 1999-04-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having reduced leakage current
US6709907B1 (en) 1992-02-25 2004-03-23 Semiconductor Energy Laboratory Co., Ltd. Method of fabricating a thin film transistor
US7148542B2 (en) 1992-02-25 2006-12-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of forming the same
US7649227B2 (en) 1992-02-25 2010-01-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of forming the same

Also Published As

Publication number Publication date
JPH0371793B2 (en) 1991-11-14

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