JPH0534836B2 - - Google Patents

Info

Publication number
JPH0534836B2
JPH0534836B2 JP57074014A JP7401482A JPH0534836B2 JP H0534836 B2 JPH0534836 B2 JP H0534836B2 JP 57074014 A JP57074014 A JP 57074014A JP 7401482 A JP7401482 A JP 7401482A JP H0534836 B2 JPH0534836 B2 JP H0534836B2
Authority
JP
Japan
Prior art keywords
thin film
film transistor
liquid crystal
current
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57074014A
Other languages
Japanese (ja)
Other versions
JPS5921064A (en
Inventor
Hiroyuki Ooshima
Toshimoto Kodaira
Toshihiko Mano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP57074014A priority Critical patent/JPS5921064A/en
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to GB8311219A priority patent/GB8311219D0/en
Priority to GB8311878A priority patent/GB2122419B/en
Priority to DE19833315671 priority patent/DE3315671C2/en
Priority to FR8307125A priority patent/FR2530868B1/en
Priority to FR8313382A priority patent/FR2532116B1/en
Publication of JPS5921064A publication Critical patent/JPS5921064A/en
Priority to SG39888A priority patent/SG39888G/en
Priority to HK70189A priority patent/HK70189A/en
Priority to US08/014,053 priority patent/US5365079A/en
Publication of JPH0534836B2 publication Critical patent/JPH0534836B2/ja
Priority to US08/237,521 priority patent/US5474942A/en
Priority to US08/259,354 priority patent/US6037608A/en
Priority to US08/406,419 priority patent/US5650637A/en
Priority to US08/408,979 priority patent/US5552615A/en
Priority to US08/445,030 priority patent/US5573959A/en
Priority to US08/461,933 priority patent/US5677547A/en
Priority to US08/859,494 priority patent/US6316790B1/en
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor
    • G02F2202/104—Materials and properties semiconductor poly-Si
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Description

【発明の詳細な説明】 本発明は光電流を低減させる構造を有する半導
体薄膜トランジスタに関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor thin film transistor having a structure that reduces photocurrent.

近年、絶縁基板上に薄膜トランジスタを形成す
る研究が活発に行なわれている。この技術は、安
価な絶縁基板を用いて薄形デイスプレイを実現す
るアクテイブマトリツクスパネル、あるいは通常
の半導体集積回路上にトランジスタなどの能動素
子を形成する三次元集積回路、あるいは安価で高
性能なイメージセンサ、あるいは高密度のメモリ
など、数多くの応用が期待されるものである。以
下、薄膜トランジスタをアクテイブマトリツクス
パネルに応用した場合を例に取つて説明するが、
本発明は薄膜トランジスタの光電流が問題となる
他の場合にも、全く同様に適用することができ
る。これは、本発明の主旨が、光電流を減少させ
るという薄膜トランジスタの本質的な特性向上に
関するものだからである。 In recent years, research on forming thin film transistors on insulating substrates has been actively conducted. This technology can be used to create active matrix panels that use inexpensive insulating substrates to create thin displays, three-dimensional integrated circuits that form active elements such as transistors on regular semiconductor integrated circuits, and inexpensive, high-performance images. It is expected to have many applications, including sensors and high-density memory. Below, we will explain the case where thin film transistors are applied to active matrix panels as an example.
The present invention can be applied in exactly the same way to other cases where the photocurrent of a thin film transistor is a problem. This is because the gist of the present invention is to reduce photocurrent, which is an essential improvement in the characteristics of thin film transistors.

薄膜トランジスタをアクテイブマトリツクスパ
ネルに応用した場合の液晶表示装置は、一般に、
上側のガラス基板と、下側の薄膜トランジスタ基
板と、その間に封入された液晶とから構成されて
おり、前記薄膜トランジスタ基板上にマトリツク
ス状に配置された液晶駆動素子を外部選択回路に
より選択し、前記液晶駆動素子に接続された液晶
駆動電極に電圧を印加することにより、任意の文
字、図形、あるいは画像の表示を行なうものであ
る。前記薄膜トランジスタ基板の一般的な回路図
を第１図に示す。 Liquid crystal display devices that apply thin film transistors to active matrix panels generally have the following characteristics:
It is composed of an upper glass substrate, a lower thin film transistor substrate, and a liquid crystal sealed between them, and an external selection circuit selects the liquid crystal driving elements arranged in a matrix on the thin film transistor substrate, and selects the liquid crystal driving elements arranged in a matrix on the thin film transistor substrate. By applying a voltage to a liquid crystal drive electrode connected to a drive element, arbitrary characters, figures, or images are displayed. A general circuit diagram of the thin film transistor substrate is shown in FIG.

第１図ａは薄膜トランジスタ基板上の液晶駆動
素子のマトリツクス状配置図である。図中の１で
囲まれた領域が表示領域であり、その中に液晶駆
動素子２がマトリツクス状に配置されている。３
は液晶駆動素子２へのデータ信号ラインであり、
４は液晶駆動素子２へのタイミング信号ラインで
ある。液晶駆動素子２の回路図を第１図ｂに示
す。５は薄膜トランジスタであり、データのスイ
ツチングを行なう。６はコンデンサであり、デー
タ信号の保持用として用いられる。このコンデン
サの容量としては、液晶自体の有する容量と故意
に設けたコンデンサの容量を含むが、場合によつ
ては液晶の容量のみで構成されることもある。７
は液晶パネルであり、７−１は各液晶駆動素子に
対応して形成された液晶駆動電極であり、７−２
は上側ガラスパネルである。 FIG. 1a is a diagram showing a matrix arrangement of liquid crystal driving elements on a thin film transistor substrate. The area surrounded by 1 in the figure is a display area, in which liquid crystal driving elements 2 are arranged in a matrix. 3
is a data signal line to the liquid crystal drive element 2,
4 is a timing signal line to the liquid crystal driving element 2; A circuit diagram of the liquid crystal driving element 2 is shown in FIG. 1b. A thin film transistor 5 performs data switching. 6 is a capacitor, which is used for holding data signals. The capacitance of this capacitor includes the capacitance of the liquid crystal itself and the capacitance of an intentionally provided capacitor, but in some cases, it may be composed only of the capacitance of the liquid crystal. 7
is a liquid crystal panel, 7-1 is a liquid crystal drive electrode formed corresponding to each liquid crystal drive element, and 7-2 is a liquid crystal drive electrode formed corresponding to each liquid crystal drive element.
is the upper glass panel.

第２図は半導体薄膜を用いた従来のＮチヤネル
薄膜トランジスタの一般的な構造を示す断面図で
ある。８はガラス、石英などの絶縁性透明基板、
９は多結晶シリコンなどの半導体薄膜、１０は半
導体薄膜中にリンやヒ素などの不純物をドープし
て形成したソース領域、１１は同じくドレイン領
域、１２はゲート膜、１３はゲート電極、１４は
層間絶縁膜、１５はソース電極、１６はドレイン
電極である。 FIG. 2 is a cross-sectional view showing the general structure of a conventional N-channel thin film transistor using a semiconductor thin film. 8 is an insulating transparent substrate such as glass or quartz;
9 is a semiconductor thin film such as polycrystalline silicon, 10 is a source region formed by doping impurities such as phosphorus or arsenic into the semiconductor thin film, 11 is also a drain region, 12 is a gate film, 13 is a gate electrode, and 14 is an interlayer. An insulating film, 15 is a source electrode, and 16 is a drain electrode.

このような薄膜トランジスタをアクテイブマト
リツクスパネルに応用する場合、薄膜トランジス
タは、液晶に印加する電圧のデータをスイツチン
グするために用いられ、このとき薄膜トランジス
タに要求される特性は大きく次の２種類に分類さ
れる。 When such thin film transistors are applied to active matrix panels, the thin film transistors are used to switch the voltage data applied to the liquid crystal, and the characteristics required of the thin film transistors are broadly classified into the following two types: .

(1) 薄膜トランジスタをON状態にした時コンデ
ンサを充電させるために充分な電流を流すこと
ができこと。(1) When the thin film transistor is turned on, sufficient current can flow to charge the capacitor.

(2) 薄膜トランジスタをOFF状態にした時、極
力、電流が流れないこと。(2) When the thin film transistor is turned off, as little current as possible should flow.

(1)は、コンデンサへのデータの書き込み特性に
関するものである。液晶の表示はコンデンサの電
位により決定されるため、短時間にデータを完壁
に書き込むことができるように、薄膜トランジス
タは充分大きい電流を流すことができなくてはな
らない。この時の電流（以下、ON電流という。）
は、コンデンサの容量と、書き込み時間とから定
まり、そのON電流をクリアできるように薄膜ト
ランジスタを製造しなくてはならない。薄膜トラ
ンジスタの流すことができるON電流は、トラン
ジスタのサイズ（チヤネル長とチヤネル幅）、構
造、製造プロセス、ゲート電圧、ドレイン電圧な
どに大きく依存する。 (1) relates to the characteristics of writing data to the capacitor. Since the liquid crystal display is determined by the potential of the capacitor, the thin film transistor must be able to flow a sufficiently large current so that data can be completely written in a short period of time. Current at this time (hereinafter referred to as ON current)
is determined by the capacitance of the capacitor and the writing time, and thin film transistors must be manufactured to clear the ON current. The ON current that can flow through a thin film transistor greatly depends on the transistor's size (channel length and channel width), structure, manufacturing process, gate voltage, drain voltage, etc.

(2)は、コンデンサに書き込まれたデータの保持
特性に関するものである。一般に、書き込まれた
データは書き込み時間よりもはるかに長い時間保
持されなくてはならない。コンデンサの容量は、
通常1PF程度の小さい値であるため、薄膜トラン
ジスタがOFF状態の時にわずかでもリーク電流
（以下、OFF電流という。）が流れると、ドレイ
ンの電位（すなわち、コンデンサの電位）は急激
にソースの電位に近づき、書き込まれたデータは
正しく保持されなくなつてしまう。したがつて、
OFF電流はできる限り、小さくしなくてはなら
ない。 (2) relates to the retention characteristics of data written to the capacitor. Generally, written data must be retained for a much longer time than the write time. The capacitance of the capacitor is
It is usually a small value of about 1PF, so if even a small amount of leakage current (hereinafter referred to as OFF current) flows when the thin film transistor is in the OFF state, the drain potential (that is, the capacitor potential) will rapidly approach the source potential. , the written data will no longer be retained correctly. Therefore,
The OFF current must be kept as small as possible.

また、薄膜トランジスタに光を照射すると、光
によりキヤリアが励起され、半導体薄膜の伝導度
が増大する。このため、ON電流、OFF電流とも
に増加する。特にOFF電流の増加の割合が著し
い。また光を照射することによる電流の増分（光
電流）は、その光の照度に比例する。したがつ
て、明るい環境にあるほど、OFF電流が増加し、
前記の要求される特性が満たされなくなる。一般
に液晶表示装置は明るい環境にあるほどコントラ
ストが向上し良好な表示特性が得られるが、スイ
ツチング素子にこのような薄膜トランジスタを用
いる場合には、逆に明るいほど表示性能が低下す
ることになる。 Furthermore, when a thin film transistor is irradiated with light, carriers are excited by the light and the conductivity of the semiconductor thin film increases. Therefore, both ON current and OFF current increase. In particular, the rate of increase in OFF current is remarkable. Further, the increase in current (photocurrent) due to irradiation with light is proportional to the illuminance of the light. Therefore, the brighter the environment, the more the OFF current increases.
The above-mentioned required characteristics are no longer satisfied. In general, in a liquid crystal display device, the brighter the environment, the better the contrast and the better display characteristics can be obtained.However, when such thin film transistors are used as switching elements, the brighter the environment, the lower the display performance.

第３図は、第２図に示した構造を有する薄膜ト
ランジスタの特性を示すグラフである。なお、こ
のデータは本出願人が実験を行なつて得られた結
果である。このグラフの横軸はソースに対するゲ
ート電圧VGSであり、縦軸はドレイン電流IDSであ
る。ソースに対するドレイン電圧VDSは4Vであ
る。 FIG. 3 is a graph showing the characteristics of the thin film transistor having the structure shown in FIG. Note that this data is the result obtained through experiments conducted by the applicant. The horizontal axis of this graph is the gate voltage V GS relative to the source, and the vertical axis is the drain current I DS . The drain to source voltage V DS is 4V.

図中、Ａの実線のグラフは光を照射しない時の
ドレイン電流（暗電流）を示し、Ｂの破線のグラ
フは１万ルツクスの光を照射した時のドレイン電
流を示している。第３図からわかるように、光を
照射することによりON電流はほとんど増加しな
いが、OFF電流は大幅に増加している。このた
め、ON／OFF比がとれなくなり、したがつて十
分なトランジスタ特性が得られない。 In the figure, the solid line graph A shows the drain current (dark current) when no light is irradiated, and the broken line graph B shows the drain current when 10,000 lux light is irradiated. As can be seen from Figure 3, the ON current hardly increases due to light irradiation, but the OFF current increases significantly. For this reason, the ON/OFF ratio cannot be maintained, and therefore sufficient transistor characteristics cannot be obtained.

本発明は、このような従来の薄膜トランジスタ
の欠点を除去するものであり、その目的とすると
ころは、光電流を低減させる構造を有する薄膜ト
ランジスタを提供することである。これを実現す
るために本発明では、半導体薄膜を用い、ソース
電極とドレイン電極とゲート電極を備えた薄膜ト
ランジスタにおいて、前記ソース電極あるいは前
記ドレイン電極を延長することにより、前記薄膜
トランジスタのチヤネル領域を被覆したことを特
徴とする薄膜トランジスタを提供する。以下、図
を参照しつつ、本発明を詳しく説明する。 The present invention is intended to eliminate such drawbacks of conventional thin film transistors, and an object thereof is to provide a thin film transistor having a structure that reduces photocurrent. To achieve this, in the present invention, in a thin film transistor using a semiconductor thin film and having a source electrode, a drain electrode, and a gate electrode, the channel region of the thin film transistor is covered by extending the source electrode or the drain electrode. Provided is a thin film transistor characterized by the following. Hereinafter, the present invention will be explained in detail with reference to the drawings.

第４図は本発明による薄膜トランジスタの構造
を示す断面図である。図中８〜１６の意味する内
容は、第２図と全く同様である。第４図からわか
るように、トランジスタのチヤネル領域は延長さ
れたソース電極により被覆されている。したがつ
てチヤネル領域には全く光が入射しない。ただし
ソース電極とドレイン電極の間隙１７からは光が
入射するための、この間隙はできる限り狭いほう
が望ましい。その間隙の幅はパターニング技術の
限界により決定される。しかし、間隙１７から入
射する光は、主にドレイン領域１１におけるキヤ
リア生成に寄与するため、光電流の発生にはほと
んど関与しない。これは、通常、ドレイン領域１
１の不純物濃度が非常に高く、発生したキヤリア
のライフタイム及び移動度が小さいためである。
したがつて第４図に示すような構造を採用するこ
とにより、光電流の発生を充分小さく抑制するこ
とができる。なお、第４図では、ソース電極を延
長することによりチヤネル部を被覆する場合につ
いて示したが、ドレイン電極を延長することによ
りチヤネル部を被覆してもよい。この場合にも、
上述した説明は同様に成立する。 FIG. 4 is a sectional view showing the structure of a thin film transistor according to the present invention. The meanings of 8 to 16 in the figure are exactly the same as in FIG. 2. As can be seen in FIG. 4, the channel region of the transistor is covered by an elongated source electrode. Therefore, no light enters the channel region. However, since light enters through the gap 17 between the source and drain electrodes, it is desirable that this gap be as narrow as possible. The width of the gap is determined by the limitations of patterning technology. However, since the light incident through the gap 17 mainly contributes to carrier generation in the drain region 11, it hardly participates in the generation of photocurrent. This is usually the drain region 1
This is because the impurity concentration of No. 1 is very high, and the lifetime and mobility of the generated carriers are small.
Therefore, by adopting the structure shown in FIG. 4, the generation of photocurrent can be suppressed to a sufficiently low level. Although FIG. 4 shows the case where the channel portion is covered by extending the source electrode, the channel portion may be covered by extending the drain electrode. Also in this case,
The above explanation holds true as well.

また本発明では、ソース領域１０あるいはドレ
イン領域１１のうち一方は、チヤネル領域と同様
に、電極で被覆されるため、光が入射する領域
は、ソース領域あるいはドレイン領域のうちの一
方のみとなる。したがつて、チヤネル領域のみを
遮光材で被覆した場合に比べて、さらに光電流を
減少せしめることが可能となる。しかも、そのよ
うな構造を実現するために、特別な製造工程を必
要としない。すなわち、ソース電極あるいはドレ
イン電極のパターンを変更するだけで、従来の製
造工程を何ら変更する必要はない。 Further, in the present invention, one of the source region 10 and the drain region 11 is covered with an electrode like the channel region, so that only one of the source region and the drain region is the region into which light is incident. Therefore, it is possible to further reduce the photocurrent compared to the case where only the channel region is covered with a light shielding material. Moreover, no special manufacturing process is required to realize such a structure. That is, there is no need to change the conventional manufacturing process, just by changing the pattern of the source electrode or drain electrode.

第５図は、第４図に示した構造を有する薄膜ト
ランジスタの特性を示すグラフである。このデー
タも本出願が実験を行ない得られた結果である。
種々のパラメータは第３図の場合と同様である。
図中、Ｃの実線のグラフは光を照射しない時のド
レイン電流（暗電流）を示し、Ｄの破線のグラフ
は１万ルツクスの光を照射した時のドレイン電流
を示している。Ｃのグラフは、第３図のＡのグラ
フに一致する。第５図からわかるように、光電流
の発生は非常にわずかであり、１万ルツクスの光
を照射してもOFF電流は1PA程度しか増加しな
い。このOFF電流のわずかな増分は、前述した
ように、主にソース電極とドレイン電極の間隙か
ら入射した光の効果によるものである。なお、ド
レイン電極を延長することによりチヤネル部を被
覆する構造の薄膜トランジスタでも、全く同様の
結果が得られる。 FIG. 5 is a graph showing the characteristics of the thin film transistor having the structure shown in FIG. This data is also the result of experiments carried out by the present application.
The various parameters are the same as in FIG.
In the figure, the solid line graph in C shows the drain current (dark current) when no light is irradiated, and the broken line graph in D shows the drain current when 10,000 lux light is irradiated. The graph of C corresponds to the graph of A in FIG. As can be seen from Figure 5, the generation of photocurrent is very small, and even when 10,000 lux of light is irradiated, the OFF current increases by only about 1 PA. As described above, this slight increase in the OFF current is mainly due to the effect of light incident from the gap between the source electrode and the drain electrode. Note that even in a thin film transistor having a structure in which the channel portion is covered by extending the drain electrode, exactly the same result can be obtained.

上述の如く本発明は、薄膜トランジスタの光電
流を大幅に低減できるので、液晶パネルに入射し
た光により薄膜トランジスタの誤動作が生ずるこ
とがなく、良好な表示特性を得ることができる。 As described above, the present invention can significantly reduce the photocurrent of the thin film transistor, so that the thin film transistor does not malfunction due to light incident on the liquid crystal panel, and good display characteristics can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図ａ，ｂは薄膜トランジスタをアクテイブ
マトリツクスパネルに応用した場合の一般的な回
路図である。第２図は半導体薄膜を用いたＮチヤ
ネル薄膜トランジスタの一般的な構造を示す断面
図である。第３図は従来の薄膜トランジスタの特
性を示すグラフである。第４図は、本発明による
薄膜トランジスタの構造を示す断面図である。第
５図は、本発明による薄膜トランジスタの特性を
示すグラフである。 Figures 1a and 1b are general circuit diagrams when thin film transistors are applied to active matrix panels. FIG. 2 is a cross-sectional view showing the general structure of an N-channel thin film transistor using a semiconductor thin film. FIG. 3 is a graph showing the characteristics of a conventional thin film transistor. FIG. 4 is a sectional view showing the structure of a thin film transistor according to the present invention. FIG. 5 is a graph showing the characteristics of the thin film transistor according to the present invention.

Claims (1)

【特許請求の範囲】 １ 一対の透明基板内に液晶が封入され、該基板
の一方の基板上に設けられた画素電極と、該画素
電極に接続され、該基板上に設けられてなる薄膜
トランジスタと、該薄膜トランジスタのソース領
域に接続されてなるソース電極とを有してなる液
晶表示装置において、 該薄膜トランジスタは、該基板上に形成された
非単結晶シリコン薄膜からなるチヤネル領域と、
該ソース領域及びドレイン領域と、該チヤネル上
にゲート絶縁膜を介して形成された光透過性のゲ
ート電極と、該ソース領域に接続され、層間絶縁
膜により該ゲート電極と絶縁された光非透過性の
ソース電極とからなり、該ソース電極が該チヤネ
ル領域上を覆つていることを特徴とする液晶表示
装置。[Claims] 1 A pair of transparent substrates in which a liquid crystal is sealed, a pixel electrode provided on one of the substrates, and a thin film transistor connected to the pixel electrode and provided on the substrate. , a liquid crystal display device comprising a source electrode connected to a source region of the thin film transistor, the thin film transistor comprising: a channel region made of a non-single crystal silicon thin film formed on the substrate;
The source region and the drain region, a light-transmitting gate electrode formed on the channel via a gate insulating film, and a light-impermeable gate electrode connected to the source region and insulated from the gate electrode by an interlayer insulating film. 1. A liquid crystal display device comprising a liquid crystal source electrode, the source electrode covering the channel region.
JP57074014A 1982-04-30 1982-04-30 Thin film transistor Granted JPS5921064A (en)

Priority Applications (16)

Application Number Priority Date Filing Date Title
JP57074014A JPS5921064A (en) 1982-04-30 1982-04-30 Thin film transistor
GB8311219A GB8311219D0 (en) 1982-04-30 1983-04-25 Thin film transistor
GB8311878A GB2122419B (en) 1982-04-30 1983-04-29 A thin film transistor and an active matrix liquid crystal display device
DE19833315671 DE3315671C2 (en) 1982-04-30 1983-04-29 Thin film transistor
FR8307125A FR2530868B1 (en) 1982-04-30 1983-04-29 THIN FILM TRANSISTOR AND LIQUID CRYSTAL DISPLAY DEVICE USING THE SAME
FR8313382A FR2532116B1 (en) 1982-04-30 1983-08-17 THIN FILM TRANSISTOR AND LIQUID CRYSTAL DISPLAY DEVICE USING THE SAME
SG39888A SG39888G (en) 1982-04-30 1988-06-20 An active matrix liquid crystal display device
HK70189A HK70189A (en) 1982-04-30 1989-08-31 An active matrix liquid crystal display device
US08/014,053 US5365079A (en) 1982-04-30 1993-02-05 Thin film transistor and display device including same
US08/237,521 US5474942A (en) 1982-04-30 1994-05-03 Method of forming a liquid crystal display device
US08/259,354 US6037608A (en) 1982-04-30 1994-05-03 Liquid crystal display device with crossover insulation
US08/406,419 US5650637A (en) 1982-04-30 1995-03-20 Active matrix assembly
US08/408,979 US5552615A (en) 1982-04-30 1995-03-23 Active matrix assembly with double layer metallization over drain contact region
US08/445,030 US5573959A (en) 1982-04-30 1995-05-19 Method of forming a liquid crystal device
US08/461,933 US5677547A (en) 1982-04-30 1995-06-05 Thin film transistor and display device including same
US08/859,494 US6316790B1 (en) 1982-04-30 1997-05-20 Active matrix assembly with light blocking layer over channel region

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57074014A JPS5921064A (en) 1982-04-30 1982-04-30 Thin film transistor

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP8673694A Division JP2564995B2 (en) 1994-04-25 1994-04-25 Liquid crystal display

Publications (2)

Publication Number Publication Date
JPS5921064A JPS5921064A (en) 1984-02-02
JPH0534836B2 true JPH0534836B2 (en) 1993-05-25

Family

ID=13534814

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57074014A Granted JPS5921064A (en) 1982-04-30 1982-04-30 Thin film transistor

Country Status (3)

Country Link
JP (1) JPS5921064A (en)
DE (1) DE3315671C2 (en)
GB (1) GB8311219D0 (en)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6179256A (en) * 1984-09-26 1986-04-22 Seiko Instr & Electronics Ltd Thin-film transistor
JPH0374849A (en) * 1989-08-16 1991-03-29 Matsushita Electron Corp Semiconductor device
JPH0456282A (en) * 1990-06-25 1992-02-24 Matsushita Electron Corp Thin film transistor and liquid crystal display provided therewith
JP3092761B2 (en) * 1991-12-02 2000-09-25 キヤノン株式会社 Image display device and method of manufacturing the same
US5317433A (en) * 1991-12-02 1994-05-31 Canon Kabushiki Kaisha Image display device with a transistor on one side of insulating layer and liquid crystal on the other side
JP2869238B2 (en) * 1992-02-07 1999-03-10 シャープ株式会社 Active matrix type liquid crystal display
JP2738315B2 (en) * 1994-11-22 1998-04-08 日本電気株式会社 Thin film transistor and method of manufacturing the same
FR2734404B1 (en) * 1995-05-16 1997-06-27 Thomson Lcd METHOD FOR MANUFACTURING TFT DIRECT STAGES WITH GRID-SOURCE OR DRAIN INTERCONNECTION
JPH09311342A (en) 1996-05-16 1997-12-02 Semiconductor Energy Lab Co Ltd Display device
US7053973B1 (en) 1996-05-16 2006-05-30 Semiconductor Energy Laboratory Co., Ltd. Display device
JP3126661B2 (en) 1996-06-25 2001-01-22 株式会社半導体エネルギー研究所 Liquid crystal display
US6576926B1 (en) * 1999-02-23 2003-06-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and fabrication method thereof
US9035389B2 (en) * 2012-10-22 2015-05-19 Taiwan Semiconductor Manufacturing Company, Ltd. Layout schemes for cascade MOS transistors
JP6466614B2 (en) * 2018-06-04 2019-02-06 株式会社半導体エネルギー研究所 Liquid crystal display

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5492022A (en) * 1977-12-29 1979-07-20 Matsushita Electric Ind Co Ltd Picture display device
JPS5562479A (en) * 1978-11-06 1980-05-10 Suwa Seikosha Kk Liquid crystal display panel
JPS5691276A (en) * 1979-12-25 1981-07-24 Citizen Watch Co Ltd Display panel
JPS56107287A (en) * 1980-01-31 1981-08-26 Tokyo Shibaura Electric Co Image display unit
JPS56150871A (en) * 1980-04-24 1981-11-21 Toshiba Corp Semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5492022A (en) * 1977-12-29 1979-07-20 Matsushita Electric Ind Co Ltd Picture display device
JPS5562479A (en) * 1978-11-06 1980-05-10 Suwa Seikosha Kk Liquid crystal display panel
JPS5691276A (en) * 1979-12-25 1981-07-24 Citizen Watch Co Ltd Display panel
JPS56107287A (en) * 1980-01-31 1981-08-26 Tokyo Shibaura Electric Co Image display unit
JPS56150871A (en) * 1980-04-24 1981-11-21 Toshiba Corp Semiconductor device

Also Published As

Publication number Publication date
DE3315671C2 (en) 1986-04-10
GB8311219D0 (en) 1983-06-02
JPS5921064A (en) 1984-02-02
DE3315671A1 (en) 1983-11-03

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