CN208903642U - Phase inverter and GOA circuit - Google Patents
Phase inverter and GOA circuit Download PDFInfo
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- CN208903642U CN208903642U CN201821605866.5U CN201821605866U CN208903642U CN 208903642 U CN208903642 U CN 208903642U CN 201821605866 U CN201821605866 U CN 201821605866U CN 208903642 U CN208903642 U CN 208903642U
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Abstract
A kind of phase inverter, comprising: first film transistor, comprising: first substrate；An at least first buffer layer is formed on the first substrate；And first polysilicon layer, a part being formed in an at least first buffer layer；And second thin film transistor (TFT), comprising: the second substrate；An at least second buffer layer is formed on second light shield layer；And second polysilicon layer, a part being formed in an at least second buffer layer.The first film transistor further comprises that the first light shield layer is formed between the first substrate and an at least first buffer layer and/or second thin film transistor (TFT) further comprises that the second light shield layer is formed between the second substrate and an at least second buffer layer.A kind of GOA circuit is also provided.
Description
Technical field
This announcement is related to display device, more particularly to a kind of phase inverter for display device and GOA circuit.
Background technique
Array gate driving (Gate driver On Array, GOA) circuit will be controlled using the processing procedure of display panel
Thin film transistor (TFT) (Thin Film Transistor, TFT) establishment of component of scan line is on the viewing area periphery of display panel.
GOA circuit include phase inverter, (inverter, INV), transmission gate (transfer gate, TG), NAND gate (NAND gate),
The elementary logic circuits such as nor gate (NOR gate).
Referring to Fig. 1, Fig. 1 shows the schematic diagram for exporting scanning signal to scan line G using phase inverter in the prior art.
The phase inverter includes P-type TFT P and N-type TFT N.The grid of the P-type TFT P
The grid of pole and the N-type TFT N are electrically connected to input endpoint IN.The source electrode of the P-type TFT P is electrical
It is connected to DC voltage source VGH (high level).The source electrode of the N-type TFT N is electrically connected to DC voltage source VGL
(low level).The drain electrode of the P-type TFT P and the drain electrode of the N-type TFT N are electrically connected to the scanning
Line G.
When a high level signal is input to the input endpoint IN, the P-type TFT P is not turned on, the N-type
Thin film transistor (TFT) N conducting, the scan line G are low level (being electrically connected to DC voltage source VGL).
When a low level signal is input to the input endpoint IN, the P-type TFT P is connected, and the N-type is thin
Film transistor N is not turned on, and the scan line G is high level (being electrically connected to DC voltage source VGH).
When the electrical characteristic variation of the P-type TFT P, lead to critical voltage (threshold voltage) Vth
It is deviated toward positive, therefore the Vgs of P-type TFT P can tend to critical voltage Vth, the electric conduction of P-type TFT P
Stream increases.There can be guiding path between DC voltage source VGH (high level) and DC voltage source VGL (low level), finally lead
Scan line G is caused to level off to 0 volt, so that the thin film transistor (TFT) being electrically connected with picture element is slowly connected, leakage current increases, and leads
Panel is caused crosstalk phenomenon occur.
Therefore it needs to propose a solution to the problems of the prior art.
Utility model content
When the electrical characteristic variation of P-type TFT, critical voltage is caused to deviate toward positive number, so that electrically connecting with picture element
The thin film transistor (TFT) connect is slowly connected, and leakage current increases, and panel is caused crosstalk phenomenon occur.
This announcement is designed to provide a kind of phase inverter and GOA circuit, can solve the problems of the prior art.
To solve the above problems, a kind of phase inverter that this announcement provides, is used for GOA circuit, the phase inverter includes: first
Thin film transistor (TFT), comprising: first substrate；An at least first buffer layer is formed on the first substrate；First polysilicon layer,
The a part being formed in an at least first buffer layer；First grid insulating layer is formed at least one first buffering
On layer and on first polysilicon layer；And first grid, it is formed on the first grid insulating layer；And second is thin
Film transistor, comprising: the second substrate；An at least second buffer layer is formed in the second substrate；Second polysilicon layer, shape
A part in an at least second buffer layer described in Cheng Yu；Second grid insulating layer is formed in an at least second buffer layer
On upper and described second polysilicon layer；And second grid, it is formed on the second grid insulating layer.The first film
Transistor further comprises that the first light shield layer is formed between the first substrate and an at least first buffer layer, and/or
Second thin film transistor (TFT) further comprises that the second light shield layer is formed in the second substrate and at least one second buffering
Between layer.
In an embodiment, the first grid is electrically connected to an input endpoint, and the second grid is electrically connected
To the input endpoint.
In an embodiment, the first film transistor further comprises one first source electrode and one first drain electrode, institute
It states the first source electrode and is electrically connected to one first DC voltage source, first drain electrode is electrically connected to an exit point, and described the
Two thin film transistor (TFT)s further comprise one second source electrode and one second drain electrode, and it is straight that second source electrode is electrically connected to one second
Galvanic electricity potential source, second drain electrode are electrically connected to the exit point.
In an embodiment, the first film transistor is P-type TFT.
In an embodiment, second thin film transistor (TFT) is N-type TFT.
A kind of GOA circuit that this announcement provides includes multiple phase inverters, and each phase inverter includes: first film transistor,
It include: first substrate；First light shield layer is formed on the first substrate；An at least first buffer layer is formed in described first
On light shield layer；First polysilicon layer, a part being formed in the first buffer layer；First grid insulating layer is formed in institute
It states in an at least first buffer layer and on first polysilicon layer；And first grid, it is exhausted to be formed in the first grid
In edge layer；And second thin film transistor (TFT), comprising: the second substrate；Second light shield layer is formed in the second substrate；At least
One second buffer layer is formed on second light shield layer；Second polysilicon layer, one be formed in the second buffer layer
Point；Second grid insulating layer is formed in an at least second buffer layer and on second polysilicon layer；And second
Grid is formed on the second grid insulating layer.The first film transistor further comprises that the first light shield layer is formed in
On the first substrate and/or second thin film transistor (TFT) further comprises that the second light shield layer is formed in the second substrate
On.
In an embodiment, the first grid is electrically connected to an input endpoint, and the second grid is electrically connected
To the input endpoint.
In an embodiment, the first film transistor further comprises one first source electrode and one first drain electrode, institute
It states the first source electrode and is electrically connected to one first DC voltage source, first drain electrode is electrically connected to an exit point, and described the
Two thin film transistor (TFT)s further comprise one second source electrode and one second drain electrode, and it is straight that second source electrode is electrically connected to one second
Galvanic electricity potential source, second drain electrode are electrically connected to the exit point.
In an embodiment, the first film transistor is P-type TFT.
In an embodiment, second thin film transistor (TFT) is N-type TFT.
Compared to the prior art, in the phase inverter of the GOA circuit of this announcement, due in P-type TFT and N-type film
At least one setting light shield layer of transistor, the light shield layer can be reduced the leakage current, and then avoid the display panel
Crosstalk phenomenon.
For the above content of this announcement can be clearer and more comprehensible, preferred embodiment is cited below particularly, and cooperate institute's accompanying drawings, makees
Detailed description are as follows:
Detailed description of the invention
Fig. 1 shows the schematic diagram for exporting scanning signal to scan line using phase inverter in the prior art.
Fig. 2 shows the top view of the phase inverter of the GOA circuit according to one embodiment of this announcement.
Fig. 3 shows Fig. 2 along the sectional view of line segment AA '.
Fig. 4 shows Fig. 2 along the sectional view of line segment BB '.
Specific embodiment
The explanation of following embodiment is to can be used to the particular implementation of implementation to illustrate this announcement with reference to additional schema
Example.
Please see Fig. 2 to Fig. 4, Fig. 2 shows the top view of the phase inverter of the GOA circuit according to one embodiment of this announcement, Fig. 3
Fig. 2 is shown along the sectional view of line segment AA ', Fig. 4 shows Fig. 2 along the sectional view of line segment BB '.
The GOA circuit includes multiple phase inverters and is set on a display panel.More particularly, the GOA circuit
It is set to the viewing area periphery of the display panel.
Each phase inverter includes a first film transistor T1 and one second thin film transistor (TFT) T2.
The first film transistor T1 includes a first substrate 10, one first light shield layer 12, at least a first buffer layer
(two first buffer layers 14,16 are shown in figure), one first polysilicon layer (polysilicon layer) 18, one first grid are exhausted
Edge layer 20, a first grid G1, one first source S 1 and one first drain D 1.
The first substrate 10 is the array substrate of the display panel.The first substrate 10 can be, but not limited to as glass
Glass substrate or flexible base plate.
First light shield layer 12 is formed on the first substrate 10.
The first buffer layer 14 is formed on the first light shield layer 12 of institute.The first buffer layer 14 can be silicon oxide layer
Or silicon nitride layer.
The first buffer layer 16 is formed in the first buffer layer 14.The first buffer layer 16 can be silica
Layer or silicon nitride layer.
First polysilicon layer 18 is formed in a part in the first buffer layer 16.
The first grid insulating layer 20 is formed in the first buffer layer 16 and on first polysilicon layer 18.
The first grid G1 is formed on the first grid insulating layer 20 and is electrically connected to an input endpoint IN.
The position that first source S 1 and first drain D 1 are formed is same as the prior art, does not add to go to live in the household of one's in-laws on getting married in this
It states.
First source S 1 is electrically connected to one first DC voltage source V1.First drain D 1 is electrically connected to one
Exit point OUT.The exit point OUT is electrically connected to the scan line of the panel.
The second thin film transistor (TFT) T2 includes a second substrate 30, one second light shield layer 32, at least a second buffer layer
(two second buffer layers 34,36 are shown in figure), one second polysilicon layer 38, a second grid insulating layer 40, a second grid G2,
One second source S 2 and one second drain D 2.
The second substrate 30 is the array substrate of the display panel.The second substrate 30 can be, but not limited to as glass
Glass substrate or flexible base plate.The second substrate 30 and the first substrate 10 are all the array substrate of the display panel.
Second light shield layer 32 is formed in the second substrate 30.
The second buffer layer 34 is formed on the second light shield layer 32 of institute.The second buffer layer 34 can be silicon oxide layer
Or silicon nitride layer.
The second buffer layer 36 is formed in the second buffer layer 34.The second buffer layer 36 can be silica
Layer or silicon nitride layer.
Second polysilicon layer 38 is formed in a part in the second buffer layer 36.
The second grid insulating layer 40 is formed in the second buffer layer 36 and on second polysilicon layer 38.
The second grid G2 is formed on the second grid insulating layer 40 and is electrically connected to the input endpoint IN.
The position that second source S 2 and second drain D 2 are formed is same as the prior art, does not add to go to live in the household of one's in-laws on getting married in this
It states.
Second source S 2 is electrically connected to one second DC voltage source V2.Second drain D 2 is electrically connected to institute
State exit point OUT.
From Fig. 3 and Fig. 4 it is found that the first film transistor T1 and the second thin film transistor (TFT) T2 has similar knot
Structure.
The characteristics of phase inverter of the GOA circuit of this announcement, is that the first film transistor T1 and second film are brilliant
At least one of body pipe T2 is provided with light shield layer.In this present embodiment, the first film transistor T1 is provided with the first shading
Layer 12, the second thin film transistor (TFT) T2 is provided with the second light shield layer 32.It, can be only thin described first in another embodiment
Film transistor T1 is provided with the first light shield layer 12, and the second thin film transistor (TFT) T2 is not provided with the second light shield layer 32.In another reality
It applies in example, the second thin film transistor (TFT) T2 only can be provided with the second light shield layer 32, the first film transistor T1 is not
First light shield layer 12 is set.
In addition, in this present embodiment, it is brilliant that the first film transistor T1 forms a p-type film doped with triad
Body pipe.More particularly, the region of the source S 1 of the first film transistor T1 and the region doping of drain D 1 have trivalent first
Element.Triad is such as, but not limited to boron.
The second thin film transistor (TFT) T2 forms a N-type TFT doped with pentad.More particularly, institute
The region doping in the region and drain D 2 of stating the source S 2 of the second thin film transistor (TFT) T2 has pentad.Pentad is for example but not
It is limited to for phosphorus.
The characteristics of phase inverter of the GOA circuit of this announcement, is that first light shield layer 12 or second light shield layer is arranged
32.First light shield layer 12 is for sheltering from the first film transistor T1 (P-type TFT).When described first thin
The critical voltage of film transistor (P-type TFT) T1 is deviated toward positive, since first light shield layer 12 blocks residence
State first film transistor (P-type TFT) T1, the electric conduction of first film transistor (P-type TFT) T1
Stream is smaller, and first film transistor (P-type TFT) T1 is not turned on.
Therefore, when a high level signal is input to the first grid of the first film transistor (P-type TFT) T1
When the G1 of pole, first film transistor (P-type TFT) T1 will not be connected because critical voltage is deviated toward positive,
The scanning signal for being input to scan line still can be the DC voltage source VGL (low level) of Fig. 1.That is, working as the phase inverter
Input when being high level signal, the output of the phase inverter is low level signal.The phase inverter can normally realize that function is (defeated
Low level signal out).More particularly, first light shield layer 12 can be reduced the first film transistor T1 (p-type film crystalline substance
Body pipe) leakage current, and then avoid the crosstalk phenomenon of the display panel.
In addition, second light shield layer 32 also can be reduced the leakage of the second thin film transistor (TFT) T2 (N-type TFT)
Electric current, and then avoid the crosstalk phenomenon of the display panel.
In the phase inverter of the GOA circuit of this announcement, due at least the one of P-type TFT and N-type TFT
Light shield layer is arranged in person, and the light shield layer can be reduced the leakage current, and then avoid the crosstalk phenomenon of the display panel.
Although above preferred embodiment is not to limit in conclusion this announcement is disclosed above with preferred embodiment
This announcement is made, those skilled in the art can make various changes and profit in the spirit and scope for not departing from this announcement
Decorations, therefore the protection scope of this announcement subjects to the scope of the claims.
Claims (10)
1. a kind of phase inverter, it to be used for GOA circuit, which is characterized in that the phase inverter includes:
First film transistor, comprising:
First substrate；
An at least first buffer layer is formed on the first substrate；
First polysilicon layer, a part being formed in an at least first buffer layer；
First grid insulating layer is formed in an at least first buffer layer and on first polysilicon layer；And
First grid is formed on the first grid insulating layer；And
Second thin film transistor (TFT), comprising:
The second substrate；
An at least second buffer layer is formed in the second substrate；
Second polysilicon layer, a part being formed in an at least second buffer layer；
Second grid insulating layer is formed in an at least second buffer layer and on second polysilicon layer；And
Second grid is formed on the second grid insulating layer,
Wherein the first film transistor further comprises that the first light shield layer is formed in the first substrate and described at least one
Between first buffer layer, and/or
Second thin film transistor (TFT) further comprises that the second light shield layer is formed in the second substrate and described at least one second
Between buffer layer.
2. phase inverter according to claim 1, which is characterized in that the first grid is electrically connected to an input endpoint,
And the second grid is electrically connected to the input endpoint.
3. phase inverter according to claim 1, which is characterized in that the first film transistor further comprises one first
Source electrode and one first drain electrode, first source electrode are electrically connected to one first DC voltage source, and first drain electrode electrically connects
It is connected to an exit point,
Second thin film transistor (TFT) further comprises that one second source electrode and one second drain electrode, second source electrode are electrically connected
To one second DC voltage source, second drain electrode is electrically connected to the exit point.
4. phase inverter according to claim 1, which is characterized in that the first film transistor is P-type TFT.
5. phase inverter according to claim 1, which is characterized in that second thin film transistor (TFT) is N-type TFT.
6. a kind of GOA circuit, which is characterized in that including multiple phase inverters, each phase inverter includes:
First film transistor, comprising:
First substrate；
An at least first buffer layer is formed on the first substrate；
First polysilicon layer, a part being formed in an at least first buffer layer；
First grid insulating layer is formed in an at least first buffer layer and on first polysilicon layer；And
First grid is formed on the first grid insulating layer；And
Second thin film transistor (TFT), comprising:
The second substrate；
An at least second buffer layer is formed in the second substrate；
Second polysilicon layer, a part being formed in an at least second buffer layer；
Second grid insulating layer is formed in an at least second buffer layer and on second polysilicon layer；And
Second grid is formed on the second grid insulating layer,
Wherein the first film transistor further comprises that the first light shield layer is formed in the first substrate and described at least one
Between first buffer layer, and/or
Second thin film transistor (TFT) further comprises that the second light shield layer is formed in the second substrate and described at least one second
Between buffer layer.
7. GOA circuit according to claim 6, which is characterized in that the first grid is electrically connected to an input endpoint,
And the second grid is electrically connected to the input endpoint.
8. GOA circuit according to claim 6, which is characterized in that the first film transistor further comprises one
One source electrode and one first drain electrode, first source electrode are electrically connected to one first DC voltage source, and first drain electrode is electrically
It is connected to an exit point,
Second thin film transistor (TFT) further comprises that one second source electrode and one second drain electrode, second source electrode are electrically connected
To one second DC voltage source, second drain electrode is electrically connected to the exit point.
9. GOA circuit according to claim 6, which is characterized in that the first film transistor is p-type film crystal
Pipe.
10. GOA circuit according to claim 6, which is characterized in that second thin film transistor (TFT) is N-type film crystal
Pipe.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821605866.5U CN208903642U (en) | 2018-09-29 | 2018-09-29 | Phase inverter and GOA circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821605866.5U CN208903642U (en) | 2018-09-29 | 2018-09-29 | Phase inverter and GOA circuit |
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| Publication Number | Publication Date |
|---|---|
| CN208903642U true CN208903642U (en) | 2019-05-24 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201821605866.5U Active CN208903642U (en) | 2018-09-29 | 2018-09-29 | Phase inverter and GOA circuit |
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| Country | Link |
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| CN (1) | CN208903642U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109243353A (en) * | 2018-09-29 | 2019-01-18 | 武汉华星光电技术有限公司 | Phase inverter and GOA circuit |
-
2018
- 2018-09-29 CN CN201821605866.5U patent/CN208903642U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109243353A (en) * | 2018-09-29 | 2019-01-18 | 武汉华星光电技术有限公司 | Phase inverter and GOA circuit |
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