JPH0247865B2 - HAKUMAKUTORANJISUTANOSEIZOHOHO - Google Patents
HAKUMAKUTORANJISUTANOSEIZOHOHOInfo
- Publication number
- JPH0247865B2 JPH0247865B2 JP12726681A JP12726681A JPH0247865B2 JP H0247865 B2 JPH0247865 B2 JP H0247865B2 JP 12726681 A JP12726681 A JP 12726681A JP 12726681 A JP12726681 A JP 12726681A JP H0247865 B2 JPH0247865 B2 JP H0247865B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- transistor
- capacitor
- gate
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010409 thin film Substances 0.000 claims description 48
- 229910052710 silicon Inorganic materials 0.000 claims description 22
- 239000010703 silicon Substances 0.000 claims description 22
- 239000010408 film Substances 0.000 claims description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 18
- 238000009792 diffusion process Methods 0.000 claims description 8
- 238000000059 patterning Methods 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 150000003376 silicon Chemical class 0.000 claims description 2
- 239000003990 capacitor Substances 0.000 description 23
- 239000004065 semiconductor Substances 0.000 description 16
- 239000011159 matrix material Substances 0.000 description 10
- 239000012535 impurity Substances 0.000 description 9
- 239000004973 liquid crystal related substance Substances 0.000 description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 210000001520 comb Anatomy 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
Description
【発明の詳細な説明】
本発明はMIS（金属−絶縁物−半導体）トラン
ジスタアレイを用いたデイスプレイのためのアク
テイブ・マトリツクス基板に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an active matrix substrate for displays using MIS (metal-insulator-semiconductor) transistor arrays.
従来アクテイブ・マトリツクスを用いたデイス
プレイパネルはダイナミツク方式に比しそのマト
リツクスサイズを非常に大きくでき、大型かつド
ツト数の大きなパネルを実現可能な方式として注
目を浴びている。特に液晶のような受光型素子で
はダイナミツク方式での駆動デユーテイは限界が
あり、テレビ表示等にはアクテイブ・マトリツク
スの応用が考えられている。第１図は従来のアク
テイブ・マトリツクスの１セルを示している。ア
ドレス線Ｘがトランジスタ２のゲートに入力され
ており、トランジスタをONさせてデータ線Ｙの
信号を保持用コンデンサ３に電荷として蓄積させ
る。再びデータを書き込むまで、このコンデンサ
３により保持され、同時に液晶４を駆動する。こ
こでVCは共通電極信号である。液晶のリークは
非常に少ないので、短時間の電荷の保持には十分
である。ここのトランジスタとコンデンサ１の製
造は通常のICのプロセスと全く同じである。第
２図は第１図のセルをシリコンゲートプロセスに
より作成した例である。単結晶シリコンウエハ上
にトランジスタ１０とコンデンサ１１が構成され
る。アドレス線Ｘとコンデンサの上電極１１は多
結晶シリコン（ポリシリコン）で、又データ線Ｙ
と液晶駆動電極１３はAlでできており、コンタ
クトホール７，８，９により、基板とAl、ポリ
シリコンとAlが夫々接続される。 Conventional display panels using active matrices can have a much larger matrix size than the dynamic method, and are attracting attention as a method that can realize large panels with a large number of dots. Particularly in the case of light-receiving elements such as liquid crystals, there is a limit to the driving duty of the dynamic method, and the application of active matrices to television displays and the like is being considered. FIG. 1 shows one cell of a conventional active matrix. The address line X is input to the gate of the transistor 2, and the transistor is turned on to cause the signal on the data line Y to be stored as a charge in the holding capacitor 3. This capacitor 3 holds the data until data is written again, and at the same time drives the liquid crystal 4. Here VC is the common electrode signal. Since liquid crystal leakage is very low, it is sufficient to hold charge for a short period of time. The manufacturing of the transistor and capacitor 1 here is exactly the same as the normal IC process. FIG. 2 is an example in which the cell shown in FIG. 1 is produced by a silicon gate process. A transistor 10 and a capacitor 11 are constructed on a single crystal silicon wafer. The address line X and the upper electrode 11 of the capacitor are made of polycrystalline silicon (polysilicon), and the data line Y
The liquid crystal drive electrode 13 is made of Al, and the substrate and Al, and the polysilicon and Al are connected through contact holes 7, 8, and 9, respectively.
この種の通常のICプロセスに従つたマトリツ
クス基板は次の大きな欠点をもつ。 Matrix substrates that follow this type of conventional IC process have the following major drawbacks.
１つはマトリツクス基板の製造プロセスがIC
と同一のため、プロセスが複雑であり工程コスト
が高いと同時に基板シリコンとの接合リークによ
る歩留低下が発生し、総コストが高い。特にシリ
コン基板とソース・ドレインとなる拡散層との接
合部には、単結晶中の結晶欠陥にかなり左右され
通常のセルではこのリーク電流を100PA以下にし
なければならず、この構造では数万個のセル全て
のリークを押えることはむずかしい。ここで発生
する接合リークはコンデンサ３に蓄積された電荷
を放電し、コントラストを低下させる。 One is that the manufacturing process of the matrix substrate is IC.
The process is complicated and the process cost is high, and at the same time, the yield decreases due to junction leakage with the substrate silicon, resulting in a high total cost. In particular, the leakage current at the junction between the silicon substrate and the diffusion layer that becomes the source/drain is considerably affected by crystal defects in the single crystal, and in a normal cell, this leakage current must be kept below 100 PA. It is difficult to suppress leaks in all cells. The junction leak generated here discharges the charge accumulated in the capacitor 3 and reduces the contrast.
２つにはAl電極のすきまからシリコン基板に
入射した光は、電子−正孔対を生成し拡散して光
電流を生じてコンデンサ３の電荷を放電してしま
いコントラストが低下する。 Second, the light incident on the silicon substrate through the gap between the Al electrodes generates electron-hole pairs and is diffused to generate a photocurrent and discharge the charge in the capacitor 3, resulting in a decrease in contrast.
本発明の目的はこの欠点を改善する方式を提供
するものであり、本発明の構成はガラス、石英、
上に半導体薄膜をチヤネルとする薄膜トランジス
タを構成するものであつて以下具体例にそつて説
明する。 The purpose of the present invention is to provide a method for improving this drawback, and the structure of the present invention is based on glass, quartz,
This constitutes a thin film transistor having a semiconductor thin film as a channel, and will be explained below with reference to a specific example.
第３図は本発明に用いマトリツクスセルを示す
ものであり、第１図の従来とは、容量18のGND
配線を新たに設けること、又は液晶の容量が十分
大きいと、それを電荷保持容量として用いるので
電荷保持用の容量18とGND配線を省略すること
ができ、この場合でも基本的なデータの書込、保
持は同じである。この場合のGND電位は一定の
バイアス電圧を意味しバイアスレベル、又は信号
レベルは問わない。又表示データの入力をデータ
線Ｙがサンプル−ホールドする容量として、デー
タ線ＹとGNDラインの間の容量21、又はアドレ
ス線Ｘとの間の容量22を利用する。 Figure 3 shows the matrix cell used in the present invention, and the conventional one shown in Figure 1 is a GND cell with a capacity of 18.
If a new wiring is provided, or if the capacitance of the liquid crystal is large enough, it will be used as a charge storage capacitor, so the charge storage capacitor 18 and the GND wiring can be omitted, and even in this case, basic data writing is not possible. , the retention is the same. The GND potential in this case means a constant bias voltage, and the bias level or signal level does not matter. Further, the capacitance 21 between the data line Y and the GND line or the capacitance 22 between the address line X and the data line Y is used as a capacitance for the data line Y to sample and hold input display data.
第４図に本発明に用いる液晶駆動のための１セ
ル４０の図面を示す。ゲート線４７とGND線４
２は同一の導電性薄膜、データ線４５、トランジ
スタ部のチヤネル４６は半導体薄膜よりなる。又
コンデンサ４９を形成するために透明駆動電極４
４をつける前に誘電体膜を全面につける。コンタ
クト・ホール４３はこの誘電体膜を開孔して電極
４４とトランジスタとのコンタクトをとる。この
時シリコン薄膜のソース・ドレイン、配線等の低
抵抗層形成のための不純物注入は工程簡略のため
導電性薄膜（例えば金属、結果として不純物注入
されるシリコン膜等の材料を用いる）をマスクと
して行なう。第６図イ〜ハは、本発明の製造方法
の一実施例を示す。同図イにおいて、透明基板６
０上に不透明な導電性薄膜を形成後パターニング
し、ゲート電極６１を形成する。さらに、このゲ
ート電極６１上に酸化膜等の絶縁膜６２を形成す
る。次に、同図ロにおいて、この絶縁膜６２上に
シリコン薄膜６３を形成し、このシリコン薄膜６
３上ネガレジスト６４を塗布する。さらに、透明
基板６０の裏側より全面露光６５を行い現像す
る。こうして、ゲート電極６１の真上にはゲート
電極の形状のネガレジストが残留する。さらに、
同図ハに示す如くゲートセルフアラインの方式で
トランジスタのソース、ドレインの拡散領域６６
を形成する。しかしこのままだと第４図の半導体
薄膜と導電性薄膜の交点４７，４８もトランジス
タ４６と同様にトランジスタが形成されてしま
い、データ線４５は交点４７と４８で切れてしま
う。本発明はこのゲートセルフアライン方式によ
る工程簡略化による欠点を、次のようにして補な
う。半導体薄膜にクロスする導電性薄膜の幅（ト
ランジスタ４６ではW1 交点４７ではW2 交点
４８でW3）をトランジスタ部は交点部より長く
とることによる。即ち第６図ロにおいて不純物は
ゲート電極６６をマスクにドープされる際、必ず
横方向にもＸだけ入る。例えば多結晶シリコンで
は1000℃、1HでリンＰは5μmも侵入する。従つ
て、交叉部は導電性薄膜の幅を６〜8μm、トラン
ジスタ部は20μmに設定すると、ゲートセルフア
ラインを行つてもトランジスタはソースとドレイ
ンが分離され、又交叉部は拡散の横拡がりによ
り、トランジスタで言えばソースとドレインがシ
ヨートされ、配線が切れない。 FIG. 4 shows a diagram of one cell 40 for driving a liquid crystal used in the present invention. Gate line 47 and GND line 4
The same conductive thin film 2, the data line 45, and the channel 46 of the transistor section are made of a semiconductor thin film. Also, in order to form a capacitor 49, a transparent drive electrode 4
Before applying 4, apply a dielectric film to the entire surface. A contact hole 43 is formed in this dielectric film to establish contact between the electrode 44 and the transistor. At this time, impurity implantation for forming low-resistance layers such as sources, drains, and wiring in silicon thin films is performed using a conductive thin film (for example, a metal, a material such as a silicon film into which impurities are implanted as a result) as a mask to simplify the process. Let's do it. FIGS. 6A to 6C show an embodiment of the manufacturing method of the present invention. In the figure A, the transparent substrate 6
After forming an opaque conductive thin film on 0, it is patterned to form a gate electrode 61. Furthermore, an insulating film 62 such as an oxide film is formed on this gate electrode 61. Next, in FIG. 7B, a silicon thin film 63 is formed on this insulating film 62.
3. Apply negative resist 64 on top. Further, the entire surface of the transparent substrate 60 is exposed to light 65 from the back side and developed. In this way, a negative resist in the shape of the gate electrode remains directly above the gate electrode 61. moreover,
As shown in FIG.
form. However, if this continues, transistors will be formed at the intersections 47 and 48 of the semiconductor thin film and the conductive thin film in FIG. The present invention compensates for the drawbacks due to process simplification by the gate self-alignment method as follows. This is because the width of the conductive thin film that crosses the semiconductor thin film (in the transistor 46, W 1 at the intersection 47, W 2 at the intersection 48 and W 3 ) is set longer in the transistor section than in the intersection. That is, in FIG. 6B, when the impurity is doped using the gate electrode 66 as a mask, it always enters in the lateral direction by an amount of X. For example, in polycrystalline silicon, phosphorus P penetrates as much as 5 μm in 1 hour at 1000°C. Therefore, if the width of the conductive thin film at the intersection is set to 6 to 8 μm and the width of the transistor is set to 20 μm, the source and drain of the transistor will be separated even if gate self-alignment is performed, and the width of the conductive thin film at the intersection will be separated due to the lateral spread of diffusion. In the case of a transistor, the source and drain are shot, and the wiring cannot be cut.
第５図は第４図における本発明の断面を示して
いる。Ａ−Ｂはトランジスタ断面、Ｃ−Ｄ，C′−
D′は交叉部の断面である。透明基板５０上に半
導体薄膜部５１，５２，５３，５４を形成後、ゲ
ート絶縁膜５５を形成し更に導電性薄膜によりゲ
ート電極５６、配線５６を形成後、これらの導電
性薄膜をマスクに半導体薄膜へ不純物ドープを行
なう。この後誘電体膜５７をつけてコンタクトホ
ールを開孔後透明駆動電極５８を形成する。この
結果、トランジスタはチヤネル５３が形成され、
又配線部は拡散部分５４がシヨートして本来の配
線機能をなす。 FIG. 5 shows a cross-section of the invention in FIG. A-B is the transistor cross section, CD, C'-
D' is the cross section of the intersection. After forming the semiconductor thin film parts 51, 52, 53, and 54 on the transparent substrate 50, forming the gate insulating film 55 and further forming the gate electrode 56 and the wiring 56 using the conductive thin film, the semiconductor is formed using these conductive thin films as a mask. Dope impurities into the thin film. Thereafter, a dielectric film 57 is attached, contact holes are opened, and transparent drive electrodes 58 are formed. As a result, a channel 53 is formed in the transistor.
Further, the wiring portion performs the original wiring function by being shot by the diffusion portion 54.
第７図はこれを更に保持用コンデンサ部に応用
した例である。セル７０はゲート線７１、データ
線７２、コンタクト・ホール７３、GNDライン
７４、交点７５，７６、コンデンサ７７、トラン
ジスタ７８、液晶駆動電極７９からできている。
この場合のコンデンサは半導体薄膜と導電性薄膜
の間のゲート絶縁膜を誘電体膜として形成され
る。しかし通常の如く大きなベタの電極でコンデ
ンサを形成すると、ゲートセルフアラインにより
不純物が半導体膜にドープされずに、コンデンサ
に直列に非常に高い抵抗が入つたと同じになり、
電荷保持の役割をしない。従つてこれを逃れるた
めにコンデンサの電極となる導電性薄膜を、トラ
ンジスタのチヤネル長（W1）より短かい幅の櫛
状にする。この結果櫛目と櫛目の間から不純物が
横方向に拡散し、下部で各々が短絡することによ
り、コンデンサの半導体膜の抵抗を下げることが
できる。 FIG. 7 shows an example in which this is further applied to a holding capacitor section. The cell 70 is made up of a gate line 71, a data line 72, a contact hole 73, a GND line 74, intersections 75 and 76, a capacitor 77, a transistor 78, and a liquid crystal drive electrode 79.
In this case, the capacitor is formed using a dielectric film as the gate insulating film between the semiconductor thin film and the conductive thin film. However, if a capacitor is formed using a large solid electrode as usual, impurities will not be doped into the semiconductor film due to gate self-alignment, and the result will be the same as if a very high resistance were inserted in series with the capacitor.
Does not play the role of charge retention. Therefore, in order to avoid this, the conductive thin film that becomes the electrode of the capacitor is made into a comb shape with a width shorter than the channel length (W 1 ) of the transistor. As a result, impurities diffuse laterally from between the combs, shorting each other at the bottom, thereby lowering the resistance of the semiconductor film of the capacitor.
第８図は第７図EFでの断面を示す。基板８０
上にシリコン薄膜を形成し、パターニングの後に
ゲート酸化膜８５及びコンデンサの誘電体膜８６
を形成後、ゲート電極及びコンデンサの電極とな
る導電性薄膜（金属膜やシリコン薄膜）をつけて
ゲート電極８７、コンデンサ電極８８を形成す
る。この後に導電性薄膜をマスクに半導体薄膜に
不純物をドープする。この時トランジスタ部は導
電性薄膜即ちゲート電極の幅が広いのでソース・
ドレイン８２，８３と不純物の入らないチヤネル
８１が形成されて、トランジスタとなる。一方コ
ンデンサは導電性薄膜８８の幅がトランジスタ部
より狭いので、不純物が横方向に拡散して短絡
し、この結果、低抵抗の半導体電極８４が形成さ
れる。この後に絶縁膜８９をつけて、コンタクト
部９１を開孔し、この後駆動電極９０を形成す
る。 FIG. 8 shows a cross section at FIG. 7 EF. Board 80
A silicon thin film is formed on top, and after patterning, a gate oxide film 85 and a capacitor dielectric film 86 are formed.
After forming, a conductive thin film (metal film or silicon thin film) that will become a gate electrode and a capacitor electrode is applied to form a gate electrode 87 and a capacitor electrode 88. Thereafter, impurities are doped into the semiconductor thin film using the conductive thin film as a mask. At this time, the transistor part has a conductive thin film, that is, a wide gate electrode, so the source and
Drains 82 and 83 and a channel 81 free from impurities are formed to form a transistor. On the other hand, since the width of the conductive thin film 88 of the capacitor is narrower than that of the transistor section, impurities are diffused laterally and short-circuited, resulting in the formation of a low-resistance semiconductor electrode 84. After this, an insulating film 89 is applied, a contact portion 91 is opened, and then a drive electrode 90 is formed.
本発明は前述のように、半導体薄膜と、半導体
金属等の導電性薄膜よりなるアクテイブ・マトリ
ツクス基板において、半導体薄膜と導電性薄膜の
交叉部分における導電性薄膜の幅を、トランジス
タ部より狭くすることにより、工程の簡略化を可
能にするものである。特にこの場合拡散の横拡が
りＸに対し、トランジスタでは2X以上、交叉部
コンデンサ部では2X以下にする。 As described above, in an active matrix substrate consisting of a semiconductor thin film and a conductive thin film such as a semiconductor metal, the width of the conductive thin film at the intersection of the semiconductor thin film and the conductive thin film is made narrower than the transistor portion. This makes it possible to simplify the process. Particularly in this case, with respect to the lateral spread of diffusion
本発明は透明基板上に半導体薄膜による薄膜ト
ランジスタを有するアクテイブマトリツクスを提
供するものであり、従来に比し次の利点がある。 The present invention provides an active matrix having thin film transistors made of semiconductor thin films on a transparent substrate, and has the following advantages over the conventional ones.
製造プロセスが簡単で、従来のパルクシリコン
タイプでは６回のフオトエツチング工程を必要と
したが、本発明の方式では３回でよく、工程コス
トが安いと共に、バルクシリコンの如くにＰ−Ｎ
接合断面積が非常に少なく従つて接合リークがわ
ずかであり歩留の向上が望める。 The manufacturing process is simple; the conventional bulk silicon type requires 6 photo etching steps, but the method of the present invention requires only 3 photo etching steps, resulting in low process costs and P-N photoetching similar to bulk silicon.
The cross-sectional area of the joint is very small, so there is little joint leakage, and an improvement in yield can be expected.
又、上方から入射した光は90％以上通過し、又シ
リコン薄膜中のキヤリアの拡散長も短かいので、
光電流は殆んど発生せず、光に対するリーク筐は
１万ルツクスの下でも10PA以下となり、光の入
射による表示像の消滅は防ぐことができた。In addition, more than 90% of the light incident from above passes through, and the carrier diffusion length in the silicon thin film is short.
Almost no photocurrent was generated, and the leakage of light from the casing was less than 10 PA even under 10,000 lux, making it possible to prevent the display image from disappearing due to the incidence of light.
更に透明基板に透明液晶駆動を用いると、最も
コントラストの高いFEタイプの液晶を用いるこ
とができ、画面の明るさも向上し、表示品質を飛
躍的に改善できる。 Furthermore, by using a transparent liquid crystal drive on a transparent substrate, it is possible to use an FE type liquid crystal with the highest contrast, improving screen brightness and dramatically improving display quality.
同時に基板にガラスやそれに準ずる材料を用い
るとパネルの組立が容易となり従来のパルクシリ
コンタイプに対し、組立て歩留りが向上し、又工
程が簡単になる。 At the same time, using glass or a similar material for the substrate makes it easier to assemble the panel, which improves the assembly yield and simplifies the process compared to the conventional bulk silicon type.
上述の如く本発明は、透明基板上に不透明導電
性薄膜を沈着しパターニングによりゲート電極を
形成し、該ゲート電極上に絶縁膜を被覆する工
程、該絶縁膜上にシリコン薄膜を沈着しパターニ
ング後、このシリコン薄膜上にネガレジストを塗
布する工程、該透明基板の裏側より全面露光し、
ゲート電極上に該ネガレジストを残留する工程、
ゲートセルフアラインにより該シリコン薄膜中に
ソース、ドレイン拡散領域を形成する工程とより
なるようにしたから、ゲート電極をマスクとした
パターングによつて理想的なゲートセルフアライ
ンが実現でき、ソースドレイン拡散を確実に実現
できる。 As described above, the present invention includes the steps of depositing an opaque conductive thin film on a transparent substrate and patterning it to form a gate electrode, coating the gate electrode with an insulating film, and depositing a silicon thin film on the insulating film and patterning it. , a process of applying a negative resist on this silicon thin film, exposing the entire surface from the back side of the transparent substrate,
a step of leaving the negative resist on the gate electrode;
Since the gate self-alignment process consists of forming source and drain diffusion regions in the silicon thin film, ideal gate self-alignment can be achieved by patterning using the gate electrode as a mask, and the source and drain diffusion regions can be formed in the silicon thin film. It can definitely be achieved.
第１図は従来のアクテイブマトリツクスに用い
たセルの回路図で第２図はバルクシリコンを用い
たセルの平面図、第３図は本発明のセル図であ
る。第４図は本発明によるアクテイブ・マトリツ
クスの平面図、第５図はその断面図、第６図イ，
ロ，ハは本発明に用いるトランジスタの形成方法
を示す。第７図は本発明の他の実施例の平面図、
第８図はその断面図を各々示す。
１１……コンデンサ３の上部電極、１０……ポ
リシリコンゲート、７，８，９……コンタクトホ
ール、１３……Alの駆動電極、１５……薄膜ト
ランジスタ、４１，７１……ゲート線、４５，７
２……データ線、４６，７８……トランジスタ、
４９，７７……コンデンサ、４３……コンタクト
ホール、４４，５８，７９，９０……駆動電極、
５５，８５……ゲート絶縁膜、５３，６７，８１
……トランジスタのチヤネル。
FIG. 1 is a circuit diagram of a cell used in a conventional active matrix, FIG. 2 is a plan view of a cell using bulk silicon, and FIG. 3 is a cell diagram of the present invention. 4 is a plan view of the active matrix according to the present invention, FIG. 5 is a sectional view thereof, and FIG.
B and C show a method for forming a transistor used in the present invention. FIG. 7 is a plan view of another embodiment of the present invention;
FIG. 8 shows their cross-sectional views. 11... Upper electrode of capacitor 3, 10... Polysilicon gate, 7, 8, 9... Contact hole, 13... Al drive electrode, 15... Thin film transistor, 41, 71... Gate line, 45, 7
2...Data line, 46, 78...Transistor,
49, 77... Capacitor, 43... Contact hole, 44, 58, 79, 90... Drive electrode,
55, 85...gate insulating film, 53, 67, 81
...transistor channel.
Claims (1)
ーニングによりゲート電極を形成し、該ゲート電
極上に絶縁膜を被覆する工程、該絶縁膜上にシリ
コン薄膜を沈着しパターニング後、このシリコン
薄膜上にネガレジストを塗布する工程、該透明基
板の裏側より全面露光し、ゲート電極上に該ネガ
レジストを残留する工程、ゲートセルフアライン
により該シリコン薄膜中にソース、ドレイン拡散
領域を形成する工程とよりなることを特徴とする
薄膜トランジスタの製造方法。1 Step of depositing an opaque conductive thin film on a transparent substrate and forming a gate electrode by patterning, and covering the gate electrode with an insulating film, depositing a silicon thin film on the insulating film and patterning, and then depositing a silicon thin film on this silicon thin film. It consists of a step of applying a negative resist, a step of exposing the entire surface of the transparent substrate to light from the back side and leaving the negative resist on the gate electrode, and a step of forming source and drain diffusion regions in the silicon thin film by gate self-alignment. A method for manufacturing a thin film transistor characterized by the following.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12726681A JPH0247865B2 (en) | 1981-08-13 | 1981-08-13 | HAKUMAKUTORANJISUTANOSEIZOHOHO |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12726681A JPH0247865B2 (en) | 1981-08-13 | 1981-08-13 | HAKUMAKUTORANJISUTANOSEIZOHOHO |
Related Child Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21342891A Division JPH0722201B2 (en) | 1991-08-26 | 1991-08-26 | Liquid crystal display manufacturing method |
| JP21342791A Division JPH0828521B2 (en) | 1991-08-26 | 1991-08-26 | Liquid crystal display |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5828867A JPS5828867A (en) | 1983-02-19 |
| JPH0247865B2 true JPH0247865B2 (en) | 1990-10-23 |
Family
ID=14955761
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12726681A Expired - Lifetime JPH0247865B2 (en) | 1981-08-13 | 1981-08-13 | HAKUMAKUTORANJISUTANOSEIZOHOHO |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0247865B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04319859A (en) * | 1991-04-18 | 1992-11-10 | Canon Inc | Facsimile equipment provided with automatic calling function |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2525263Y2 (en) * | 1989-06-28 | 1997-02-05 | 三恵工業株式会社 | Stamped muffler |
| JPH0722201B2 (en) * | 1991-08-26 | 1995-03-08 | セイコーエプソン株式会社 | Liquid crystal display manufacturing method |
| JP2996854B2 (en) * | 1994-01-27 | 2000-01-11 | 株式会社 半導体エネルギー研究所 | Method for manufacturing insulated gate field effect semiconductor device |
| JP2648788B2 (en) * | 1994-06-10 | 1997-09-03 | 株式会社 半導体エネルギー研究所 | Insulated gate field effect semiconductor device |
| JP2789168B2 (en) * | 1994-06-10 | 1998-08-20 | 株式会社 半導体エネルギー研究所 | Method for manufacturing insulated gate field effect semiconductor device for liquid crystal display panel |
| US10502321B2 (en) * | 2014-01-14 | 2019-12-10 | Compart Systems Pte, Ltd. | Gasket retainer for surface mount fluid component |
-
1981
- 1981-08-13 JP JP12726681A patent/JPH0247865B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04319859A (en) * | 1991-04-18 | 1992-11-10 | Canon Inc | Facsimile equipment provided with automatic calling function |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5828867A (en) | 1983-02-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5474942A (en) | Method of forming a liquid crystal display device | |
| US5650637A (en) | Active matrix assembly | |
| EP0610969B1 (en) | Active matrix panel | |
| US4103297A (en) | Light-insensitive matrix addressed liquid crystal display system | |
| JP2967126B2 (en) | Semiconductor integrated circuit device for flat light valve substrate | |
| JPS59501562A (en) | Method for manufacturing a display screen using thin film transistors and capacitors | |
| GB2081018A (en) | Active Matrix Assembly for Display Device | |
| JPH0133833B2 (en) | ||
| US5337172A (en) | Liquid crystal matrix control employing doped semiconductor pixel electrode surrounded by undoped channel region | |
| JPH0534836B2 (en) | ||
| JPH0247865B2 (en) | HAKUMAKUTORANJISUTANOSEIZOHOHO | |
| US6100951A (en) | Thin-film switching elements for electronic devices and a method of manufacturing the same | |
| JP2668317B2 (en) | Active matrix panel | |
| JPH09127556A (en) | Display device and its drive method | |
| JPH0330308B2 (en) | ||
| JPH0132661B2 (en) | ||
| JP3305814B2 (en) | Thin film transistor and liquid crystal display device using the same | |
| JPH0669235A (en) | Manufacture of thin-film transistor | |
| JPH0828521B2 (en) | Liquid crystal display | |
| JP2568990B2 (en) | Liquid crystal display device and method of manufacturing the same | |
| JPS6053082A (en) | Thin-film transistor | |
| JP2564995B2 (en) | Liquid crystal display | |
| GB2122419A (en) | A thin film transistor and an active matrix liquid crystal display device | |
| JPS5945486A (en) | Display panel | |
| JPS5914662A (en) | Manufacture of semiconductor device |