JPH0828521B2 - Liquid crystal display - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device for a display using a MIS (metal-insulator-semiconductor) transistor array.

[0002]

2. Description of the Related Art Conventionally, a display panel using an active matrix has attracted attention as a method capable of realizing a large-sized panel having a large number of dots because its matrix size can be made very large as compared with the dynamic method. In particular, a light-receiving element such as a liquid crystal has a limited drive duty in a dynamic system, and application of an active matrix is considered for a television display and the like. FIG.
Shows one cell of a conventional active matrix. The address line X is input to the gate of the transistor 2, and the transistor is turned on to accumulate the signal on the data line Y in the holding capacitor 3 as electric charge. It is held by this capacitor 3 until data is written again,
At the same time, the liquid crystal 4 is driven. Here, VC is a common electrode signal. Since the leakage of the liquid crystal is very small, it is enough to hold the charge for a short time. The manufacturing of the transistor and the capacitor 1 here is exactly the same as the process of an ordinary IC.
FIG. 2 shows an example in which the cell of FIG. 1 is manufactured by a silicon gate process. A transistor 10 and a capacitor 11 are formed on a single crystal silicon wafer. The address line X and the upper electrode 11 of the capacitor are made of polycrystalline silicon (polysilicon), and the data line Y and the liquid crystal drive electrode 13 are made of Al.
1, polysilicon and Al are connected to each other.

[0003]

The matrix substrate according to the conventional IC process of this kind has the following major drawbacks.

First, since the manufacturing process of the matrix substrate is the same as that of the IC, the process is complicated and the process cost is high, and at the same time, the yield is reduced due to the junction leak with the substrate silicon, and the total cost is high. In particular, at the junction between the silicon substrate and the diffusion layer serving as the source / drain, the leak current must be 100 PA or less in a normal cell, which is considerably affected by crystal defects in the single crystal. It is difficult to suppress the leak of all the cells. Here, the generated junction leak discharges the electric charge accumulated in the capacitor 3 and reduces the contrast.

Secondly, the light incident on the silicon substrate through the gap of the Al electrode generates electron-hole pairs and diffuses to generate a photocurrent to discharge the electric charge of the capacitor 3 to lower the contrast.

[0006]

The object of the present invention is to provide a method for remedying this drawback, in which a liquid crystal is enclosed between a pair of substrates and one of the substrates is arranged in a matrix. A thin film transistor having arrayed pixel electrodes, a source / drain region made of a silicon thin film and connected to the pixel electrode, a data line for supplying a data signal to the source region of the thin film transistor, and a gate electrode of the transistor. In a liquid crystal display device having a gate line for supplying a gate signal, wherein the source region and the drain region are formed by introducing impurities using the gate electrode as a mask, the source line is the thin film transistor of the thin film transistor. It is formed of the same material as the source region at the same time, and the diffusion of impurities in the source region and the drain region is laterally spread. The line width of the gate line of intersection of the gate line and the source line with respect to X is less than 2X, the width of the gate electrode of the transistor is a liquid crystal display device, characterized in that at least 2X.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The constitution of the present invention constitutes a thin film transistor using a silicon thin film as a channel on a glass, quartz or silicon wafer, which will be described below with reference to specific examples. FIG. 3 shows a matrix cell used in the present invention, which is different from the conventional one shown in FIG. 1 in that a GND wiring of a capacitor 18 is newly provided, or if the capacitance of liquid crystal is sufficiently large, it is used as a charge storage capacitor. Therefore, the capacitance for holding charge 18
The GND wiring can be omitted, and even in this case, the basic writing and holding of data is the same. In this case, the GND potential means a constant bias voltage, regardless of the bias level or the signal level. In addition, as a capacitance for the data line Y to sample and hold the input of display data, the capacitance 21 between the data line Y and the GND line or the address line X
The capacity 22 between and is used.

FIG. 4 shows a circuit for driving a liquid crystal used in the present invention.
A drawing of a cell 40 is shown. The gate line 47 and the GND line 42 are made of the same conductive thin film, and the data line 45 and the channel 46 of the transistor section are made of a semiconductor thin film. Also, a dielectric film is applied to the entire surface before the transparent drive electrode 44 is applied to form the capacitor 49. The contact hole 43 opens this dielectric film to make contact between the electrode 44 and the transistor. At this time, the impurity injection for forming the low resistance layer such as the source / drain of the silicon thin film and the wiring is performed by using the conductive thin film (for example, a metal, and a material such as the silicon film to which the impurity is injected as a result is used) as a mask for simplifying the process. Diffusion regions of the source and drain of the transistor are formed by the gate self-alignment method. However, as it is, the intersections 47 and 48 of the semiconductor thin film and the conductive thin film of FIG.
Transistors are formed in the same way as the above, and the data line 4
5 breaks at intersections 47 and 48.

Further, FIGS. 6A to 6C show a manufacturing method of another embodiment using the self-alignment technique of the present invention in an inverted thin film transistor having a lower gate electrode and an upper channel portion. In FIG. 9A, an opaque conductive thin film is formed on the transparent substrate 60 and then patterned to form a gate electrode 61. Further, an insulating film 62 such as an oxide film is formed on the gate electrode 61. Next, in FIG. 9B, a silicon thin film 63 is formed on the insulating film 62, and a positive resist 64 is applied on the silicon thin film 63. Further, the entire surface is exposed from the back side of the transparent substrate 60, and development is performed. Thus, the positive resist in the shape of the gate electrode remains directly above the gate electrode 61. Further, source / drain diffusion regions 66 of the transistor are formed by the gate self-alignment method shown in FIG.

The present invention compensates for the drawbacks due to the process simplification by the gate self-alignment method as follows. That is, to explain with reference to FIG. 4, the width of the conductive thin film crossing the semiconductor thin film (W1 in the transistor 46,
This is because the transistor portion takes W2 at the intersection 47 and W3 at the intersection 48) longer than the intersection. Further, when described in detail using the embodiment of FIG. 6, when the impurity is doped with the gate electrode 66 as a mask in FIG. The width is 2X or more, and the width of the conductive thin film at the intersection of the semiconductor thin film and the conductive thin film is 2X or less. For example, in polycrystalline silicon, phosphorus P penetrates as much as 5 μm at 1000 ° C. for 1H. Therefore, if the width of the conductive thin film at the intersection is set to 6 to 8 μm and the width of the transistor portion is set to 20 μm, the source and drain of the transistor are separated even if gate self-alignment is performed.
In addition, due to the spread of diffusion at the intersection, the source and drain of the transistor are short-circuited, and the wiring is not cut.

FIG. 5 shows a cross section of the invention in FIG. AB is a transistor cross section, CD, C'-D '
Is a cross section of the intersection. After forming the semiconductor thin film portions 51, 52, 53, 54 on the transparent substrate 50, a gate insulating film 55 is formed, and a gate electrode 56 and a wiring 56 are formed by a conductive thin film.
After forming, the semiconductor thin film is doped with impurities using these conductive thin films as a mask. After that, a dielectric film 57 is attached and a contact hole is opened, and then a transparent drive electrode 58 is formed.
As a result, the channel 52 is formed in the transistor, and the diffusion portion 54 of the wiring portion is short-circuited to perform the original wiring function.

FIG. 7 shows an example in which this is further applied to a holding capacitor section. The cell 70 has a gate line 71 and a data line 7
2. Contact holes 73, GND lines 74, intersections 75 and 76, capacitors 77, transistors 78, and liquid crystal drive electrodes 79. The capacitor in this case is formed by using the gate insulating film between the semiconductor thin film and the conductive thin film as a dielectric film. However, when a capacitor is formed with a large solid electrode as usual, impurities are not doped into the semiconductor film due to gate self-alignment, and it becomes the same as when a very high resistance is inserted in series with the capacitor, and it does not play a role of charge retention. . Therefore, in order to escape from this, the conductive thin film serving as the electrode of the capacitor is formed into a comb shape having a width shorter than the channel length (W1) of the transistor. As a result, the impurities are laterally diffused from between the comb lines and short-circuited at the lower parts, so that the resistance of the semiconductor film of the capacitor can be reduced.

FIG. 8 shows the determination in FIG. 7EF. Board 80
After forming a silicon thin film on the gate oxide film 85 and a capacitor dielectric film 86 after patterning, a conductive thin film (metal film silicon thin film) to be a gate electrode and a capacitor electrode is attached to the gate electrode 87, The capacitor electrode 88 is formed. Thereafter, the semiconductor thin film is doped with impurities using the conductive thin film as a mask. At this time, since the conductive thin film, that is, the width of the gate electrode, is wide in the transistor portion, the source / drain 82, 83 and the channel 81 free of impurities are formed to form a transistor. On the other hand, in the capacitor, since the width of the conductive thin film 88 is narrower than that of the transistor portion, impurities are laterally diffused and short-circuited, and as a result, the semiconductor electrode 84 having a low resistance is formed. After that, an insulating film 89 is attached, a contact portion 91 is opened, and then a drive electrode 90 is formed.

As described above, according to the present invention, in the active matrix substrate composed of the semiconductor thin film and the conductive thin film such as a semiconductor metal, the width of the conductive thin film at the intersection of the semiconductor thin film and the conductive thin film is set to be smaller than that of the transistor part. By narrowing the width, the process can be simplified.
In this case, in particular, the lateral spread X of the diffusion is set to 2X or more for the transistor and 2X or less for the crossing capacitor portion.

[0015]

The present invention provides an active matrix having a thin film transistor made of a semiconductor thin film on a transparent substrate, and has the following advantages over conventional ones.

The manufacturing process is simple, and the conventional bulk silicon type requires 6 times of photo-etching steps, but the method of the present invention requires only 3 times, the process cost is low, and P-type like bulk silicon. Since the N-junction cross-sectional area is very small, the junction leak is slight, and the yield can be improved. In addition, light incident from above passes 90% or more, and since the diffusion length of carriers in the silicon thin film is short, almost no photocurrent is generated, and the leak current for light is 10 PA or less even under 10,000 lux. , It was possible to prevent the display image from disappearing due to the incidence of light.

Further, when a transparent liquid crystal drive is used for the transparent substrate,
Since the FE type liquid crystal having the highest contrast can be used, the brightness of the screen can be improved and the display quality can be dramatically improved.

At the same time, if glass or a similar material is used for the substrate, the panel can be easily assembled, the assembly yield is improved and the process is simplified as compared with the conventional bulk silicon type.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a cell used in a conventional active matrix.

FIG. 2 is a plan view of a cell using bulk silicon.

FIG. 3 is a cell diagram of the present invention.

FIG. 4 is a plan view of an active matrix according to the present invention.

FIG. 5 is a cross-sectional view of an active matrix according to the present invention.

6A, 6B, 6C, 6D, 6E, 6F, 6G, and 6H are diagrams showing a method of forming a thin film transistor of another embodiment of the present invention.

FIG. 7 is a plan view of an embodiment to which the present invention is applied.

FIG. 8 is a sectional view of an embodiment to which the present invention is applied.

[Explanation of symbols]

11 ... Top electrode of capacitor 3 ... Polysilicon gate 7, 8, 9 Contact hole 13 Al drive electrode 15・ ・ ・ ・ ・ ・ ・ ・ Thin film transistor 41, 71 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Gate line 45, 72 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Data Lines 46, 78 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Transistors 49, 77 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Capacitors 43 ・ ・ ・ ・ ・・ ・ ・ ・ ・ ・ ・ ・ Contact holes 44, 58, 79, 90 ・ ・ ・ ・ Drive electrodes 55, 85 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Gate insulating film 53 , 67, 81 .......... channel of the transistor

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 27/12 A

Claims (1)

[Claims] 1. A liquid crystal is enclosed between a pair of substrates, the substrate comprising:
Pixels arranged in a matrix on one substrate
Equipped with electrodes and source / drain regions consisting of silicon thin film
And a thin film transistor connected to the pixel electrode,
Supplying a data signal to the source region of the thin film transistor
Data line, gate to the gate electrode of the transistor
A gate line for supplying a signal, and the source region and
The drain region is doped with impurities by using the gate electrode as a mask.
A liquid crystal display device formed by introducing
The source line is the same as the source region of the thin film transistor.
And the source region and the drain region.
For the lateral spread X of the diffusion of impurities in the rain region
The line width of the gate line at the intersection of the gate line and the source line is
2X or less, the width of the gate electrode of the transistor is
A liquid crystal display device having a size of 2X or more.