JPH05150260A - Active matrix substrate - Google Patents

Active matrix substrate

Info

Publication number
JPH05150260A
JPH05150260A JP31275191A JP31275191A JPH05150260A JP H05150260 A JPH05150260 A JP H05150260A JP 31275191 A JP31275191 A JP 31275191A JP 31275191 A JP31275191 A JP 31275191A JP H05150260 A JPH05150260 A JP H05150260A
Authority
JP
Japan
Prior art keywords
electrode
thin film
liquid crystal
active matrix
additional capacitance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP31275191A
Other languages
Japanese (ja)
Inventor
Yuji Kawachi
裕二 河内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP31275191A priority Critical patent/JPH05150260A/en
Publication of JPH05150260A publication Critical patent/JPH05150260A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To reduce leakage current from a picture element additional capacity part as one of the causes of defective inhomogeneous contrast between picture element units of an active matrix liq. crystal panel. CONSTITUTION:This active matrix substrate has a picture element electrode for driving a liq. crystal and an active switching element for driving the liq. crystal. Additional capacity is formed between a thin silicon film 2 electrically connected to the picture element electrode and an electric conductive thin film electrode 4 disposed on the film 2 with a gate SiO2 film 3 in-between. This capacity is independent of the capacity of the liq. crystal between the picture element electrode and a counter electrode. The silicon film 1 under the electrode 4 is doped with impurity atoms.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は液晶ディスプレイに用い
られるアクティブマトリックス基板の画素の付加容量の
構造に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a pixel additional capacitance of an active matrix substrate used in a liquid crystal display.

【0002】[0002]

【従来の技術】従来の液晶ディスプレイに用いられた薄
膜能動素子を有するアクティブマトリックス基板におい
ては、画素電極と独立に付加容量を設ける場合、能動素
子である薄膜トランジスタの形成と同時に付加容量を形
成していた。特にスタガード型トランジスタでは、図
3、4に示す様にガラス基板16上にシリコン薄膜1
2、13をCVD法で形成し、フォトエッチ後、酸化又
はCVD法又はスパッタ法でSiO2 膜を形成する。こ
の後ゲート電極19、15を形成し、該ゲート電極を用
いたセルフアライン法でソース、ドレイン部12にイオ
ン注入した構造であった。この時同時に付加容量を形成
する。付加容量の下電極18は、トランジスタの導電層
シリコン20、13を用いて形成する。間の絶縁膜はト
ランジスタの絶縁膜形成と同時にSiO2 を用いる。上
側電極19はゲート電極20形成時に同時に行なう。そ
の後トランジスタのソース、ドレイン部形成のイオン打
込みと同様に、付加容量下電極18部に不純物原子のド
ーズを行なっていた。上記のプロセスを用いた付加容量
の構造は図3に示すが、ゲート電極の下位置にある下電
極の薄膜シリコン層は不純物原子がドーズされず、イン
トリンシックな状態にある。そこで上電極19に電圧を
印加した下電極表面層に反転層を誘起させ、下電極のド
ーズされた部分18と電気的な導通をとる。該状態で付
加容量としての機能を働かせ、トランジスタのリーク電
流や液晶を介したリーク電流が流れることによって生じ
る画素電極に保持された電荷のリークを補充し、画素電
位の降下を押さえる効果を出している。また図4の18
は付加容量下電極の不純物原子がドーズされた部分を示
すがイオン打込み後の活性化熱処理によってゲート電極
下へ数μm入り込んだ状態になっている。付加容量上電
極19へ印加する電圧がしきい値に達するまでは上記上
電極19の下に拡散した部分のみが容量として機能する
ことになる。又上電極19への印加電圧がしきい値より
も大きな場合は、該上電極19のパターン面積分の容量
が機能する。つまり付加容量は上電極19への電圧依存
性をもつことになる。画素電極電位は液晶駆動電位に応
じ変化するわけで、付加容量への印加電圧は該液晶駆動
電位に応じ変化することになる。
2. Description of the Related Art In an active matrix substrate having a thin film active element used in a conventional liquid crystal display, when an additional capacitor is provided independently of a pixel electrode, the additional capacitor is formed at the same time when a thin film transistor which is an active element is formed. It was Particularly in the staggered transistor, as shown in FIGS. 3 and 4, the silicon thin film 1 is formed on the glass substrate 16.
2 and 13 are formed by the CVD method, and after photoetching, a SiO 2 film is formed by the oxidation, the CVD method, or the sputtering method. After that, the gate electrodes 19 and 15 were formed, and the source / drain portion 12 was ion-implanted by the self-alignment method using the gate electrodes. At this time, the additional capacitance is formed at the same time. The lower electrode 18 of the additional capacitor is formed by using the conductive layer silicon 20, 13 of the transistor. As the insulating film between them, SiO 2 is used at the same time when the insulating film of the transistor is formed. The upper electrode 19 is formed simultaneously with the formation of the gate electrode 20. After that, similar to the ion implantation for forming the source and drain portions of the transistor, a dose of impurity atoms was performed to the lower portion 18 of the additional capacitance lower electrode. The structure of the additional capacitor using the above process is shown in FIG. 3, but the thin film silicon layer of the lower electrode below the gate electrode is in an intrinsic state in which impurity atoms are not dosed. Therefore, an inversion layer is induced in the lower electrode surface layer to which a voltage is applied to the upper electrode 19 to establish electrical conduction with the dosed portion 18 of the lower electrode. In this state, the function as an additional capacitor is activated to supplement the leak of the electric charge held in the pixel electrode caused by the leak current of the transistor or the leak current through the liquid crystal, and suppress the drop of the pixel potential. There is. 18 of FIG.
Shows the portion where the impurity atoms of the lower electrode of the additional capacitance are dosed, but it is in a state of entering several μm below the gate electrode by the activation heat treatment after ion implantation. Until the voltage applied to the additional capacitor upper electrode 19 reaches the threshold value, only the portion diffused under the upper electrode 19 functions as a capacitor. When the voltage applied to the upper electrode 19 is larger than the threshold value, the capacity corresponding to the pattern area of the upper electrode 19 functions. That is, the additional capacitance has a voltage dependency on the upper electrode 19. Since the pixel electrode potential changes according to the liquid crystal drive potential, the voltage applied to the additional capacitance changes according to the liquid crystal drive potential.

【0003】[0003]

【発明が解決しようとする課題】しかし前述の従来技術
では付加容量絶縁膜を介したリーク電流が逆に液晶の保
持動作を妨げる原因になる課題を有していた。小型(対
角画面サイズ2インチ以下)の液晶パネルや高精細化に
よって画素ピッチが50μm以下になる様な液晶パネル
では、液晶容量に比べ付加容量の比率が大きくなり付加
容量を介したリーク電流が問題になってくる。
However, the above-mentioned prior art has a problem that the leak current through the additional capacitance insulating film causes the liquid crystal holding operation to be hindered. In a small-sized (diagonal screen size of 2 inches or less) liquid crystal panel or a liquid crystal panel whose pixel pitch is 50 μm or less due to high definition, the ratio of the additional capacitance is larger than the liquid crystal capacitance, and the leakage current through the additional capacitance is large. It becomes a problem.

【0004】付加容量下電極の電位は液晶駆動電位と等
電位であり交流波形の様に対向電極電位に対してプラス
とマイナスの電位を交互にくり返す。付加容量上電極は
常にしきい値電圧以上の電位差を下電極との間に持たな
ければならないので、下電極電位が対向電極電位に対し
マイナスの状態時には、しきい値電圧を超えた電圧が付
加容量に印加され、リーク電流に対しては不利な状況と
なる。液晶の交流駆動は液晶の寿命の面からみても必要
不可欠で、駆動上避けられない。このリーク電流が大き
くなると表示上画素単位のコントラスト不均一の状態と
なり、パネル表示後の検査で不良となり歩留り低下の原
因となっていた。又この絶縁膜中を流れるリーク電流の
管理は非常に難しく、設計段階での液晶容量と付加容量
の比率を最適化やトランジスタや液晶のリーク電流を低
く押さえることで少しでも保持動作に余裕をもたせるし
か対処の方法がない。商品企画上も小型化、高精細化を
難しくさせる技術的ネックな課題となっていた。そこ
で、本発明はこの様な問題点を解決するもので、その目
的とするところは、付加容量の絶縁膜を介したリーク電
流を低減させ、液晶駆動の保持動作を安定化させるため
の手段を提供するところにある。
The potential of the lower electrode of the additional capacitor is equal to the liquid crystal driving potential, and the positive and negative potentials are alternately repeated with respect to the potential of the counter electrode as in the AC waveform. Since the upper electrode of the additional capacitance must always have a potential difference equal to or higher than the threshold voltage with the lower electrode, when the lower electrode potential is negative with respect to the counter electrode potential, a voltage exceeding the threshold voltage is added. It is applied to the capacitor, which is a disadvantageous situation for the leakage current. AC driving of the liquid crystal is indispensable from the viewpoint of the life of the liquid crystal, and is inevitable in terms of driving. When the leak current becomes large, the contrast becomes non-uniform on a pixel-by-pixel basis on the display, resulting in a defect in the inspection after the panel display, which causes a decrease in yield. In addition, it is very difficult to manage the leak current flowing through this insulating film, and the ratio of liquid crystal capacity to additional capacity is optimized at the design stage, and the leakage current of transistors and liquid crystal is kept low to allow a little holding operation. There is no way to deal with it. In terms of product planning, it was a technical bottleneck that made miniaturization and high definition difficult. Therefore, the present invention solves such a problem, and an object of the present invention is to provide means for reducing the leak current through the insulating film of the additional capacitance and stabilizing the holding operation of the liquid crystal drive. It is in the place of providing.

【0005】[0005]

【課題を解決するための手段】本発明のアクティブマト
リックス基板は、画素電極と対向電極の間の液晶容量と
独立して、該画素電極と電気的導通をもつシリコン薄
膜、該シリコン薄膜とゲートSiO2 膜を介した導電性
薄膜電極の間に付加容量を形成し、該導電性薄膜下部の
シリコン薄膜に不純物原子がドーズされていることを特
徴とする液晶駆動用画素電極と液晶駆動用能動スイッチ
ング素子を有するアクティブマトリックス基板。
An active matrix substrate of the present invention is a silicon thin film having electrical continuity with a pixel electrode and a liquid crystal capacitance between the pixel electrode and a counter electrode, the silicon thin film and the gate SiO 2. Liquid crystal driving pixel electrode and liquid crystal driving active switching, characterized in that an additional capacitance is formed between the conductive thin film electrodes via two films, and impurity atoms are dosed in the silicon thin film under the conductive thin film. An active matrix substrate having elements.

【0006】[0006]

【実施例】本発明の液晶ディスプレイ用アクティブマト
リックス基板は画素中に設けられた付加容量部のリーク
電流を低減させ、保持動作を安定化させて、画素単位の
コントラスト不均一不良を無くすことを目的としてい
る。以下にその手段の詳細な説明を行なう。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The active matrix substrate for a liquid crystal display of the present invention is intended to reduce the leak current of the additional capacitance portion provided in the pixel, stabilize the holding operation, and eliminate the non-uniformity in contrast in pixel units. I am trying. A detailed description of the means will be given below.

【0007】本発明の付加容量の構造を図1に示す。ガ
ラス基板5に容量下電極1、2を形成し、その上に絶縁
膜3を形成し、さらにその上に上電極4を形成した状態
にある。特徴とするところはシリコン薄膜である下電極
の上電極と重なる部分に不純物原子があり、画素電極ス
イッチング能動素子である薄膜トランジスター(以下T
FT−ThinFilmTransisterと示す。)の不純物原子の極
性に応じてP型、N型の不純物原子を選択してドーズさ
れていることである。この図1の構造を上から見た図が
図2で、図2中のA−A′の断面が図1で示されること
になる。10がトランジスタのソースドレイン部で9が
トランジスタのゲート電極を表わす。トランジスタ部は
付加容量部と異なりゲート電極下の導電層シリコン−チ
ャンネル部はイントリンシックでドーズされていない。
付加容量部の上電極6は常に反転層のできるしきい値電
圧以上の電位に設定されるが本発明による構造であると
容量の電圧依存性は無くなり安定な付加容量が形成でき
る。又リーク電流は従来のイントリンシックな構造の場
合、単位面積あたりの電流は2×10-12 A/μm2
(16.5V印加時)なのに対し本発明の構造では2×
10-14 A/μm2 (16.5V印加時)と2ケタ低く
することが可能となった。画素コントラスト不均一不良
は10-14 A/μm以上で起きる場合が多く、余裕を2
ケタ程度稼げるために歩留り向上を期待できる。又画素
コントラスト不均一不良はTFT基板製造段階では発見
することは不可能であり、液晶パネルとして対向電極を
張り合せた後液晶を注入、封止して電圧印加し中間調を
点燈させて初めてこの不良が発見される。つまり良品の
対向基板とパネル組立ての工数が無駄になる可能性が有
り製品コストにハネ返る不良のひとつと考えることがで
きる。本発明によりこの不良が防止できることは製品コ
ストダウンに効果が期待できることになる。リーク電流
がコントラスト不均一不良の原因となる理由を詳細に説
明する。リーク電流は主に4種類有る。ひとつはトラン
ジスタを介したリーク電流であり、ひとつは付加容量を
介したリーク電流がある。また液晶を介して対向電極へ
リークするものや画素電極と並列に並ぶソースラインに
リークする電流の計4種類である。いずれの場合でも画
素電極の電位が画素電極に蓄積された電荷が流れだすこ
とで、対向電極に引かれ、液晶にかかる電位差が低下
し、液晶層の光透過量が印加信号電圧によって期待され
るものと異なってくる。この異なり具合いが数万個有る
画素の間で異なるので映像として同時に全画素を観察し
た場合、不均一なコントラストとなって、あたかも無数
の中間調の点欠陥がある様に写って見える。前述した4
種のリーク電流のうちリークする物の物性に依る所で決
まるものが液晶を介したものと本発明で課題としている
付加容量のリークである。今までは改良するにしても材
料の開発等で物性そのものを変更するしか方法がなかっ
た。しかし本発明の方法によれば付加容量を介したリー
ク電流を若干のプロセス変更で減少させることができ
る。
The structure of the additional capacitor of the present invention is shown in FIG. The capacitor lower electrodes 1 and 2 are formed on the glass substrate 5, the insulating film 3 is formed thereon, and the upper electrode 4 is further formed thereon. The feature is that a thin film transistor (hereinafter referred to as T
It is shown as FT-ThinFilmTransister. That is, the P-type and N-type impurity atoms are selected and dosed according to the polarity of the impurity atoms. FIG. 2 is a view of the structure of FIG. 1 as seen from above, and FIG. 1 is a sectional view taken along line AA ′ in FIG. Reference numeral 10 represents a source / drain portion of the transistor, and 9 represents a gate electrode of the transistor. The transistor portion is different from the additional capacitance portion in that the conductive layer silicon-channel portion under the gate electrode is intrinsic and not dosed.
The upper electrode 6 of the additional capacitance portion is always set to a potential equal to or higher than the threshold voltage of the inversion layer, but the structure according to the present invention eliminates the voltage dependency of the capacitance and can form a stable additional capacitance. In the case of the conventional intrinsic structure, the leakage current is 2 × 10 -12 A / μm 2 per unit area.
(At the time of applying 16.5 V), the structure of the present invention is 2 ×
It was possible to lower the value by 10 digits to 10 −14 A / μm 2 (when 16.5 V was applied). Poor pixel contrast non-uniformity often occurs at 10 -14 A / μm or more, and the margin is 2
Yield improvement can be expected in order to make a profit. In addition, it is impossible to find pixel contrast non-uniformity defects in the TFT substrate manufacturing stage, and only after the opposite electrodes are bonded to each other as a liquid crystal panel, liquid crystal is injected, sealed, and voltage is applied to turn on the halftone. This defect is discovered. In other words, the man-hours for assembling the non-defective counter substrate and the panel may be wasted, and it can be considered as one of the defects that reduce the product cost. The prevention of this defect by the present invention can be expected to be effective in reducing the product cost. The reason why the leak current causes the uneven contrast defect will be described in detail. There are mainly four types of leak current. One is the leak current through the transistor, and the other is the leak current through the additional capacitance. In addition, there are a total of four types: current leaking to the counter electrode through the liquid crystal and current leaking to the source line arranged in parallel with the pixel electrode. In either case, the electric potential accumulated in the pixel electrode flows out from the electric potential of the pixel electrode, the electric potential difference applied to the liquid crystal is reduced by the electric charge accumulated in the pixel electrode, and the light transmission amount of the liquid crystal layer is expected by the applied signal voltage. It will be different from the one. Since the difference is different among tens of thousands of pixels, when all the pixels are simultaneously observed as an image, the contrast becomes non-uniform, and it looks as if there are countless halftone point defects. 4 mentioned above
Among the kinds of leak currents, the ones that are determined depending on the physical properties of the leaking material are the ones through the liquid crystal and the leak of the additional capacitance which is the subject of the present invention. Until now, even if it was improved, the only way to change the physical properties was to develop the material. However, according to the method of the present invention, the leak current through the additional capacitance can be reduced with a slight process change.

【0008】では、本発明の付加容量構造を実現するプ
ロセスについて詳細に述べる。図1で5のガラス基板
(石英ガラス等)上に第1層シリコン薄膜をCVD法
(減圧)で形成し、フォトエッチングで島状にパターニ
ングする。厚さは800Å〜1200Å程度である。こ
のシリコン層は図2に示すトランジスタ部10と付加容
量下電極7、8部である。この後にゲート酸化工程で絶
縁膜(SiO2 )を前述のシリコン薄膜(この後第1層
シリコン薄膜と称す)上に形成する。絶縁膜の厚さは1
100Å〜1300Å程度であり酸化の方法はドライ酸
化で行なう。この後トランジスタ部のみにレジストパタ
ーンを残すフォト工程を行なって後、イオン打込みでリ
ン又はボロンイオンを第1層シリコン薄膜全面にドーズ
する。その後にゲート電極となるシリコン薄膜を減圧C
VD法で形成し、図2、6、9に示すトランジスタゲー
ト電極6と付加容量上電極9の形状にフォトエッチング
法でパターニングする。イオン打込みでトランジスタの
ソース、ドレイン形成の後層間絶縁膜をCVD法やTE
OSで形成し、フォトエッチングでコンタクトホールを
形成して後、画素電極であるITO(インジウム、スズ
の酸化物)をスパッタ法で形成フォトエチングでパター
ニングし、ソースラインのアルミニウムをスパッタ法で
形成し、フォトエッチング法でパターニングする。この
様にして形成したTFT中の第1層シリコン薄膜中に不
純物原子がドープされていると付加容量部のゲート酸化
物を流れる電流がドープされない場合よりも小さく、画
素単位コントラスト不均一不良になりににくい。
Now, the process for realizing the additional capacitance structure of the present invention will be described in detail. A first-layer silicon thin film is formed on the glass substrate (quartz glass or the like) 5 shown in FIG. 1 by the CVD method (reduced pressure), and is patterned into islands by photoetching. The thickness is about 800Å to 1200Å. This silicon layer is the transistor portion 10 and the additional capacitor lower electrodes 7 and 8 shown in FIG. After that, an insulating film (SiO 2 ) is formed on the above-mentioned silicon thin film (hereinafter referred to as a first-layer silicon thin film) in a gate oxidation process. The thickness of the insulating film is 1
It is about 100 Å to 1300 Å, and the oxidation method is dry oxidation. After that, a photo step is performed to leave the resist pattern only in the transistor portion, and then phosphorus or boron ions are ion-implanted to the entire surface of the first-layer silicon thin film. After that, the silicon thin film to be the gate electrode is depressurized C
It is formed by the VD method, and is patterned by the photoetching method into the shapes of the transistor gate electrode 6 and the additional capacitance upper electrode 9 shown in FIGS. After forming the source and drain of the transistor by ion implantation, the interlayer insulating film is formed by CVD or TE.
After forming a contact hole by photo-etching by forming OS, ITO (oxide of indium and tin) which is a pixel electrode is formed by a sputtering method, patterning is performed by photo-etching, and aluminum of a source line is formed by a sputtering method. Patterning is performed by the photo etching method. When the first-layer silicon thin film in the TFT thus formed is doped with impurity atoms, the current flowing through the gate oxide of the additional capacitance portion is smaller than that when it is not doped, resulting in non-uniformity in pixel unit contrast. Difficult

【0009】[0009]

【発明の効果】以上述べた様な発明によれば、液晶駆動
用画素電極と液晶駆動用能動スイッチング素子を有する
アクティブマトリックス基板において、該画素電極と対
向電極の間の液晶容量と独立して、該画素電極と導通を
もつシリコン薄膜、該シリコン薄膜とゲートSiO2
を介した導電性薄膜電極の間に付加容量を形成し、該導
電性薄膜電極下部のシリコン薄膜に不純物原子がドーズ
されていることにより、付加容量部を流れるリーク電流
が、従来の構造に比べ2ケタ低下することで画素コント
ラスト不均一不良を未然に防止することができる効果を
有する。
According to the invention as described above, in an active matrix substrate having a liquid crystal driving pixel electrode and a liquid crystal driving active switching element, independently of the liquid crystal capacitance between the pixel electrode and the counter electrode, A silicon thin film having electrical continuity with the pixel electrode, an additional capacitance is formed between the silicon thin film and the conductive thin film electrode via the gate SiO 2 film, and impurity atoms are dosed to the silicon thin film below the conductive thin film electrode. By doing so, the leak current flowing through the additional capacitance portion is reduced by two digits compared with the conventional structure, so that it is possible to prevent a pixel contrast nonuniformity defect from occurring.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の画素付加容量構造断面図。FIG. 1 is a sectional view of a pixel additional capacitance structure of the present invention.

【図2】本発明の画素付加容量構造平面図。FIG. 2 is a plan view of a pixel additional capacitance structure of the present invention.

【図3】従来の画素付加容量構造断面図。FIG. 3 is a sectional view of a conventional pixel additional capacitance structure.

【図4】従来の画素付加容量構造平面図。FIG. 4 is a plan view of a conventional pixel additional capacitance structure.

【符号の説明】[Explanation of symbols]

1 付加容量下電極ゲート電極との重なり部 2 第1層シリコン薄膜 3 ゲート酸化膜 4 ゲート電極 5 ガラス基板 6 ゲート電極 7 付加容量下電極ゲート電極との重なり部 8 第1層シリコン薄膜 9 ゲート電極 10 トランジスタソースドレイン部 11 トランジスタチャンネル部 12 第1層シリコン薄膜 13 付加容量下電極ゲート電極との重なり部 14 ゲート酸化膜 15 ゲート電極 16 ガラス基板 17 付加容量下電極ゲート電極との重なり部 18 第1層シリコン薄膜 19 ゲート電極 20 トランジスタソースドレイン部 図2中の一点破線A−A′の断面が図1で表わされる。 図4の一点破線B−B′の断面が図3で表わされる。 1 Overlay portion with additional capacitance lower electrode gate electrode 2 First layer silicon thin film 3 Gate oxide film 4 Gate electrode 5 Glass substrate 6 Gate electrode 7 Overlay portion with additional capacitance lower electrode gate electrode 8 First layer silicon thin film 9 Gate electrode 10 Transistor Source / Drain Part 11 Transistor Channel Part 12 First Layer Silicon Thin Film 13 Overlapping Part with Additional Capacitance Lower Electrode Gate Electrode 14 Gate Oxide Film 15 Gate Electrode 16 Glass Substrate 17 Overlapping Part with Additional Capacitance Lower Electrode Gate Electrode 18 1st Layer Silicon thin film 19 Gate electrode 20 Transistor source / drain portion A cross section taken along one-dot chain line AA 'in FIG. 2 is shown in FIG. A cross section taken along one-dot chain line BB ′ of FIG. 4 is shown in FIG.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】液晶駆動用画素電極と液晶駆動用能動スイ
ッチング素子を有するアクティブマトリックス基板にお
いて、該画素電極と対向電極の間の液晶容量と独立し
て、該画素電極と電気的導通をもつシリコン薄膜、該シ
リコン薄膜とゲートSiO2 膜を介した導電性薄膜電極
の間に付加容量を形成し、該導電性薄膜電極下部のシリ
コン薄膜に不純物原子がドーズされていることを特徴と
するアクティブマトリックス基板。
1. An active matrix substrate having a liquid crystal driving pixel electrode and a liquid crystal driving active switching element, the silicon having electrical continuity with the pixel electrode independent of a liquid crystal capacitance between the pixel electrode and a counter electrode. An active matrix characterized in that an additional capacitance is formed between a thin film, the silicon thin film and a conductive thin film electrode via a gate SiO 2 film, and impurity atoms are dosed to the silicon thin film below the conductive thin film electrode. substrate.
JP31275191A 1991-11-27 1991-11-27 Active matrix substrate Pending JPH05150260A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31275191A JPH05150260A (en) 1991-11-27 1991-11-27 Active matrix substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31275191A JPH05150260A (en) 1991-11-27 1991-11-27 Active matrix substrate

Publications (1)

Publication Number Publication Date
JPH05150260A true JPH05150260A (en) 1993-06-18

Family

ID=18032985

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31275191A Pending JPH05150260A (en) 1991-11-27 1991-11-27 Active matrix substrate

Country Status (1)

Country Link
JP (1) JPH05150260A (en)

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