JPH07118443B2 - Manufacturing method of a semiconductor device - Google Patents

Manufacturing method of a semiconductor device

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JPH07118443B2
JPH07118443B2 JP59100180A JP10018084A JPH07118443B2 JP H07118443 B2 JPH07118443 B2 JP H07118443B2 JP 59100180 A JP59100180 A JP 59100180A JP 10018084 A JP10018084 A JP 10018084A JP H07118443 B2 JPH07118443 B2 JP H07118443B2
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thin film
film
source
amorphous silicon
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JPS60245124A (en
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靖夫 狩野
節夫 碓井
俊之 鮫島
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ソニー株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • H01L29/6675Amorphous silicon or polysilicon transistors
    • H01L29/66757Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/268Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • H01L29/6675Amorphous silicon or polysilicon transistors
    • H01L29/66765Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、薄膜トランジスタ(TFT)等の半導体装置の製法に関する。 FIELD OF THE DETAILED DESCRIPTION OF THE INVENTION Industry The present invention relates to a process for the production of a semiconductor device such as a thin film transistor (TFT).

背景技術とその問題点 例えば透過型液晶ディスプレイにおいては、各絵素をオン,オフするためのスイッチング素子として薄膜トランジスタが用いられている。 In Problems e.g. transmission type liquid crystal display with background art, the thin film transistor is used each picture element on, as a switching element for turning off. この場合、薄膜トランジスタは、透明ガラス基板上に多数配列して形成される。 In this case, the thin film transistor is formed by a large number arranged on a transparent glass substrate. 第1 First
図は従来のガラス基板上に薄膜トランジスタを形成する製法例である。 Figure is a process example of forming a thin film transistor of the conventional glass substrate. これは先づ第1図Aに示すようにガラス基板(1)上にアルミニウム又は酸化インジウム錫(以下ITOと略す)等によるゲート電極(2)を形成して後、SiO 2膜(3)、水素化アモルファスシリコン(以下a−Si:Hと略す)膜(4)及びオーミックコンタクト用のn形a−Si:H(n + −a−Si:H)膜(5)を連続してプラズマCVD法で全面に堆積する。 After this form ahead Dzu first (hereinafter abbreviated as ITO), aluminum or indium tin oxide on the glass substrate (1) as shown in Figure A gate electrode by such (2), SiO 2 film (3), hydrogenated amorphous silicon (hereinafter a-Si: H abbreviated) film (4) and n-type a-Si for ohmic contact: H (n + -a-Si : H) plasma CVD continuous film (5) It is deposited over the entire surface by law. 次でa−Si:H膜(4) Next at a-Si: H film (4)
及びn + −a−Si:H膜(5)をパターニングして薄膜トランジスタを作るために必要な部分を島領域化する。 And n + -a-Si: patterning the H film (5) to the island region of the parts necessary to make a thin film transistor. 次に第1図Bに示すようにソース及びドレイン部上にAl/Mo2 Then in Figure 1 the source and drain portions on as shown in B Al / Mo2
層膜構造、モリブデン、チタン又はニクロム等によるソース電極(6)及びドレイン電極(7)を形成する。 Layer film structure to form a molybdenum source electrode (6) by titanium or nichrome or the like, and a drain electrode (7). 次に第1図Cに示すようにソース電極(6)及びドレイン電極(7)間に臨むn + −a−Si:H膜(5)をプラズマエッチング法等により除去し、ソース及びドレイン間のリーク電流をなくす。 Then the first source electrode (6) and a drain electrode (7) as shown in Figure C face between n + -a-Si: H film (5) is removed by plasma etching or the like, between the source and the drain eliminate the leak current. 然る後、第1図Dに示すようにパッシベーション用及び液晶配向用のSiO 2層(8)を全面に形成し、さらにチャンネル部に対応する部分を覆うように遮光層(9)を形成して薄膜トランジスタを形成する。 Thereafter, a passivation as shown in Figure 1 D and the SiO 2 layer for liquid crystal alignment (8) is formed on the entire surface, forming more shielding layer so as to cover the portions corresponding to the channel portion (9) Te to form a thin film transistor.

この製法では、フォトリソグラフィーに使用するマスクとして、ゲート電極(2)のパターン形成用、a−Si:H In this method, a mask used for photolithography, the gate electrode (2) for patterning, a-Si: H
膜(4)の島領域形成用、ソース及びドレイン電極(6)及び(7)のパターン形成用、更に遮光層(9) Film (4) for the island regions forming the source and drain electrodes (6) and the pattern formation of (7), further light shielding layer (9)
のパターン形成用の4枚のマスクが最低必要となる。 Four masks for pattern formation of the lowest necessary.
又、a−Si:H(4)の膜厚は約0.5μm程度ないとn + Also, a-Si: H (4 ) of thickness not about 0.5 [mu] m n + -
a−Si:H膜(5)をエッチング除去する場合に充分な厚みを残せないこと、n + −a−Si:H膜(5)のエッチング工程でのむらやa−Si:H膜(4)の堆積のむらが加わり広い面積に亘って一様な特性の多数の薄膜トランジスタが得にくい等の欠点があった。 a-Si: H film (5) that no leave sufficient thickness when etching is removed, n + -a-Si: unevenness and a-Si at the etching process of the H film (5): H film (4) plurality of thin film transistors of uniform characteristics over a large area unevenness is exerted in the deposition is a defect, such as difficult to obtain. a−Si:H膜(4)が厚いとソース,ドレイン電極(6),(7)の厚みが1μm a-Si: H film (4) is thick and the source, drain electrode (6), the thickness of (7) 1 [mu] m
程度ないと段切れが生じ易い。 The extent and without prone stage breakage.

そしてこの様な厚いa−Si:H膜(4)ではa−Si:Hの光伝導度が大きいために、光を遮蔽するための遮光層(9)が必要となり製造工程を一層複雑にしている。 And such a thick a-Si: In H film (4) a-Si: To photoconductivity of H is large, the light-shielding layer for shielding the light (9) in the more complex the need and becomes the manufacturing process there. a
−Si:H膜(4)は水素化されているため、膜内に欠陥が少く、通常オン/オフ比10 6が得られ、閾値電圧Vth=5V -Si: for H film (4) is hydrogenated, the defect is less in the membrane, normally on / off ratio of 10 6 is obtained, the threshold voltage Vth = 5V
程度のものが得られる。 The extent of what can be obtained. しかし非晶質であるために有効移動度は0.1〜0.5cm 2 /V・Sと小さく、早いスイッチング特性が得られない。 However effective mobility in order to be amorphous as small as 0.1~0.5cm 2 / V · S, not faster switching characteristics.

発明の目的 本発明は、上述の点に鑑み、製造を容易にし、且つ性能の向上が図れる薄膜トランジスタ等の半導体装置の製法を提供するものである。 Object the present invention relates to a view of the above, in which the ease of manufacture and to provide a production method of a semiconductor device such as a thin film transistor can be improved in performance.

発明の概要 本発明は、非晶質基板上に膜厚100Å〜1000Åの非晶質シリコン薄膜を形成した後、非晶質シリコン薄膜表面において吸収される波長100nm〜400nmの短波長パルスレーザ光を照射して非晶質シリコン薄膜の多結晶化の熱処理を行うことを特徴とする半導体装置の製法である。 The present invention, after forming the amorphous silicon thin film having a thickness of 100Å~1000Å on an amorphous substrate, a short wavelength pulse laser light having a wavelength 100nm~400nm absorbed in the amorphous silicon thin film surface is a process of a semiconductor device which is characterized in that the heat treatment of irradiating the polycrystalline amorphous silicon thin film.

この発明の製法では、基体全体を高温にすることなく低温(室温)にて非晶質シリコン薄膜の結晶化、不純物の活性化等が行え性能の向上が図れる。 In the method of the invention, crystallization of the amorphous silicon thin film at a low temperature (room temperature) without the entire substrate to a high temperature, thereby improving the performance it can activate the impurity and the like. また製造が容易となる。 In addition it is easy to manufacture.

実施例 本発明では、結晶化しようとする非晶質シリコン薄膜に短波長パルスレーザを照射したとき、そのレーザ光が非晶質シリコン薄膜の極表面のみで吸収され、その後熱伝導によって薄膜の内部が溶けて再結晶化し、或はアニールされて結晶粒が大きくなることを利用して例えば薄膜トランジスタ等の半導体装置を製造するものである。 In an embodiment the present invention, when irradiated with short-wavelength pulsed laser to an amorphous silicon thin film to be crystallized, the laser light is absorbed only at the extreme surface of the amorphous silicon thin film, the interior of the thin film by the subsequent heat conduction in which it is recrystallized melt, or is annealed to produce a semiconductor device such as a thin-film transistor, for example, by utilizing the fact that the crystal grain becomes large.

例えば非晶質シリコン薄膜としてa−Si:H膜を用いこれに波長308nmのXeClエキシマーレーザ光を照射した場合、この波長に対する吸収係数は10 6 cm -1に達するので、極表面(100Å程度)で吸収され熱に変換される。 For example amorphous silicon thin film as a-Si: when irradiating the an XeCl excimer laser beam having a wavelength of 308nm which with H film, the absorption coefficient for the wavelength reaches 10 6 cm -1, extreme surface (about 100 Å) in is absorbed and converted into heat.
この熱は直ちに熱伝導によって薄膜内部に伝わる。 This heat is transferred to the internal thin film by immediately heat conduction. この様に膜の表面又は内部が瞬間的に高温になるためにa− For surface or inside of such a film becomes momentarily high temperature a-
Si:H膜は水素を出さずに結晶化されその特性は著しく変化する。 Si: H film is its characteristic is crystallized without an hydrogen vary significantly. 例えば膜の移動度が著しく増大し、また光伝導度が低減する。 For example films mobility significantly increased, also the optical conductivity is reduced. またイオン注入された膜はその不純物が活性化される。 The ion-implanted layer is an impurity are activated.

この様な短波長の高エネルギーパルスレーザ光を照射するときは、a−Si:H膜中の水素は放出されず、結晶化した後も結晶粒界のダングリングボンドをなくす働きを行う。 When irradiating a high energy pulsed laser light of such short wavelength, a-Si: hydrogen in the H film is not released, even after crystallization perform work to eliminate the dangling bonds of grain boundaries.

本発明が用いる短波長パルスレーザ光としては、そのレーザ波長が100〜400nm、実用範囲は150〜350nm、パルス幅が100nsec以下で好ましくは10〜50nsec就中20nsecである。 The short-wavelength pulsed laser beam to which the present invention is used, the laser wavelength is 100 to 400 nm, the practical range is 150 to 350 nm, pulse width preferably below 100nsec a 10~50nsec especially 20 nsec. またパルスのピーク強度は10 6 W/cm 2以上〜10 8 W/c The peak intensity of the pulse is 10 6 W / cm 2 or more to 10 8 W / c
m 2以下とし、フルーエンス(1回のパルスのエネルギー)は1J/cm 2以下、好ましくは50mJ/cm 2以上〜500mJ/cm and m 2, fluence (energy of one pulse) is 1 J / cm 2 or less, preferably 50 mJ / cm 2 or more to 500 mJ / cm
2以下、より好ましくは200〜500mJ/cm 2とする。 2 or less, more preferably 200~500mJ / cm 2. このような短波長パルスレーザ光を用いれば局部的な加熱が可能となる。 By using such a short wavelength pulse laser light allows local heating.

次に、図面を参照して本発明の実施例を説明する。 Next, with reference to the accompanying drawings illustrating the embodiment of the present invention. なお、各例は第1図と同様の薄膜トランジスタの製造に適用した場合である。 Each example is when applied to the manufacture of similar thin film transistor and the first FIG.

第2図は本発明の一実施例である。 Figure 2 shows an embodiment of the present invention. 本例においては先づ第2図Aに示すようにガラス基板(1)上にアルミニウム又はITO等によるゲート電極(2)を形成して後、SiO After forming a gate electrode (2) of aluminum or ITO or the like on a glass substrate (1) as shown above Dzu Figure 2 A in this example, SiO
2膜(3)、a−Si:H膜(4)及びn + −a−Si:H膜(5)を順次プラズマCVD法で全面に堆積する。 2 film (3), a-Si: H film (4) and n + -a-Si: depositing over the entire surface by H film are sequentially plasma CVD method (5). 次でa Next in a
−Si:H膜(4)及びn + −a−Si:H膜(5)をパターニングして薄膜トランジスタを作る部分を島領域化する。 -Si: H film (4) and n + -a-Si: patterning the H film (5) to the island region of the portions to make a thin film transistor.

次に、第2図Bに示すように、例えばモリブデン、チタン又はニクロム等によるソース電極(6)及びドレイン電極(7)を形成し、両電極(6)及び(7)をマスクにチャンネル部に対応する部分上のn + −a−Si:H膜(5)をプラズマエッチング法等によって選択除去する(第2図C)。 Next, as shown in FIG. 2 B, such as molybdenum, titanium or to form a source electrode (6) and a drain electrode (7) by such nichrome, both electrodes (6) and (7) in the channel portion in the mask n + -a-Si on the corresponding parts: H film (5) is selectively removed by plasma etching or the like (FIG. 2 C). ここまでの工程は第1図A〜Cの工程と同じである。 Steps up to here are the same as steps in FIG. 1 A through C.

次に、第2図Dに示すように、全面にSiO 2膜(8)を被着形成した後、表面側から短波長パルスレーザ光即ちUV Next, as shown in Figure 2 D, after SiO 2 film (8) is deposited and formed on the entire surface, a short wavelength pulse laser light i.e. UV from the surface side
(紫外線)パルスレーザ光(10)を照射してa−Si:H膜(4)のチャンネル部(4C)を多結晶化し、目的の薄膜トランジスタを得る。 (UV) irradiating pulsed laser light (10) a-Si: polycrystallized channel portion (4C) of the H film (4) to obtain the desired thin film transistor.

この製法ではチャンネル部(4C)のa−Si:H膜を水素を出さずに結晶化できることにより、薄膜トランジスタの移動度を大きくすることができる。 a-Si in the channel portions in this process (4C): by H film can be crystallized without an hydrogen, can be increased mobility of the thin film transistor. 又、a−Si:H膜の結晶化により光伝導度が少なくなり、光が当たってもリーク電流の発生が減少する。 Also, a-Si: photoconductivity is reduced by crystallization H film, even if the light hits reduces occurrence of leakage current. 従って従来のチャンネル部上を覆う遮光層(9)及びその為のマスク工程が省略できる。 Accordingly mask process of the light-shielding layer (9) and its order covering the conventional channel portion can be omitted. UVパルスレーザ光(10)はSiO 2膜(8)を透過し、 UV pulsed laser beam (10) passes through the SiO 2 film (8),
電極(6)(7)で反射するため温度は上らず、電極(6)(7)を損うことなくチャンネル部を処理できる。 Temperature is not climbed to reflect the electrode (6) (7), the electrodes (6) (7) capable of processing channel section without impairing. 因みにアルゴンレーザ、YAGレーザのように長波長レーザでは、膜が薄い場合、光の吸収が小さく長時間の照射となるため、a−Si:H膜全体の温度が上がると共に、基板への熱の影響が大きくなり、基板が変形したり、SiO 2膜(8)、電極(6),(7)等が損傷を受けるという不都合が生じやすい。 Argon laser, a long wavelength laser as YAG lasers Incidentally, when the film is thin, the absorption of light is reduced for a long time irradiation, a-Si: the temperature of the entire H film increases, the heat to the substrate effect is increased, the substrate is deformed or, SiO 2 film (8), the electrode (6), easily occurs inconvenience that (7) or the like is damaged.

このように電極(6)(7)をマスクとして(所謂セルファライメントにより)レーザ照射を行い局部的な結晶化を行うことにより、a−Si:H膜(4)の堆積、電極(6)(7)の形成の後でも照射部以外を非常に高い温度にすることなく低温にての結晶化が可能である。 Thus, by performing the electrodes (6) (the so-called self-alignment) (7) as a mask local crystallization perform laser irradiation, a-Si: H film deposition (4), the electrodes (6) ( it is possible to crystallize the at a low temperature without the very high temperatures other than the irradiation unit even after the formation of 7). 依って薄膜トランジスタの構造及び製造工程を簡単化できる。 It can be simplified structure and manufacturing process of a thin film transistor depending.

第3図はプレーナー型の薄膜トランジスタ製法に適用した他の実施例である。 Figure 3 shows another embodiment applied to a thin film transistor manufacturing method of the planar type.

これは、第3図Aに示すようにガラス基板(1)上にa This, a on a glass substrate (1) as shown in FIG. 3 A
−Si:H膜(4)及びSiO 2膜(3)を順次被着形成し、パターンニングして島領域化する。 -Si: H film (4) and the SiO 2 film (3) were successively deposited and formed, to the island region by being patterned. 次でチャンネル部(4 The channel part in the next (4
C)に対応するSiO 2膜(3)上に例えばチタン、モリブデン又はニクロム等よりなるゲート電極(2)を形成し、このゲート電極(2)をマスクにしてa−Si:H膜(4)のソース部(4S)及びドレイン部(4D)にリン又はボロン等の所要の不純物をイオン注入する。 SiO 2 film (3) on, for example, titanium corresponding to C), to form a gate electrode (2) made of such as molybdenum or nichrome, the gate electrode (2) as a mask a-Si: H film (4) the required impurity ions are implanted, such as the source section (4S) and a drain portion (4D) phosphorus or boron.

次に、第3図Bに示すようにソース及びドレイン部(4 Next, source and drain regions as shown in FIG. 3 B (4
S)及び(4D)に一部接続する如く例えばモリブデン、 S) and (4D) to as to partially connected to, for example molybdenum,
チタン、ニクロム又はITO等によるソース電極(6)及びドレイン電極(7)を被着形成し、さらにSiO 2膜(8)を被着形成する。 Titanium, a source electrode (6) and a drain electrode (7) is deposited and formed by nichrome or ITO or the like, SiO 2 film (8) is deposited and formed. その後、ガラス基板(1)側よりUVパルスレーザ光(10)を照射する。 Thereafter, irradiated from the glass substrate (1) side UV pulsed laser beam (10). これによってソース及びドレイン部(4S)及び(4D)は活性化し、チャンネル部(4C)は結晶化する。 This source and drain portions (4S) and (4D) is activated, the channel part (4C) crystallizes.

この場合、ガラス基板(1)に石英ガラス、パイレックスガラスを用いれば例えば波長308nmのレーザ光は透過するのでa−Si:H膜(4)とガラス基板(1)の界面で光は熱に変わり、a−Si:H膜(4)は熱処理される。 In this case, quartz glass on the glass substrate (1), the laser beam of if a wavelength 308nm using a Pyrex glass is transparent a-Si: light at the interface of the H film (4) and the glass substrate (1) is converted into heat , a-Si: H film (4) is heat treated. 斯くして目的の薄膜トランジスタを得る。 Obtain the desired thin film transistor and thus.

また、UVパルスレーザ光を用いているので、a−Si:H薄膜のみが、短時間加熱後、急冷されるので、ソース、ドレイン部の不純物原子は活性化されるが、長波長パルス(又は連続)レーザ光を用いた時のように横方向への不純物拡散はない。 Moreover, because of the use of UV pulsed laser beam, a-Si: Only H thin film, after briefly heating, since it is rapidly cooled, the source, impurity atoms of the drain unit is activated, a long wavelength pulse (or continuous) no impurity diffusion in the lateral direction as in the case of using a laser beam.

この実施例ではソース、ドレイン部(4S),(4D)のa The source, drain unit in this embodiment (4S), a of (4D)
−Si:H膜も水素を出さずに結晶化されるのでオーミックコンタクトを完全にし、かつ不純物の活性化も充分行なわれ、チャンネル部との界面特性を向上させることができる。 -Si: Since H film is also crystallized without an hydrogen to complete an ohmic contact, and the activation of the impurities are performed sufficiently, thereby improving the interface characteristics between the channel portion. 又、a−Si:H膜(4)を充分薄くでき、膜厚100 Also, a-Si: H film (4) be sufficiently thin, thickness 100
Å〜1000Åの範囲が可能であるため、a−Si:H膜の結晶化に加えて膜厚が薄いことにより、更に光伝導度を少なくすることができリーク電流の発生を減少することができる。 Because the range of Å~1000Å are possible, a-Si: by the thickness in addition to the crystallization of the H film is thin, it is possible to further reduce the occurrence of leakage current can be reduced photoconductivity . 更にa−Si:H膜(4)が薄くできるので、ソース、ドレイン電極の段切れが生じない。 Further a-Si: Since H film (4) can be thin, the source, disconnection of the drain electrode does not occur.

第4図はスタガート型の薄膜トランジスタの製法に適用した他の実施例である。 Figure 4 shows another embodiment applied to preparation of Sutagato thin film transistor.

これは、第4図Aに示すようにガラス基板(1)上に例えばモリブデン、チタン、ニクロム又はITOによるソース電極(6)及びドレイン電極(7)を形成して後、a After this, the fourth glass substrate (1) as shown in Figure A on the example molybdenum, titanium, and a source electrode (6) and a drain electrode (7) by nichrome or ITO, a
−Si:H膜(4)、SiO 2膜(3)を形成する。 -Si: H film (4), to form a SiO 2 film (3) below. さらに例えばアルミニウム又はITOによるゲート電極(2)を形成し、島領域化した表面全体にSiO 2膜(8)を被着形成する。 Furthermore, for example to form a gate electrode (2) of aluminum or ITO, it is deposited and formed a SiO 2 film (8) on the entire island region of the surface. そしてソース及びドレイン部(4S)及び(4D)に対応するa−Si:H膜にリン又はボロン等の所要の不純物をイオン注入する。 The source and drain regions (4S) and corresponding to (4D) a-Si: the required impurity such as phosphorus or boron is ion-implanted into the H film.

次に、第4図Bに示すように表面とガラス基板(1)側の2方向からUVパルスレーザ光(10)を照射し、チャンネル部(4C)を結晶化させ、またソース及びドレイン部(4S)及び(4D)を結晶化と共に不純物の活性化を行う。 Then, irradiation with UV pulsed laser beam (10) from two directions of the fourth surface and the glass substrate (1) as shown in Figure B-side, the channel portion (4C) is crystallized, and the source and drain portions ( 4S) and (4D) to activate the impurity with crystallization. この場合、ソース及びドレイン部(4S)及び(4D) In this case, the source and drain portions (4S) and (4D)
とチャンネル部(4C)のレーザ光の照射条件を変えて、 By changing the channel unit irradiation conditions of the laser beam (4C) and,
それぞれの適正条件を選ぶ。 Choose each of proper conditions.

この実施例ではチャンネル部(4C)とソース、ドレイン部(4S),(4D)に対するレーザ光の照射条件を夫々最適条件に選び得るのでより特性の向上が図れる。 Channel unit in this embodiment (4C) and the source, drain portions (4S), attained more characteristics improve because may opt irradiation conditions of the laser beam respectively optimum conditions for (4D). 又、a In addition, a
−Si:H膜(4)の膜厚も充分薄くできる。 -Si: H film (4) film thickness of the can also be thin enough.

第5図及び第6図はイオン注入工程を省略した更に他の実施例である。 Figure 5 and Figure 6 is a further embodiment is omitted an ion implantation process. 共に不純物ドープのないa−Si:H膜(4)に対してオーミック特性のよい金属例えばニクロムをソース電極(6)及びドレイン電極(7)に用い、 Using the H film (4) a source electrode (6) good metal e.g. nichrome having ohmic characteristics with respect to and the drain electrode (7),: together with no impurity doped a-Si
表裏2方向よりUVパルスレーザ光(10)を照射してチャンネル部分(4C)及びソース部(4S)、ドレイン部(4 Channel portion from front and back directions by irradiating UV pulsed laser beam (10) (4C) and the source portions (4S), the drain portion (4
D)の結晶化を行う。 Performing crystallization of D). この場合、UVパルスレーザ光(1 In this case, UV pulsed laser light (1
0)をソース、ドレイン部(4S),(4D)に照射するとき電極界面が充分オーミックになるようにUV照射条件(強さ、時間)を選ぶ。 0) source, a drain portion (4S), choosing (UV irradiation conditions so that the electrode interface is sufficiently ohmic when irradiated to 4D) (intensity and time). また場合によっては、例えばn + In some cases, for example, n +
形に対してリン(P)、ヒ素(As)、アンチモン(Sb) Phosphorus relative form (P), arsenic (As), antimony (Sb)
等の5価元素を、P +形に対してボロン(B)、アルミニウム(Al)、ガリウム(Ga)等の3価元素を含むソース、ドレイン電極(6),(7)を用いるのも良い。 The pentavalent element etc., boron (B) with respect to the P +, aluminum (Al), the source comprising a trivalent element of gallium (Ga), or the like, the drain electrode (6), may be used to (7) . ソース、ドレイン電極(6),(7)としてはニクロムの他ITO、モリブデン又はチタン等を用いることができる。 Source and drain electrodes (6), it is possible to use other ITO, molybdenum or titanium or the like of nichrome as (7). この製法では特に不純物のイオン注入工程が省略されるので、製造工程がより簡単化される。 Since the ion implantation process, especially impurities in this process is omitted, and the manufacturing process is more simplified. 第5図の構成は、第2図の実施例においてn + −a−Si:H膜(5)を省略したものであり、従って、第2図に比してa−Si:H膜(4)を充分薄くでき、例えば200Å程度とすることができ、その分光伝導度が減り特性がより向上する。 Configuration of FIG. 5 is, n + in the embodiment of FIG. 2 -a-Si: is obtained by omitting the H film (5), therefore, in comparison with Figure 2 a-Si: H film (4 ) be sufficiently thin, for example, be a 200Å about characteristic reduces its spectral conductivity is further improved.

尚、第2図〜第6図の実施例を液晶ディスプレイ等に応用する場合には全体をSiO 2等の配向用絶縁層を被着する必要がある。 Incidentally, it is necessary to deposit an alignment insulation layer of SiO 2 or the like the whole in the case of applying the embodiment of FIG. 2-FIG. 6 in a liquid crystal display or the like. この層を300℃程度の高温で作る場合はソース、ドレイン電極はAlを用いることができないが、蒸着等の低温プロセスを用いればプラズマによるSiO 2 、a Source when making this layer of approximately 300 ° C. at high temperature, the drain electrode can not be used Al, SiO 2 by plasma by using the low temperature process such as vapor deposition, a
−Si:Hの堆積以外はすべて低温(室温)プロセスで高性能の薄膜トランジスタアレイを作ることが可能である。 -Si: All H except the deposition it is possible to produce high-performance thin-film transistor array at a low temperature (room temperature) process.

上述の実施例によれば、基体全体を高温にすることなく、低温でチャンネル部のa−Si:H膜を水素を出さずに結晶化できることにより、薄膜トランジスタの移動度を大きくすることができ、早いスイッチング特性が得られる。 According to the above-described embodiment, without the entire substrate to a high temperature, of the channel portion a-Si at low temperatures: The ability to crystallize H film without producing hydrogen, it is possible to increase the mobility of the thin film transistor, fast switching characteristics can be obtained. そして、基板への熱の影響が及びにくいので、基板変形が起こりにくい。 Then, the influence of heat Oyobi difficult to substrate, substrate deformation is unlikely to occur.

又、a−Si:H膜を結晶化することにより、又充分薄くできることにより、光伝導度を小さく光が照射されてもリーク電流が流れにくくなる。 Also, a-Si: by crystallizing H film, the ability to sufficiently thin Furthermore, even when the light conductivity decreases light is irradiated hardly leak current flows. このため遮光層が省略される。 Therefore shielding layer is omitted. 又、高エネルギー、短時間の短波長パルスレーザ光を用いることにより、低温でa−Si:H膜の結晶化ができ、従って電極形成、パッシベーション膜の形成後に結晶化工程を行うことが可能となる。 Further, by using a high energy, short duration short wavelength pulse laser light, at low temperature a-Si: H film can be crystallized, and therefore the electrode formation can be performed crystallization step after formation of a passivation film Become. 従って、薄膜トランジスタの構成及び製造工程が簡単になり、また生産の歩留りも向上するものである。 Therefore, configuration and manufacturing process of a thin film transistor is simplified, also but also improves the yield of production. 又、薄膜トランジスタアレイの製造に適用した場合には、各トランジスタ共に均一な特性が得られる。 Further, when applied to the production of the thin film transistor array, each transistor both uniform characteristics can be obtained.

尚、上例ではa−Si:H薄膜を用いた場合について説明したが、水素を含まない非晶質シリコン薄膜の場合においても、a−Si:H薄膜の場合と同様に波長100nm〜400nmの光に対してこの光が極表面で吸収され、同様に実施することができる。 In the above example a-Si: has been described with H thin film, even in the case of amorphous silicon thin film not containing hydrogen, a-Si: For H film as well as the wavelength 100nm~400nm this light is absorbed by the electrode surface to light it can be carried out similarly. その際、基板変形を起こすことなく結晶化できること、電極形成、パッシベーション膜の形成後の結晶化、不純物の活性化に関しては水素を含む非晶質シリコン薄膜の場合と同様の作用効果を奏するものである。 At that time, can be crystallized without causing deformation of the substrate, electrodes formed, crystallization after forming the passivation film, with respect to the activation of the impurities intended to the same operational advantages as in the case of amorphous silicon thin film containing hydrogen is there.

発明の効果 本発明によれば、短波長パルスレーザ光を用いることにより、膜の極表面のみが瞬時に熱せられるため、基板への熱の影響が及びにくくなり、基板の変形を起こすことなく、非晶質シリコン薄膜を局部的に結晶化でき、又不純物の活性化もでき、例えば移動度の大きい薄膜に変えることができる。 According to the present invention, by using a short wavelength pulse laser light, since only the extreme surface of the film is heated instantaneously, influence of heat on the substrate is less likely Oyobi, without causing deformation of the substrate, it can locally crystallize the amorphous silicon thin film, and the activation of the impurities can, for example, can be converted into large thin mobility. しかも、この結晶化、活性化は基体全体を高温にすることなく、低温で行えるので、電極形成、パッシベーション膜の形成後に結晶化、活性化工程を行うことができる。 Moreover, the crystallization activation without the entire substrate to a high temperature, since performed at low temperature, it is possible to perform electrode formation, crystallization after the formation of the passivation film, the activation step. 特に、膜厚100Å〜1000Åの非晶質シリコン薄膜に対して波長100nm〜400nmの短波長パルスレーザ光を照射すると、レーザ光は薄膜内部でほぼ10 In particular, when irradiated with short wavelength pulse laser light having a wavelength 100nm~400nm respect amorphous silicon thin film having a thickness of 100 Å to 1000 Å, the laser light is substantially within the film 10
0%吸収され、基板側にもれないので、基板としてガラス基板のような低耐熱性基板を用いることができ、この低耐熱性基板上に形成した非晶質シリコン薄膜の溶融結晶化が可能となる。 Absorbed 0% and does not leak to the substrate side, it is possible to use a low heat resistant substrate such as a glass substrate as the substrate, it can be melt crystallization of the amorphous silicon thin film formed on the low heat resistant substrate to become. 従って、例えば薄膜トランジスタに適用した場合、その性能を向上し、かつ製造を容易にするものである。 Thus, for example, when applied to a thin film transistor, in which improved its performance, and ease of manufacture.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

第1図は従来の薄膜トランジスタの製法の一例を示す工程図、第2図は本発明による薄膜トランジスタの製法の一実施例を示す工程図、第3図乃至第6図は夫々本発明による薄膜トランジスタの製法の他の実施例を示す断面図である。 Process diagram showing an example of FIG. 1 is a conventional thin film transistor manufacturing method, FIG. 2 is a process diagram showing an embodiment of a thin film transistor of the process according to the invention, FIG. 3 to FIG. 6 is a thin film transistor according to each invention process it is a sectional view showing another embodiment of. (1)はガラス基板、(2)はゲート電極、(3)はSi (1) a glass substrate, (2) a gate electrode, (3) Si
O 2膜、(4)はa−Si:H膜、(5)はn + −a−Si:H膜、 O 2 film, (4) a-Si: H film, (5) the n + -a-Si: H film,
(6)はソース電極、(7)はドレイン電極、(10)は短波長パルスレーザ光である。 (6) is a source electrode, (7) a drain electrode (10) is a short wavelength pulse laser light.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 狩野 靖夫 東京都品川区北品川6丁目7番35号 ソニ ー株式会社内 (56)参考文献 特開 昭57−104217(JP,A) 特開 昭57−155726(JP,A) 特開 昭58−197717(JP,A) 特開 昭57−138129(JP,A) 特開 昭57−194518(JP,A) 特開 昭58−182816(JP,A) ────────────────────────────────────────────────── ─── of the front page continued (72) inventor Yasuo Kano Shinagawa-ku, Tokyo Kita 6-chome No. 7 No. 35 Sony over within Co., Ltd. (56) reference Patent Sho 57-104217 (JP, a) JP Akira 57-155726 (JP, A) JP Akira 58-197717 (JP, A) JP Akira 57-138129 (JP, A) JP Akira 57-194518 (JP, A) JP Akira 58-182816 (JP, A)

Claims (1)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】非晶質基板上に膜厚100Å〜1000Åの非晶質シリコン薄膜を形成した後、該非晶質シリコン薄膜表面において吸収される波長100nm〜400nmの短波長パルスレーザ光を照射して上記非晶質シリコン薄膜の多結晶化の熱処理を行うことを特徴とする半導体装置の製法。 [Claim 1] After forming an amorphous silicon thin film having a thickness of 100Å~1000Å on an amorphous substrate, by irradiating a short wavelength pulse laser light having a wavelength 100nm~400nm absorbed in the amorphous silicon thin film surface preparation of a semiconductor device which is characterized in that the heat treatment of the polycrystalline of the amorphous silicon thin Te.
JP59100180A 1984-05-18 1984-05-18 Manufacturing method of a semiconductor device Expired - Lifetime JPH07118443B2 (en)

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