JPH07118443B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device

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Publication number
JPH07118443B2
JPH07118443B2 JP59100180A JP10018084A JPH07118443B2 JP H07118443 B2 JPH07118443 B2 JP H07118443B2 JP 59100180 A JP59100180 A JP 59100180A JP 10018084 A JP10018084 A JP 10018084A JP H07118443 B2 JPH07118443 B2 JP H07118443B2
Authority
JP
Japan
Prior art keywords
film
thin film
manufacturing
source
amorphous silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59100180A
Other languages
Japanese (ja)
Other versions
JPS60245124A (en
Inventor
節夫 碓井
俊之 鮫島
靖夫 狩野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
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Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP59100180A priority Critical patent/JPH07118443B2/en
Publication of JPS60245124A publication Critical patent/JPS60245124A/en
Publication of JPH07118443B2 publication Critical patent/JPH07118443B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • H01L29/6675Amorphous silicon or polysilicon transistors
    • H01L29/66757Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/268Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • H01L29/6675Amorphous silicon or polysilicon transistors
    • H01L29/66765Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Ceramic Engineering (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Optics & Photonics (AREA)
  • Electromagnetism (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Recrystallisation Techniques (AREA)

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、薄膜トランジスタ(TFT)等の半導体装置の
製法に関する。
Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device such as a thin film transistor (TFT).

背景技術とその問題点 例えば透過型液晶ディスプレイにおいては、各絵素をオ
ン,オフするためのスイッチング素子として薄膜トラン
ジスタが用いられている。この場合、薄膜トランジスタ
は、透明ガラス基板上に多数配列して形成される。第1
図は従来のガラス基板上に薄膜トランジスタを形成する
製法例である。これは先づ第1図Aに示すようにガラス
基板(1)上にアルミニウム又は酸化インジウム錫(以
下ITOと略す)等によるゲート電極(2)を形成して
後、SiO2膜(3)、水素化アモルファスシリコン(以下
a−Si:Hと略す)膜(4)及びオーミックコンタクト用
のn形a−Si:H(n+−a−Si:H)膜(5)を連続してプ
ラズマCVD法で全面に堆積する。次でa−Si:H膜(4)
及びn+−a−Si:H膜(5)をパターニングして薄膜トラ
ンジスタを作るために必要な部分を島領域化する。次に
第1図Bに示すようにソース及びドレイン部上にAl/Mo2
層膜構造、モリブデン、チタン又はニクロム等によるソ
ース電極(6)及びドレイン電極(7)を形成する。次
に第1図Cに示すようにソース電極(6)及びドレイン
電極(7)間に臨むn+−a−Si:H膜(5)をプラズマエ
ッチング法等により除去し、ソース及びドレイン間のリ
ーク電流をなくす。然る後、第1図Dに示すようにパッ
シベーション用及び液晶配向用のSiO2層(8)を全面に
形成し、さらにチャンネル部に対応する部分を覆うよう
に遮光層(9)を形成して薄膜トランジスタを形成す
る。
Background Art and its Problems For example, in a transmissive liquid crystal display, a thin film transistor is used as a switching element for turning on and off each picture element. In this case, a large number of thin film transistors are arranged and formed on the transparent glass substrate. First
The figure shows an example of a conventional method of manufacturing a thin film transistor on a glass substrate. First, as shown in FIG. 1A, after forming a gate electrode (2) of aluminum or indium tin oxide (hereinafter abbreviated as ITO) on a glass substrate (1), a SiO 2 film (3), Hydrogenated amorphous silicon (hereinafter abbreviated as a-Si: H) film (4) and n-type a-Si: H (n + -a-Si: H) film (5) for ohmic contact are continuously plasma-enhanced by plasma CVD. It is deposited on the entire surface by the method. Then a-Si: H film (4)
And the n + -a-Si: H film (5) is patterned to form island regions in the portions necessary for producing thin film transistors. Next, as shown in FIG. 1B, Al / Mo2 is formed on the source and drain portions.
A source electrode (6) and a drain electrode (7) are formed of a layer film structure, molybdenum, titanium, or nichrome. Next, as shown in FIG. 1C, the n + -a-Si: H film (5) facing between the source electrode (6) and the drain electrode (7) is removed by a plasma etching method or the like, and the n Eliminate leakage current. Then, as shown in FIG. 1D, a SiO 2 layer (8) for passivation and liquid crystal alignment is formed on the entire surface, and a light shielding layer (9) is formed so as to cover a portion corresponding to the channel portion. To form a thin film transistor.

この製法では、フォトリソグラフィーに使用するマスク
として、ゲート電極(2)のパターン形成用、a−Si:H
膜(4)の島領域形成用、ソース及びドレイン電極
(6)及び(7)のパターン形成用、更に遮光層(9)
のパターン形成用の4枚のマスクが最低必要となる。
又、a−Si:H(4)の膜厚は約0.5μm程度ないとn+
a−Si:H膜(5)をエッチング除去する場合に充分な厚
みを残せないこと、n+−a−Si:H膜(5)のエッチング
工程でのむらやa−Si:H膜(4)の堆積のむらが加わり
広い面積に亘って一様な特性の多数の薄膜トランジスタ
が得にくい等の欠点があった。a−Si:H膜(4)が厚い
とソース,ドレイン電極(6),(7)の厚みが1μm
程度ないと段切れが生じ易い。
In this manufacturing method, as a mask used for photolithography, a-Si: H for pattern formation of the gate electrode (2) is used.
For forming island regions of the film (4), for forming patterns of the source and drain electrodes (6) and (7), and further for a light shielding layer (9)
At least four masks for pattern formation are required.
If the film thickness of a-Si: H (4) is about 0.5 μm, n +
A sufficient thickness cannot be left when the a-Si: H film (5) is removed by etching, unevenness in the etching process of the n + -a-Si: H film (5), and the a-Si: H film (4) However, there is a drawback in that it is difficult to obtain a large number of thin film transistors having uniform characteristics over a wide area due to the unevenness of deposition. If the a-Si: H film (4) is thick, the thickness of the source and drain electrodes (6) and (7) is 1 μm.
If it is not so high, breaks easily occur.

そしてこの様な厚いa−Si:H膜(4)ではa−Si:Hの光
伝導度が大きいために、光を遮蔽するための遮光層
(9)が必要となり製造工程を一層複雑にしている。a
−Si:H膜(4)は水素化されているため、膜内に欠陥が
少く、通常オン/オフ比106が得られ、閾値電圧Vth=5V
程度のものが得られる。しかし非晶質であるために有効
移動度は0.1〜0.5cm2/V・Sと小さく、早いスイッチン
グ特性が得られない。
Since such a thick a-Si: H film (4) has a large photoconductivity of a-Si: H, a light-shielding layer (9) for shielding light is required, which makes the manufacturing process more complicated. There is. a
-Si: H film (4) has been hydrogenated, so there are few defects in the film, an on / off ratio of 10 6 is usually obtained, and the threshold voltage Vth = 5V.
You can get something. However, since it is amorphous, the effective mobility is as small as 0.1 to 0.5 cm 2 / V · S, and fast switching characteristics cannot be obtained.

発明の目的 本発明は、上述の点に鑑み、製造を容易にし、且つ性能
の向上が図れる薄膜トランジスタ等の半導体装置の製法
を提供するものである。
SUMMARY OF THE INVENTION In view of the above points, the present invention provides a method of manufacturing a semiconductor device such as a thin film transistor, which can be manufactured easily and whose performance can be improved.

発明の概要 本発明は、非晶質基板上に膜厚100Å〜1000Åの非晶質
シリコン薄膜を形成した後、非晶質シリコン薄膜表面に
おいて吸収される波長100nm〜400nmの短波長パルスレー
ザ光を照射して非晶質シリコン薄膜の多結晶化の熱処理
を行うことを特徴とする半導体装置の製法である。
SUMMARY OF THE INVENTION The present invention, after forming an amorphous silicon thin film having a film thickness of 100 Å ~ 1000 Å on an amorphous substrate, a short wavelength pulse laser light having a wavelength of 100 nm ~ 400 nm absorbed on the surface of the amorphous silicon thin film. A method for manufacturing a semiconductor device is characterized in that the amorphous silicon thin film is irradiated and heat treatment for polycrystallizing the amorphous silicon thin film is performed.

この発明の製法では、基体全体を高温にすることなく低
温(室温)にて非晶質シリコン薄膜の結晶化、不純物の
活性化等が行え性能の向上が図れる。また製造が容易と
なる。
According to the manufacturing method of the present invention, the amorphous silicon thin film can be crystallized and impurities can be activated at a low temperature (room temperature) without raising the temperature of the entire substrate to improve the performance. In addition, manufacturing becomes easy.

実施例 本発明では、結晶化しようとする非晶質シリコン薄膜に
短波長パルスレーザを照射したとき、そのレーザ光が非
晶質シリコン薄膜の極表面のみで吸収され、その後熱伝
導によって薄膜の内部が溶けて再結晶化し、或はアニー
ルされて結晶粒が大きくなることを利用して例えば薄膜
トランジスタ等の半導体装置を製造するものである。
Example In the present invention, when the amorphous silicon thin film to be crystallized is irradiated with a short-wavelength pulse laser, the laser light is absorbed only by the extreme surface of the amorphous silicon thin film, and then the internal portion of the thin film is thermally conductive. Is melted and recrystallized, or annealed to increase the size of crystal grains, thereby manufacturing a semiconductor device such as a thin film transistor.

例えば非晶質シリコン薄膜としてa−Si:H膜を用いこれ
に波長308nmのXeClエキシマーレーザ光を照射した場
合、この波長に対する吸収係数は106cm-1に達するの
で、極表面(100Å程度)で吸収され熱に変換される。
この熱は直ちに熱伝導によって薄膜内部に伝わる。この
様に膜の表面又は内部が瞬間的に高温になるためにa−
Si:H膜は水素を出さずに結晶化されその特性は著しく変
化する。例えば膜の移動度が著しく増大し、また光伝導
度が低減する。またイオン注入された膜はその不純物が
活性化される。
For example, when an a-Si: H film is used as an amorphous silicon thin film and this is irradiated with XeCl excimer laser light with a wavelength of 308 nm, the absorption coefficient for this wavelength reaches 10 6 cm -1 , so the surface (about 100 Å) Is absorbed by and converted into heat.
This heat is immediately transferred to the inside of the thin film by heat conduction. In this way, the surface or inside of the film is momentarily heated to a high temperature.
The Si: H film is crystallized without releasing hydrogen, and its characteristics change significantly. For example, the mobility of the film is significantly increased and the photoconductivity is reduced. Further, the ion-implanted film has its impurities activated.

この様な短波長の高エネルギーパルスレーザ光を照射す
るときは、a−Si:H膜中の水素は放出されず、結晶化し
た後も結晶粒界のダングリングボンドをなくす働きを行
う。
When such a high-energy pulsed laser beam having a short wavelength is irradiated, hydrogen in the a-Si: H film is not released, and it functions to eliminate dangling bonds at crystal grain boundaries even after crystallization.

本発明が用いる短波長パルスレーザ光としては、そのレ
ーザ波長が100〜400nm、実用範囲は150〜350nm、パルス
幅が100nsec以下で好ましくは10〜50nsec就中20nsecで
ある。またパルスのピーク強度は106W/cm2以上〜108W/c
m2以下とし、フルーエンス(1回のパルスのエネルギ
ー)は1J/cm2以下、好ましくは50mJ/cm2以上〜500mJ/cm
2以下、より好ましくは200〜500mJ/cm2とする。このよ
うな短波長パルスレーザ光を用いれば局部的な加熱が可
能となる。
The short wavelength pulsed laser light used in the present invention has a laser wavelength of 100 to 400 nm, a practical range of 150 to 350 nm, and a pulse width of 100 nsec or less, preferably 10 to 50 nsec, especially 20 nsec. The peak intensity of the pulse is 10 6 W / cm 2 or more to 10 8 W / c.
m 2 or less, fluence (energy of one pulse) is 1 J / cm 2 or less, preferably 50 mJ / cm 2 or more to 500 mJ / cm
2 or less, more preferably 200 to 500 mJ / cm 2 . If such a short wavelength pulsed laser beam is used, local heating can be performed.

次に、図面を参照して本発明の実施例を説明する。な
お、各例は第1図と同様の薄膜トランジスタの製造に適
用した場合である。
Next, embodiments of the present invention will be described with reference to the drawings. In addition, each example is a case where it is applied to manufacture of a thin film transistor similar to that in FIG.

第2図は本発明の一実施例である。本例においては先づ
第2図Aに示すようにガラス基板(1)上にアルミニウ
ム又はITO等によるゲート電極(2)を形成して後、SiO
2膜(3)、a−Si:H膜(4)及びn+−a−Si:H膜
(5)を順次プラズマCVD法で全面に堆積する。次でa
−Si:H膜(4)及びn+−a−Si:H膜(5)をパターニン
グして薄膜トランジスタを作る部分を島領域化する。
FIG. 2 shows an embodiment of the present invention. In this example, first, as shown in FIG. 2A, after forming the gate electrode (2) of aluminum or ITO on the glass substrate (1), SiO 2 is formed.
The 2 film (3), the a-Si: H film (4) and the n + -a-Si: H film (5) are sequentially deposited on the entire surface by the plasma CVD method. Next a
By patterning the -Si: H film (4) and the n + -a-Si: H film (5), a portion for forming a thin film transistor is formed into an island region.

次に、第2図Bに示すように、例えばモリブデン、チタ
ン又はニクロム等によるソース電極(6)及びドレイン
電極(7)を形成し、両電極(6)及び(7)をマスク
にチャンネル部に対応する部分上のn+−a−Si:H膜
(5)をプラズマエッチング法等によって選択除去する
(第2図C)。ここまでの工程は第1図A〜Cの工程と
同じである。
Next, as shown in FIG. 2B, a source electrode (6) and a drain electrode (7) made of, for example, molybdenum, titanium, or nichrome are formed, and both electrodes (6) and (7) are used as a mask to form a channel portion. The n + -a-Si: H film (5) on the corresponding portion is selectively removed by plasma etching or the like (FIG. 2C). The steps up to this point are the same as the steps shown in FIGS.

次に、第2図Dに示すように、全面にSiO2膜(8)を被
着形成した後、表面側から短波長パルスレーザ光即ちUV
(紫外線)パルスレーザ光(10)を照射してa−Si:H膜
(4)のチャンネル部(4C)を多結晶化し、目的の薄膜
トランジスタを得る。
Next, as shown in FIG. 2D, after a SiO 2 film (8) is formed on the entire surface, a short wavelength pulse laser beam, that is, UV
Irradiation with (ultraviolet) pulsed laser light (10) is performed to polycrystallize the channel portion (4C) of the a-Si: H film (4) to obtain the target thin film transistor.

この製法ではチャンネル部(4C)のa−Si:H膜を水素を
出さずに結晶化できることにより、薄膜トランジスタの
移動度を大きくすることができる。又、a−Si:H膜の結
晶化により光伝導度が少なくなり、光が当たってもリー
ク電流の発生が減少する。従って従来のチャンネル部上
を覆う遮光層(9)及びその為のマスク工程が省略でき
る。UVパルスレーザ光(10)はSiO2膜(8)を透過し、
電極(6)(7)で反射するため温度は上らず、電極
(6)(7)を損うことなくチャンネル部を処理でき
る。因みにアルゴンレーザ、YAGレーザのように長波長
レーザでは、膜が薄い場合、光の吸収が小さく長時間の
照射となるため、a−Si:H膜全体の温度が上がると共
に、基板への熱の影響が大きくなり、基板が変形した
り、SiO2膜(8)、電極(6),(7)等が損傷を受け
るという不都合が生じやすい。
In this manufacturing method, the mobility of the thin film transistor can be increased because the a-Si: H film of the channel portion (4C) can be crystallized without releasing hydrogen. Also, the crystallization of the a-Si: H film reduces the photoconductivity, and the generation of leak current is reduced even when exposed to light. Therefore, the conventional light-shielding layer (9) covering the channel portion and the masking process therefor can be omitted. The UV pulsed laser light (10) passes through the SiO 2 film (8),
Since the light is reflected by the electrodes (6) and (7), the temperature does not rise, and the channel portion can be processed without damaging the electrodes (6) and (7). By the way, in a long-wavelength laser such as an argon laser or a YAG laser, when the film is thin, light absorption is small and irradiation is performed for a long time. Therefore, the temperature of the entire a-Si: H film rises and the heat of the substrate The influence is increased and the substrate is likely to be deformed, and the SiO 2 film (8), the electrodes (6), (7) and the like are easily damaged.

このように電極(6)(7)をマスクとして(所謂セル
ファライメントにより)レーザ照射を行い局部的な結晶
化を行うことにより、a−Si:H膜(4)の堆積、電極
(6)(7)の形成の後でも照射部以外を非常に高い温
度にすることなく低温にての結晶化が可能である。依っ
て薄膜トランジスタの構造及び製造工程を簡単化でき
る。
In this way, laser irradiation (by so-called self-alignment) is performed by using the electrodes (6) and (7) as masks to perform local crystallization, thereby depositing the a-Si: H film (4), the electrode (6) ( Even after the formation of 7), it is possible to crystallize at a low temperature without raising the temperature other than the irradiated portion to a very high temperature. Therefore, the structure and manufacturing process of the thin film transistor can be simplified.

第3図はプレーナー型の薄膜トランジスタ製法に適用し
た他の実施例である。
FIG. 3 shows another embodiment applied to a planar type thin film transistor manufacturing method.

これは、第3図Aに示すようにガラス基板(1)上にa
−Si:H膜(4)及びSiO2膜(3)を順次被着形成し、パ
ターンニングして島領域化する。次でチャンネル部(4
C)に対応するSiO2膜(3)上に例えばチタン、モリブ
デン又はニクロム等よりなるゲート電極(2)を形成
し、このゲート電極(2)をマスクにしてa−Si:H膜
(4)のソース部(4S)及びドレイン部(4D)にリン又
はボロン等の所要の不純物をイオン注入する。
This is done on the glass substrate (1) as shown in FIG. 3A.
A Si: H film (4) and a SiO 2 film (3) are sequentially deposited and patterned to form island regions. Next in the channel section (4
A gate electrode (2) made of, for example, titanium, molybdenum, or nichrome is formed on the SiO 2 film (3) corresponding to C), and the gate electrode (2) is used as a mask to form an a-Si: H film (4). Into the source part (4S) and the drain part (4D) of the above, the necessary impurities such as phosphorus or boron are ion-implanted.

次に、第3図Bに示すようにソース及びドレイン部(4
S)及び(4D)に一部接続する如く例えばモリブデン、
チタン、ニクロム又はITO等によるソース電極(6)及
びドレイン電極(7)を被着形成し、さらにSiO2
(8)を被着形成する。その後、ガラス基板(1)側よ
りUVパルスレーザ光(10)を照射する。これによってソ
ース及びドレイン部(4S)及び(4D)は活性化し、チャ
ンネル部(4C)は結晶化する。
Next, as shown in FIG. 3B, the source and drain portions (4
S) and (4D) are partially connected, such as molybdenum,
A source electrode (6) and a drain electrode (7) made of titanium, nichrome, ITO or the like are deposited, and a SiO 2 film (8) is deposited. Then, UV pulse laser light (10) is irradiated from the glass substrate (1) side. As a result, the source and drain parts (4S) and (4D) are activated, and the channel part (4C) is crystallized.

この場合、ガラス基板(1)に石英ガラス、パイレック
スガラスを用いれば例えば波長308nmのレーザ光は透過
するのでa−Si:H膜(4)とガラス基板(1)の界面で
光は熱に変わり、a−Si:H膜(4)は熱処理される。斯
くして目的の薄膜トランジスタを得る。
In this case, if quartz glass or Pyrex glass is used for the glass substrate (1), laser light having a wavelength of 308 nm, for example, is transmitted, so the light changes to heat at the interface between the a-Si: H film (4) and the glass substrate (1). , A-Si: H film (4) is heat-treated. Thus, the target thin film transistor is obtained.

また、UVパルスレーザ光を用いているので、a−Si:H薄
膜のみが、短時間加熱後、急冷されるので、ソース、ド
レイン部の不純物原子は活性化されるが、長波長パルス
(又は連続)レーザ光を用いた時のように横方向への不
純物拡散はない。
Further, since the UV pulsed laser light is used, only the a-Si: H thin film is heated for a short time and then rapidly cooled, so that the impurity atoms in the source and drain parts are activated, but the long wavelength pulse (or There is no lateral impurity diffusion as when using continuous laser light.

この実施例ではソース、ドレイン部(4S),(4D)のa
−Si:H膜も水素を出さずに結晶化されるのでオーミック
コンタクトを完全にし、かつ不純物の活性化も充分行な
われ、チャンネル部との界面特性を向上させることがで
きる。又、a−Si:H膜(4)を充分薄くでき、膜厚100
Å〜1000Åの範囲が可能であるため、a−Si:H膜の結晶
化に加えて膜厚が薄いことにより、更に光伝導度を少な
くすることができリーク電流の発生を減少することがで
きる。更にa−Si:H膜(4)が薄くできるので、ソー
ス、ドレイン電極の段切れが生じない。
In this embodiment, a of source and drain parts (4S) and (4D)
Since the -Si: H film is also crystallized without releasing hydrogen, the ohmic contact is completed and the impurities are sufficiently activated, so that the interface characteristics with the channel portion can be improved. Also, the a-Si: H film (4) can be made sufficiently thin, and the film thickness is 100
Since the range from Å to 1000Å is possible, the photoconductivity can be further reduced and the generation of leak current can be reduced due to the thin film thickness in addition to the crystallization of the a-Si: H film. . Furthermore, since the a-Si: H film (4) can be made thin, disconnection of the source and drain electrodes does not occur.

第4図はスタガート型の薄膜トランジスタの製法に適用
した他の実施例である。
FIG. 4 shows another embodiment applied to a method of manufacturing a staggered thin film transistor.

これは、第4図Aに示すようにガラス基板(1)上に例
えばモリブデン、チタン、ニクロム又はITOによるソー
ス電極(6)及びドレイン電極(7)を形成して後、a
−Si:H膜(4)、SiO2膜(3)を形成する。さらに例え
ばアルミニウム又はITOによるゲート電極(2)を形成
し、島領域化した表面全体にSiO2膜(8)を被着形成す
る。そしてソース及びドレイン部(4S)及び(4D)に対
応するa−Si:H膜にリン又はボロン等の所要の不純物を
イオン注入する。
This is done by forming a source electrode (6) and a drain electrode (7) of, for example, molybdenum, titanium, nichrome or ITO on the glass substrate (1) as shown in FIG.
-Si: H film (4), to form a SiO 2 film (3). Further, for example, a gate electrode (2) made of aluminum or ITO is formed, and a SiO 2 film (8) is deposited on the entire surface of the island region. Then, necessary impurities such as phosphorus or boron are ion-implanted into the a-Si: H film corresponding to the source and drain portions (4S) and (4D).

次に、第4図Bに示すように表面とガラス基板(1)側
の2方向からUVパルスレーザ光(10)を照射し、チャン
ネル部(4C)を結晶化させ、またソース及びドレイン部
(4S)及び(4D)を結晶化と共に不純物の活性化を行
う。この場合、ソース及びドレイン部(4S)及び(4D)
とチャンネル部(4C)のレーザ光の照射条件を変えて、
それぞれの適正条件を選ぶ。
Next, as shown in FIG. 4B, UV pulse laser light (10) is irradiated from two directions on the surface and the glass substrate (1) side to crystallize the channel part (4C), and also to source and drain parts ( 4S) and (4D) are crystallized and impurities are activated. In this case, the source and drain parts (4S) and (4D)
And changing the irradiation condition of the laser light of the channel part (4C),
Select the appropriate conditions for each.

この実施例ではチャンネル部(4C)とソース、ドレイン
部(4S),(4D)に対するレーザ光の照射条件を夫々最
適条件に選び得るのでより特性の向上が図れる。又、a
−Si:H膜(4)の膜厚も充分薄くできる。
In this embodiment, the laser light irradiation conditions for the channel part (4C) and the source / drain parts (4S), (4D) can be selected as optimum conditions, so that the characteristics can be further improved. Also, a
The film thickness of the -Si: H film (4) can be made sufficiently thin.

第5図及び第6図はイオン注入工程を省略した更に他の
実施例である。共に不純物ドープのないa−Si:H膜
(4)に対してオーミック特性のよい金属例えばニクロ
ムをソース電極(6)及びドレイン電極(7)に用い、
表裏2方向よりUVパルスレーザ光(10)を照射してチャ
ンネル部分(4C)及びソース部(4S)、ドレイン部(4
D)の結晶化を行う。この場合、UVパルスレーザ光(1
0)をソース、ドレイン部(4S),(4D)に照射すると
き電極界面が充分オーミックになるようにUV照射条件
(強さ、時間)を選ぶ。また場合によっては、例えばn+
形に対してリン(P)、ヒ素(As)、アンチモン(Sb)
等の5価元素を、P+形に対してボロン(B)、アルミニ
ウム(Al)、ガリウム(Ga)等の3価元素を含むソー
ス、ドレイン電極(6),(7)を用いるのも良い。ソ
ース、ドレイン電極(6),(7)としてはニクロムの
他ITO、モリブデン又はチタン等を用いることができ
る。この製法では特に不純物のイオン注入工程が省略さ
れるので、製造工程がより簡単化される。第5図の構成
は、第2図の実施例においてn+−a−Si:H膜(5)を省
略したものであり、従って、第2図に比してa−Si:H膜
(4)を充分薄くでき、例えば200Å程度とすることが
でき、その分光伝導度が減り特性がより向上する。
5 and 6 show still another embodiment in which the ion implantation process is omitted. A metal having good ohmic characteristics, such as nichrome, is used for the source electrode (6) and the drain electrode (7) for both the a-Si: H film (4) which is not doped with impurities.
UV pulsed laser light (10) is applied from the front and back sides, and the channel part (4C), source part (4S), drain part (4)
Crystallize D). In this case, UV pulsed laser light (1
UV irradiation conditions (strength, time) are selected so that the electrode interface becomes sufficiently ohmic when the source / drain parts (4S) and (4D) are irradiated with (0). In some cases, for example, n +
Phosphorus (P), arsenic (As), antimony (Sb) for shape
It is also possible to use source and drain electrodes (6), (7) containing trivalent elements such as boron (B), aluminum (Al), gallium (Ga), etc., for pentavalent elements such as P + type. . As the source and drain electrodes (6) and (7), ITO, molybdenum, titanium or the like can be used in addition to nichrome. In this manufacturing method, the ion implantation step of impurities is omitted in particular, so that the manufacturing process is further simplified. The structure shown in FIG. 5 is obtained by omitting the n + -a-Si: H film (5) in the embodiment shown in FIG. 2, and therefore, compared with the structure shown in FIG. ) Can be made sufficiently thin, for example, can be set to about 200Å, its spectral conductivity is reduced, and the characteristics are further improved.

尚、第2図〜第6図の実施例を液晶ディスプレイ等に応
用する場合には全体をSiO2等の配向用絶縁層を被着する
必要がある。この層を300℃程度の高温で作る場合はソ
ース、ドレイン電極はAlを用いることができないが、蒸
着等の低温プロセスを用いればプラズマによるSiO2、a
−Si:Hの堆積以外はすべて低温(室温)プロセスで高性
能の薄膜トランジスタアレイを作ることが可能である。
When the embodiment of FIGS. 2 to 6 is applied to a liquid crystal display or the like, it is necessary to cover the entire surface with an insulating layer for alignment such as SiO 2 . When this layer is formed at a high temperature of about 300 ° C., Al cannot be used for the source and drain electrodes, but if a low temperature process such as vapor deposition is used, SiO 2 and a
High-performance thin film transistor arrays can be fabricated by low temperature (room temperature) processes except for the deposition of -Si: H.

上述の実施例によれば、基体全体を高温にすることな
く、低温でチャンネル部のa−Si:H膜を水素を出さずに
結晶化できることにより、薄膜トランジスタの移動度を
大きくすることができ、早いスイッチング特性が得られ
る。そして、基板への熱の影響が及びにくいので、基板
変形が起こりにくい。
According to the above-described embodiment, the mobility of the thin film transistor can be increased by crystallizing the a-Si: H film of the channel portion at a low temperature without releasing hydrogen without raising the temperature of the entire substrate. Fast switching characteristics can be obtained. Further, since the influence of heat on the substrate is less likely to occur, the substrate is less likely to be deformed.

又、a−Si:H膜を結晶化することにより、又充分薄くで
きることにより、光伝導度を小さく光が照射されてもリ
ーク電流が流れにくくなる。このため遮光層が省略され
る。又、高エネルギー、短時間の短波長パルスレーザ光
を用いることにより、低温でa−Si:H膜の結晶化がで
き、従って電極形成、パッシベーション膜の形成後に結
晶化工程を行うことが可能となる。従って、薄膜トラン
ジスタの構成及び製造工程が簡単になり、また生産の歩
留りも向上するものである。又、薄膜トランジスタアレ
イの製造に適用した場合には、各トランジスタ共に均一
な特性が得られる。
Further, by crystallizing the a-Si: H film and making it sufficiently thin, the photoconductivity is small and the leak current becomes difficult to flow even when irradiated with light. Therefore, the light shielding layer is omitted. Also, by using a high-energy, short-time, short-wavelength pulsed laser light, the a-Si: H film can be crystallized at a low temperature, so that the crystallization process can be performed after the electrode formation and the passivation film formation. Become. Therefore, the structure and manufacturing process of the thin film transistor are simplified, and the production yield is improved. When applied to the manufacture of a thin film transistor array, uniform characteristics can be obtained for each transistor.

尚、上例ではa−Si:H薄膜を用いた場合について説明し
たが、水素を含まない非晶質シリコン薄膜の場合におい
ても、a−Si:H薄膜の場合と同様に波長100nm〜400nmの
光に対してこの光が極表面で吸収され、同様に実施する
ことができる。その際、基板変形を起こすことなく結晶
化できること、電極形成、パッシベーション膜の形成後
の結晶化、不純物の活性化に関しては水素を含む非晶質
シリコン薄膜の場合と同様の作用効果を奏するものであ
る。
In the above example, the case of using the a-Si: H thin film was described, but in the case of an amorphous silicon thin film containing no hydrogen, the wavelength of 100 nm to 400 nm is the same as in the case of the a-Si: H thin film. For light, this light is absorbed at the polar surface and can be similarly implemented. At that time, regarding the ability to crystallize without causing substrate deformation, electrode formation, crystallization after formation of a passivation film, and activation of impurities, the same effect as in the case of an amorphous silicon thin film containing hydrogen can be obtained. is there.

発明の効果 本発明によれば、短波長パルスレーザ光を用いることに
より、膜の極表面のみが瞬時に熱せられるため、基板へ
の熱の影響が及びにくくなり、基板の変形を起こすこと
なく、非晶質シリコン薄膜を局部的に結晶化でき、又不
純物の活性化もでき、例えば移動度の大きい薄膜に変え
ることができる。しかも、この結晶化、活性化は基体全
体を高温にすることなく、低温で行えるので、電極形
成、パッシベーション膜の形成後に結晶化、活性化工程
を行うことができる。特に、膜厚100Å〜1000Åの非晶
質シリコン薄膜に対して波長100nm〜400nmの短波長パル
スレーザ光を照射すると、レーザ光は薄膜内部でほぼ10
0%吸収され、基板側にもれないので、基板としてガラ
ス基板のような低耐熱性基板を用いることができ、この
低耐熱性基板上に形成した非晶質シリコン薄膜の溶融結
晶化が可能となる。従って、例えば薄膜トランジスタに
適用した場合、その性能を向上し、かつ製造を容易にす
るものである。
EFFECTS OF THE INVENTION According to the present invention, by using a short-wavelength pulsed laser beam, only the extreme surface of the film is instantly heated, so that the influence of heat on the substrate is less likely to occur and the substrate is not deformed. The amorphous silicon thin film can be locally crystallized, impurities can be activated, and the amorphous silicon thin film can be converted into, for example, a thin film having high mobility. Moreover, since this crystallization and activation can be performed at a low temperature without raising the temperature of the entire substrate, the crystallization and activation steps can be performed after the electrode formation and the passivation film formation. In particular, when an amorphous silicon thin film with a film thickness of 100 Å to 1000 Å is irradiated with short-wavelength pulse laser light with a wavelength of 100 nm to 400 nm, the laser light is almost 10
Since it is absorbed by 0% and does not leak to the substrate side, it is possible to use a low heat resistant substrate such as a glass substrate, and it is possible to melt and crystallize the amorphous silicon thin film formed on this low heat resistant substrate. Becomes Therefore, when it is applied to, for example, a thin film transistor, its performance is improved and manufacturing is facilitated.

【図面の簡単な説明】[Brief description of drawings]

第1図は従来の薄膜トランジスタの製法の一例を示す工
程図、第2図は本発明による薄膜トランジスタの製法の
一実施例を示す工程図、第3図乃至第6図は夫々本発明
による薄膜トランジスタの製法の他の実施例を示す断面
図である。 (1)はガラス基板、(2)はゲート電極、(3)はSi
O2膜、(4)はa−Si:H膜、(5)はn+−a−Si:H膜、
(6)はソース電極、(7)はドレイン電極、(10)は
短波長パルスレーザ光である。
FIG. 1 is a process drawing showing an example of a conventional thin film transistor manufacturing method, FIG. 2 is a process drawing showing an example of a thin film transistor manufacturing method according to the present invention, and FIGS. 3 to 6 are respectively thin film transistor manufacturing methods according to the present invention. It is sectional drawing which shows the other Example. (1) is a glass substrate, (2) is a gate electrode, (3) is Si
O 2 film, (4) a-Si: H film, (5) n + -a-Si: H film,
(6) is a source electrode, (7) is a drain electrode, and (10) is short-wavelength pulsed laser light.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 狩野 靖夫 東京都品川区北品川6丁目7番35号 ソニ ー株式会社内 (56)参考文献 特開 昭57−104217(JP,A) 特開 昭57−155726(JP,A) 特開 昭58−197717(JP,A) 特開 昭57−138129(JP,A) 特開 昭57−194518(JP,A) 特開 昭58−182816(JP,A) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasuo Kano 6-735 Kitashinagawa, Shinagawa-ku, Tokyo Sony Corporation (56) References JP-A-57-104217 (JP, A) JP-A-SHO 57-155726 (JP, A) JP-A-58-197717 (JP, A) JP-A-57-138129 (JP, A) JP-A-57-194518 (JP, A) JP-A-58-182816 (JP, A) A)

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】非晶質基板上に膜厚100Å〜1000Åの非晶
質シリコン薄膜を形成した後、該非晶質シリコン薄膜表
面において吸収される波長100nm〜400nmの短波長パルス
レーザ光を照射して上記非晶質シリコン薄膜の多結晶化
の熱処理を行うことを特徴とする半導体装置の製法。
1. An amorphous silicon thin film having a film thickness of 100Å to 1000Å is formed on an amorphous substrate, and then a short wavelength pulsed laser beam having a wavelength of 100 nm to 400 nm absorbed on the surface of the amorphous silicon thin film is irradiated. And a heat treatment for polycrystallizing the amorphous silicon thin film.
JP59100180A 1984-05-18 1984-05-18 Manufacturing method of semiconductor device Expired - Lifetime JPH07118443B2 (en)

Priority Applications (1)

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JP59100180A JPH07118443B2 (en) 1984-05-18 1984-05-18 Manufacturing method of semiconductor device

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JP6181909A Division JP2546538B2 (en) 1994-07-11 1994-07-11 Thin film transistor manufacturing method
JP18191294A Division JPH0750257A (en) 1994-07-11 1994-07-11 Manufacture of semiconductor device
JP25126796A Division JP2725669B2 (en) 1996-09-24 1996-09-24 Semiconductor device manufacturing method

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Publication Number Publication Date
JPS60245124A JPS60245124A (en) 1985-12-04
JPH07118443B2 true JPH07118443B2 (en) 1995-12-18

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