JPS58182816A - Recrystallizing method of silicon family semiconductor material - Google Patents

Recrystallizing method of silicon family semiconductor material

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Publication number
JPS58182816A
JPS58182816A JP57065827A JP6582782A JPS58182816A JP S58182816 A JPS58182816 A JP S58182816A JP 57065827 A JP57065827 A JP 57065827A JP 6582782 A JP6582782 A JP 6582782A JP S58182816 A JPS58182816 A JP S58182816A
Authority
JP
Japan
Prior art keywords
silicon
based semiconductor
substrate
film
semiconductor material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57065827A
Other languages
Japanese (ja)
Inventor
Keiji Kobayashi
啓二 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP57065827A priority Critical patent/JPS58182816A/en
Publication of JPS58182816A publication Critical patent/JPS58182816A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H01L21/02683—Continuous wave laser beam
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/0242—Crystalline insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02595—Microstructure polycrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02598—Microstructure monocrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02609—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02689—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using particle beams
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02691—Scanning of a beam

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Optics & Photonics (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To synthesize polycrystalline silicon which is proximate to single crystal by such an arrangement wherein polycrystalline silicon is melted by heating, and molten silicon is caused to single-crystallize or microcrystalline by zone melt method. CONSTITUTION:On a substrate 1 made of sapphire or quartz glass, a film 2 of SiO2 of 0.3mum is provided by oxidization at a high temperature. On the film 2 of SiO2, a film of about 0.5mum in thickness of silicon family semiconductor consists of noncrystalline silicon or polycrystalline silicon is formed by spatter method, etc. After that, this specimen is heated and processed at such temperatures lower than the softening temperature of the substrate 1 and higher than the melting point of the film 3 of silicon family semiconductor, and the silicon family semiconductor film 3 is caused to single-crystallize or microcrystallize. As said heat processing, for example, high frequency melting may be made at 1,250 deg.C by using carbon as a heat generating substance and further annealing is made and then B or P may be introduced by ion injecting method, or annealing may be made in the atmosphere of gases such as Ar, N2, etc.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、非品質シリコンや多結晶シリコン等のシリコ
ン系半導体を単結晶化若しくは微結晶化せしめるシリコ
ン系半導体材料の再結晶方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of recrystallizing a silicon-based semiconductor material for single-crystallizing or microcrystallizing a silicon-based semiconductor such as non-quality silicon or polycrystalline silicon.

〔発明の技術的背景とその間融点〕[Technical background of the invention and its melting point]

従来の技術としては、非晶質シリ′コンや多結晶シリコ
ン等に＠接しーザーアニールを行って結晶化したり、ｐ
形、ｎ形をつくるために、シラン（ＳβＨ，）にジホラ
ン、フォスフインを加えることによって所望の４亀形を
得ていた。しかし、この方法では得られた結晶粒径が１
〜２〔μη１〕程度であり、充分高い正孔移動度、電子
移動度が得られず、半導体の特性の電圧電流曲線の再現
性も充分でなく、液晶テレビなどの商運デバイスとして
使用するには困難である。また減圧ＣＶＤ法によって多
結晶シリコンを基板上に直接つける方法があるが、非晶
質シリコンに比べて膜厚を厚くすることが困難であり、
長時間を要するという欠点がある。Conventional techniques include crystallizing amorphous silicon, polycrystalline silicon, etc. by @ contact laser annealing, and
In order to create the n-type and the n-type, the desired four-tortoise shape was obtained by adding diphorane and phosphine to silane (SβH,). However, with this method, the obtained crystal grain size is 1
~2 [μη1], it is not possible to obtain sufficiently high hole mobility and electron mobility, and the reproducibility of the voltage-current curve of semiconductor characteristics is not sufficient, so it cannot be used as a commercial device such as an LCD TV. It is difficult. There is also a method of applying polycrystalline silicon directly onto a substrate using low pressure CVD, but it is difficult to increase the film thickness compared to amorphous silicon.
The disadvantage is that it takes a long time.

〔発明の目的〕[Purpose of the invention]

本発明の目ｆｌ’ｌは、グロー放電法やスパッター法に
よって作製された非晶質シリコン或いはＣＶＤ法によっ
て作製された多結晶シリコンを加熱溶融、ゾーンメルト
法によって単結晶化若しくは咳結晶化し、単結晶に近い
多結晶シリコンを合成し得るシリコン系半導体材料の再
結晶方法を提供することにある。なお、ここでいつは結
晶化とは必ずしも系全体に結晶が分散している状態では
なく、部分的微結晶或いは結晶と非晶質との共存による
不均質構造をも含む。The object of the present invention is to melt amorphous silicon produced by a glow discharge method or a sputtering method or polycrystalline silicon produced by a CVD method and turn it into a single crystal or a single crystal by a zone melt method. An object of the present invention is to provide a method for recrystallizing a silicon-based semiconductor material that can synthesize polycrystalline silicon close to crystalline. Note that crystallization here does not necessarily mean a state in which crystals are dispersed throughout the system, but also includes a heterogeneous structure due to partial microcrystals or the coexistence of crystals and amorphous materials.

〔発明の概要〕[Summary of the invention]

本発明は、基板の上にグロー放電による非晶質シリコン
或いはＣＶＤ法による多結晶シリコンからなるシリコン
系半導体を形成したのち、熱、レーザ光、放射線等をエ
ネルギ源とし、上記シリコン系半導体を基板の軟化温度
以下で、かつシリコン系半導体の融点より高い温度で加
熱処理し、シリコン系半導体を単結晶化若しくは微結晶
化するようにした方法である。なお、グロー放電によっ
て水素や弗素等を導入して作成した非晶質シリコンを上
記エネルギー源を使用して微結晶化させてもよい。さら
に、微結晶化させる過程に於て、Ａｒ　＋　Ｃｇ　Ｎ＠
　＠　Ｎ２　　ガス雰囲気中で行ってもよく、非晶質シ
リコンを微結晶化させてｎ形、ｐ形導電形を形成させた
多結晶シリコンを得ることも可能である。また、加熱処
理の温度な基板の軟化点以下にしている理由は、これ以
上の温度で処理すると基板がたわんでしまい、半導体基
板として使用不能となるからである。The present invention involves forming a silicon-based semiconductor made of amorphous silicon by glow discharge or polycrystalline silicon by CVD on a substrate, and then using heat, laser light, radiation, etc. as an energy source to convert the silicon-based semiconductor into a substrate. In this method, the silicon-based semiconductor is heat-treated at a temperature below the softening temperature of the silicon-based semiconductor and above the melting point of the silicon-based semiconductor to single-crystallize or microcrystallize the silicon-based semiconductor. Note that amorphous silicon created by introducing hydrogen, fluorine, etc. by glow discharge may be microcrystallized using the above energy source. Furthermore, in the process of microcrystallization, Ar + Cg N@
The process may be carried out in an @N2 gas atmosphere, and it is also possible to microcrystallize amorphous silicon to obtain polycrystalline silicon with n-type and p-type conductivity. The reason why the heat treatment temperature is set below the softening point of the substrate is that if the temperature is higher than this, the substrate will warp and become unusable as a semiconductor substrate.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、上記の過程を経た多結晶シリコンを基
板として用い、例えば電界効果トランジスタを作製して
見ると、ＦＥＴの正孔移動度が９０〜２５　Ｑ　Ｃｃｍ
”／　１ｉｅ（！　）程度であり、しきい値電圧のばら
つきが少く、リーク電流も１０　　（Ａ）程度のものが
得られた。また、基板の結晶粒径も３〜１５〔μ＋Ａ）
程度のものであり、これらの基板はＦＥＴだけではなく
太ｌｌ＃１電池、ビデオディスク基板としても工業的に
使用可能である。したがって、本発明方法の有用性は極
めて大きい。According to the present invention, for example, when a field effect transistor is manufactured using polycrystalline silicon that has undergone the above process as a substrate, the hole mobility of the FET is 90 to 25 Q Ccm.
”/1ie (!), with little variation in threshold voltage, and a leakage current of about 10 (A). Also, the crystal grain size of the substrate was 3 to 15 [μ+A].
These substrates can be used industrially not only as FETs but also as #1 batteries and video disk substrates. Therefore, the usefulness of the method of the present invention is extremely large.

〔発明の実施例〕[Embodiments of the invention]

図は本発明の詳細な説明するだめの断面図である。まず
、サファイアや石英ガラス等からなる基板１を用いて、
この基板１上に０．３〔μｍ〕の厚さの８１０．膜２を
高温酸化でつける。このＳｉｎ、膜２上に約０５〔μｍ
〕の厚さの非晶質シリコン或いは多結晶シリコンからな
るシリコン系半導体膜３をスパッター法文ｔよグロー放
電法で膜付けする。しかるのち、この試料を基板１の軟
化温度以下でシリコン系半導体膜３の融点以上の温度で
加熱処理して、シリコン系半導体膜３を単結晶化若しく
は微結晶化せしめる。ここで上記加熱処理としては、例
えば１２５０（’Ｃ）で炭素を発熱体として高周波溶融
を行い、さらにアニールを行ったのち、イオン注入法で
Ｂ或いはＰを導入してもよく、またＡ　ｒ　、　Ｎ１等
のガス雰囲気中でアニールを行ってもよい。さらにこれ
らのシリコン系半導体膜３中に水素或いは弗素を導入し
て糸を安定化し、微結晶化させてもよい。基板のアニー
ルはレーザーアニール。The figure is a cross-sectional view for detailed explanation of the invention. First, using a substrate 1 made of sapphire, quartz glass, etc.
On this substrate 1, 810. Film 2 is applied by high temperature oxidation. This Sin is approximately 05 μm thick on the film 2.
A silicon-based semiconductor film 3 made of amorphous silicon or polycrystalline silicon having a thickness of ] is deposited by a glow discharge method using a sputtering method. Thereafter, this sample is heat-treated at a temperature below the softening temperature of the substrate 1 and above the melting point of the silicon-based semiconductor film 3 to make the silicon-based semiconductor film 3 monocrystalline or microcrystalline. Here, as the above heat treatment, for example, high frequency melting may be performed at 1250 ('C) using carbon as a heating element, and after further annealing, B or P may be introduced by ion implantation, or A r , Annealing may be performed in a gas atmosphere such as N1. Furthermore, hydrogen or fluorine may be introduced into these silicon-based semiconductor films 3 to stabilize the threads and make them microcrystalline. The substrate is annealed by laser annealing.

Ｍ７二−ル、電子ビームアニーノン等いスレか一回以上
行ってもよい。You may go to threads such as M7 Neil, Electron Beam Anion, etc. more than once.

〈実施例１、〉 前記した酸化膜とＣＶＤ法で多結晶シリコンをサファイ
ア基板上につける。次いで　１４００〔℃〕の高度で一
坦溶融を行ったのち、ＣＷ　−Ａ　ｒレーザーで（１２
Ｗ、スキャン速度２５　（，７１１／　Ｓ　。<Example 1> Polycrystalline silicon is deposited on a sapphire substrate using the oxide film described above and the CVD method. Next, after performing uniform melting at an altitude of 1400 [℃], a CW-Ar laser (12
W, scan speed 25 (,711/S.

基板１１Ｍ１ｉｌ１５０℃）アニール後、Ｐのイオン注
入をドーズｔｔ　ｌ　Ｘ　１０”　（ＣｒＩＬ−”）、
加速電圧１３０（Ｋｅ　Ｖ）で行った。これを用いてＰ
−チャンネルＡｌゲートＦＥＴを作製し、正孔移動度を
測定したととろμｓ　−１７０〔（、ｍ２／　Ｖ　・ｓ
ｅｃ　）リーク電−，，（Ａ） 流１０　　　であった。結晶粒径は約１２〔μ＋Ａ）で
あった。作製した膜をｘＨ回折で調べたところ結晶方位
（１１１）、（１１０）、（１００）の回折パターンが
認められた。After annealing (substrate 11M1il150°C), P ion implantation dose tt l x 10"(CrIL-"),
The acceleration voltage was 130 (Ke V). Using this, P
- A channel Al-gate FET was fabricated and the hole mobility was measured at a temperature of μs -170 [(, m2/V s
ec) Leakage current,, (A) Current was 10. The crystal grain size was approximately 12 [μ+A). When the produced film was examined by xH diffraction, diffraction patterns of crystal orientations (111), (110), and (100) were observed.

〈実施例２〉 酸化膜、水素含有多結晶質シリコンを石英基板上にっけ
、１２００（’Ｃ）でゾーンメルトを行った。次いで、
アニール後Ｐのイオン注入をドーズ閂Ｉ　Ｘ　１０”　
（ａｌｌ−”）、加速電圧１３０　（Ｋｅｙ）で行った
。これを用いてＰ−チャネルＦＥＴを作製し、正孔移動
度を測定したところ、μｅ−１５０（ｃｙａ”／Ｖ、　
５ｅｅ）　　、　　リ　−　り　”ＪＬ’ａｔ　　５ｘ
　　１　０　−＋。<Example 2> An oxide film and hydrogen-containing polycrystalline silicon were placed on a quartz substrate, and zone melting was performed at 1200 ('C). Then,
After annealing, the dose of P ion implantation is I x 10”
(all-") at an accelerating voltage of 130 (Key). Using this, a P-channel FET was fabricated and the hole mobility was measured.
5ee), ``JL'at 5x''
1 0 −+.

（Ａ）であった。粒径は１５〔μｍ〕であった。作製し
たポリシリコ〕ノの結晶方位は（１１１）。It was (A). The particle size was 15 [μm]. The crystal orientation of the produced polysilico is (111).

（１１０）等であった。(110) etc.

〈実施例３〉 前記サファイア基板、酸化膜、多結晶シリコンを用い、
３１−構造にしたものを１２５０（”Ｃ）の温度で１０
分間熱処理したのち、２００　（’Ｃ）で電子ビームア
ニールを行い単結晶化させた。ドーズｔｉｉ　２　Ｘ　
１０”　（ｃＩｎ−”）　、加速電圧１００　（Ｋｅｙ
）でＰのイオン注入を行い、ＰチャネルＦＥＴを作製し
、正孔移動度を測定したところμｅ＝２５０（ｃｍ’／
　Ｖ、　ｌ１ｅｃ　）であった。粒径は１０　Ｃｓ瑯〕
であり、多結晶の方位は（１００）のものが析出してい
ることをＸ線回析で確認した。<Example 3> Using the sapphire substrate, oxide film, and polycrystalline silicon,
31-The structure is heated to 10 at a temperature of 1250 ("C).
After heat treatment for a minute, electron beam annealing was performed at 200 ('C) to form a single crystal. dose tii 2x
10"(cIn-"), acceleration voltage 100 (Key
), P ion implantation was performed to fabricate a P channel FET, and the hole mobility was measured, μe = 250 (cm'/
V, l1ec). Particle size is 10 Cs
It was confirmed by X-ray diffraction that the polycrystal orientation was (100).

〈実施例４．〉 前記石英基板、酸化膜、Ｌｐ−ＣＶＤ法による多結晶シ
リコンを用い、３層構造にしたものを１３００（’Ｃ）
のＩＭＩｉｔで１０分間熱処理した。その後、Ａｒガス
中でレーザアニールしドース１１１Ｘ　ｌ　Ｏ”　（ｃ
ＩＩＬ−″２〕、加速電圧１３０　ＣＫｅ　Ｖ）でＰの
イオン注入を行い、Ｐチャン不ノンＦＥＴを作製し、正
孔移動ｉｔを測定したところＰ　ｅ−１７０（ｃＩＩＬ
”／Ｖ　＋ｓｅｃ　）であった。粒径は灼１０〔μｍ〕
であり、結晶方位は（１００）（１１０）等が析出して
いた。<Example 4. 〉 1300 ('C) has a three-layer structure using the quartz substrate, oxide film, and polycrystalline silicon produced by Lp-CVD method.
Heat treatment was performed using IMIit for 10 minutes. After that, laser annealing was performed in Ar gas at a dose of 111X l O” (c
P ion implantation was performed at an accelerating voltage of 130 CKe V) to fabricate a P-channel non-FET, and hole transfer was measured.
”/V +sec).The particle size was 10 [μm].
, and crystal orientations such as (100) and (110) were precipitated.

〈実施例５．〉 前記サファイア基板、酸化膜、グロー放電による水素含
有アモルファスｓ＋をつけた基板を１０００（’Ｃ）の
温度で１０分間熱処理したのちＮ、雰囲気中で１５０℃
熱線アニールした。この非晶質シリコン中にＰをドーズ
駄ｌＸ１Ｏ”（ｃＩｎ−”）、加速′４圧１２０　（Ｋ
ｅＶ）　ノ条件で注入をし、ＦＥＴを作製し、正孔移動
度を測定したところμｅ　−０，５（ｃｉ”／Ｖ−ｓｅ
ａ）、粒径は５００（Ａ）、リーク電流は１Ｏ−１２（
”〕であった。結晶方位は（１００）（１１１）（１１
０）が析出していた。<Example 5. > The sapphire substrate, the oxide film, and the substrate with hydrogen-containing amorphous S+ formed by glow discharge were heat-treated at a temperature of 1000 ('C) for 10 minutes, and then heated at 150 °C in a N atmosphere.
Hot wire annealed. P is dosed into this amorphous silicon, accelerated at a pressure of 120 (K
When injection was carried out under conditions of
a), particle size is 500 (A), leakage current is 1O-12 (
”].The crystal orientation was (100)(111)(11
0) was precipitated.

以上説明した実施例から判るように、本発明は非晶質シ
リコン或いは多結晶シリコンから単結晶若しくは漱結晶
を有するすぐれた半導体材料を合成する方法であり、工
業的にすぐれた合成方法であるということができる。As can be seen from the examples described above, the present invention is a method for synthesizing an excellent semiconductor material having a single crystal or a grain crystal from amorphous silicon or polycrystalline silicon, and is said to be an industrially excellent synthesis method. be able to.

【図面の簡単な説明】[Brief explanation of drawings]

図は本発明の詳細な説明する断面図である。 図において、１・・・ウェハー、２・・・酸化膜、３・
・・アモルファスシリコン、４・・・イオン注入、５・
・・レーザアニール。The figure is a sectional view illustrating the invention in detail. In the figure, 1... wafer, 2... oxide film, 3...
...Amorphous silicon, 4...Ion implantation, 5.
...Laser annealing.

Claims (5)

【特許請求の範囲】[Claims] （１）　　基板上に非晶質シリコン或いは多結晶シリコ
ンからなるシリコン系半導体を被看したのち、上記基板
の軟化温度以下でかつ上記半導体の融点以上の温度で加
熱処理し、該半導体を単結晶化若しくは微結晶化させる
ことを特徴とするシリコン系半導体材料の再結晶方法。(1) After placing a silicon-based semiconductor made of amorphous silicon or polycrystalline silicon on a substrate, heat treatment is performed at a temperature below the softening temperature of the substrate and above the melting point of the semiconductor to convert the semiconductor into a single crystal. 1. A method for recrystallizing a silicon-based semiconductor material, the method comprising crystallizing or microcrystallizing a silicon-based semiconductor material. （２）　　前記加熱処理におけるエネルギー源として、
熱線紫外線、放射線、レーザー光或いは電子ビームを使
用したことを特徴とする特許請求の範囲ｖＩｌ項記載の
シリコン系半導体材料の再結晶方法。(2) As an energy source in the heat treatment,
A method for recrystallizing a silicon-based semiconductor material according to claim 11, characterized in that hot ultraviolet rays, radiation, laser light, or electron beams are used. （３）　　ｉｉｌ記シリコン系半導体を単結晶化若しく
は微結晶化させる過程に於で、シリコン系半導体中に水
素、弗素を含有させることを特徴とする前記特許請求の
範囲第１項記載の多結晶シリコンの製造方法。(3) The polycrystal according to claim 1, wherein hydrogen and fluorine are contained in the silicon-based semiconductor in the process of single-crystallizing or microcrystallizing the silicon-based semiconductor (iii). Method of manufacturing silicon. （４）　　前記シリコン系半導体を単結晶化若しくは微
結晶化させる過程に於て、Ａｒ，Ｊ，Ｃ。 Ｎ，ガス雰囲気中で処理することを特徴とする前記特許
請求の範囲第１項記載のシリコン系半導体材料の再結晶
方法。(4) Ar, J, and C in the process of single-crystallizing or microcrystalizing the silicon-based semiconductor. A method for recrystallizing a silicon-based semiconductor material according to claim 1, characterized in that the process is carried out in an N, gas atmosphere. （５）　　前記単結晶化若しくは微結晶化させる過程に
於で，ｎ形あるいはｐ形導電形を付与するドープ物質を
加えることを特徴とする前記特許請求の範囲第１項記載
のシリコン系半導体材料の再結晶方法。(5) The silicon-based semiconductor material according to claim 1, wherein a doping substance imparting n-type or p-type conductivity is added during the single crystallization or microcrystallization process. Recrystallization method.
JP57065827A 1982-04-20 1982-04-20 Recrystallizing method of silicon family semiconductor material Pending JPS58182816A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57065827A JPS58182816A (en) 1982-04-20 1982-04-20 Recrystallizing method of silicon family semiconductor material

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57065827A JPS58182816A (en) 1982-04-20 1982-04-20 Recrystallizing method of silicon family semiconductor material

Publications (1)

Publication Number Publication Date
JPS58182816A true JPS58182816A (en) 1983-10-25

Family

ID=13298243

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57065827A Pending JPS58182816A (en) 1982-04-20 1982-04-20 Recrystallizing method of silicon family semiconductor material

Country Status (1)

Country Link
JP (1) JPS58182816A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60109282A (en) * 1983-11-17 1985-06-14 Seiko Epson Corp Semiconductor device
JPS60245124A (en) * 1984-05-18 1985-12-04 Sony Corp Manufacture of semiconductor device
JPH01128572A (en) * 1987-11-13 1989-05-22 Nippon Telegr & Teleph Corp <Ntt> Thin film transistor and manufacture thereof
JPH07147259A (en) * 1994-07-11 1995-06-06 Sony Corp Manufacture of thin film transistor
JPH08264527A (en) * 1996-04-05 1996-10-11 Semiconductor Energy Lab Co Ltd Fabricaiton of semiconductor device
US6607947B1 (en) 1990-05-29 2003-08-19 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device with fluorinated layer for blocking alkali ions

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5623748A (en) * 1979-08-05 1981-03-06 Shunpei Yamazaki Manufacture of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5623748A (en) * 1979-08-05 1981-03-06 Shunpei Yamazaki Manufacture of semiconductor device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60109282A (en) * 1983-11-17 1985-06-14 Seiko Epson Corp Semiconductor device
JPS60245124A (en) * 1984-05-18 1985-12-04 Sony Corp Manufacture of semiconductor device
JPH01128572A (en) * 1987-11-13 1989-05-22 Nippon Telegr & Teleph Corp <Ntt> Thin film transistor and manufacture thereof
US6607947B1 (en) 1990-05-29 2003-08-19 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device with fluorinated layer for blocking alkali ions
US7355202B2 (en) 1990-05-29 2008-04-08 Semiconductor Energy Co., Ltd. Thin-film transistor
JPH07147259A (en) * 1994-07-11 1995-06-06 Sony Corp Manufacture of thin film transistor
JPH08264527A (en) * 1996-04-05 1996-10-11 Semiconductor Energy Lab Co Ltd Fabricaiton of semiconductor device

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