JPH11145484A - Manufacture of thin-film transistor - Google Patents

Manufacture of thin-film transistor

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Publication number
JPH11145484A
JPH11145484A JP25243998A JP25243998A JPH11145484A JP H11145484 A JPH11145484 A JP H11145484A JP 25243998 A JP25243998 A JP 25243998A JP 25243998 A JP25243998 A JP 25243998A JP H11145484 A JPH11145484 A JP H11145484A
Authority
JP
Japan
Prior art keywords
thin film
semiconductor thin
amorphous
polycrystalline semiconductor
temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25243998A
Other languages
Japanese (ja)
Inventor
Takashi Noguchi
隆 野口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP25243998A priority Critical patent/JPH11145484A/en
Publication of JPH11145484A publication Critical patent/JPH11145484A/en
Pending legal-status Critical Current

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  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a thin-film transistor on which electric characteristics can be improved by reducing the grain boundary trap in a polycrystalline semiconductor thin film. SOLUTION: An SiO2 insulating film 2 of about 1,000 Å in thickness is formed on a substrate 1 as an insulated substrate, and a polycrystalline silicon film 3 is deposited thereon in a thickness of 400 Å using a CVD method (chemical vapor deposition) at a temperature of 610 deg.C, for example. Then, silicon ions (Si <+> ) of 1×10<14> /cm<2> in dosage is made into an amorphous state and is (low temperature annealed at 600 deg.C for 40 hours (low temperature annealing). Moreover, the annealing is stopped at the state, wherein crystallization of the polycrystalline silicon film 3 is not saturated. Then, the material is heated up at a temperature between the melting point temperature of amorphous silicon and the melting point temperature of single-crystal silicon by projecting an excimer laser of 220 mj/cm<2> , an amorphous part 3A is formed, it is changed into a single-crystal part 3B, and a polycrystalline silicon film 3 having large grain diameter of 0.02 μm is formed.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、多結晶半導体薄膜
を能動層に有する薄膜トランジスタの製造方法に関す
る。
The present invention relates to a method for manufacturing a thin film transistor having a polycrystalline semiconductor thin film in an active layer.

【0002】[0002]

【従来の技術】近年、液晶ディスプレイ,LSI等に非
晶質(アモルファス)シリコンが盛んに用いられてい
る。この非晶質シリコンを用いたデバイスとしては、薄
膜トランジスタ(TFT)がある。
2. Description of the Related Art In recent years, amorphous silicon has been actively used in liquid crystal displays, LSIs and the like. As a device using this amorphous silicon, there is a thin film transistor (TFT).

【0003】また、このような薄膜トランジスタを形成
する半導体薄膜の形成方法としては、特願昭61−78
120号公報記載に係る技術が知られている。この従来
技術は、絶縁基体上の薄膜半導体層にレーザを照射して
溶融した後、冷却固化してなる薄膜単結晶を形成するに
際し、レーザ照射の前工程で熱処理を施して半導体層の
半導体の粒径を均一にするようにしたものである。
A method of forming a semiconductor thin film for forming such a thin film transistor is disclosed in Japanese Patent Application No. 61-78.
A technique according to Japanese Patent Publication No. 120 is known. In this prior art, a thin film semiconductor layer on an insulating substrate is irradiated with a laser and melted, and then cooled and solidified to form a thin film single crystal. The particle size is made uniform.

【0004】さらに最近では、液晶ディスプレイ,LS
I等において移動度の向上が期待されており、このため
高移動度が期待される多結晶シリコン薄膜の研究が盛ん
になっている。
More recently, liquid crystal displays, LS
For example, polycrystalline silicon thin films, which are expected to have high mobility, have been actively studied.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、多結晶
シリコン薄膜を用いて薄膜トランジスタを形成する場
合、粒界にトラップが生じ、このトラップ密度が大きく
なる問題点がある。
However, when a thin film transistor is formed using a polycrystalline silicon thin film, traps are generated at grain boundaries, and the trap density is increased.

【0006】斯るトラップ密度(Nt)が増大した場
合、以下の式により、 S〜kT/q・ln10・(1+qNt/Cox)…(1) S:電圧のスイング値 q:電荷 Cox:絶縁膜容量 μ〜μ0・exp(−ΔE/kT)…(2) μ:移動度 ΔE:グレインバンダリーを乗り越えるためのエネルギ
ー μ0∝L…(3) L:粒径 ΔE∝Nt 2…(4) Jr=(qNtkTπ)δvthi/2WR(VR)…(5) (pn
接合) J:電流密度 Ni:真性キャリア密度 VR:逆バイアス 移動度μが小さくなると共に、電圧のスイング値が大き
く、また、リーク電流が大きくなるという問題点があ
る。特に、多結晶シリコンの粒界部は、微細な非晶質と
してとらえることもでき、ダングリングボンドが存在
し、トラップ密度が大きいといえる。
When the trap density (N t ) increases, the following equation is used: S〜kT / q · ln10 · (1 + qN t / C ox ) (1) S: voltage swing value q: electric charge C ox : insulating film capacity μ to μ 0 · exp (−ΔE / kT) (2) μ: mobility ΔE: energy for overcoming the grain boundary μ 0 ∝L (3) L: particle size ΔE∝N t 2 ... (4) J r = (qN t kTπ) δv th n i / 2W R (V R) ... (5) (pn
Junction) J: current density N i: the intrinsic carrier density V R: with reverse bias mobility μ is small, a large swing of the voltage, also has a problem that the leakage current increases. In particular, the grain boundary portion of polycrystalline silicon can be regarded as fine amorphous, and it can be said that dangling bonds exist and the trap density is high.

【0007】本発明は、このような従来の問題点に着目
して創案されたものであって、粒界のトラップ密度を減
少させて、電気的特性を高めた多結晶半導体薄膜を能動
層に有する、薄膜トランジスタの製造方法を得んとする
ものである。
The present invention has been made in view of such a conventional problem, and a polycrystalline semiconductor thin film having improved electrical characteristics by reducing the trap density of grain boundaries is used as an active layer. And a method of manufacturing a thin film transistor.

【0008】[0008]

【課題を解決するための手段】(1)絶縁基板上に多結
晶半導体薄膜を形成する工程と、少なくとも前記多結晶
半導体薄膜を構成する結晶の粒界を溶融する一方、前記
多結晶半導体薄膜の厚さを変えないアニール処理を前記
多結晶半導体薄膜に施す工程と、前記アニール処理が施
された多結晶半導体薄膜を能動層に有する薄膜トランジ
スタを形成する工程とを含むことを特徴としている。
(1) A step of forming a polycrystalline semiconductor thin film on an insulating substrate, and melting at least grain boundaries of crystals constituting the polycrystalline semiconductor thin film, The method is characterized by including a step of performing an annealing process on the polycrystalline semiconductor thin film without changing the thickness, and a process of forming a thin film transistor having the polycrystalline semiconductor thin film subjected to the annealing process in an active layer.

【0009】また前記多結晶半導体薄膜が、化学的気相
成長法によって堆積された薄膜であることを特徴とし、
前記多結晶半導体薄膜が、前記絶縁基板上に非晶質半導
体薄膜を形成し、この非晶質半導体薄膜に結晶化が飽和
しない程度のアニールを施すことによって一部に非晶質
部を残して結晶化した領域を含む多結晶半導体薄膜であ
ることを特徴とし、前記アニール処理工程が、前記非晶
質部を溶融する工程であることを特徴としている。
Further, the polycrystalline semiconductor thin film is a thin film deposited by a chemical vapor deposition method,
The polycrystalline semiconductor thin film forms an amorphous semiconductor thin film on the insulating substrate, and anneals the amorphous semiconductor thin film to such an extent that crystallization is not saturated, leaving an amorphous portion in part. It is a polycrystalline semiconductor thin film including a crystallized region, and the annealing step is a step of melting the amorphous portion.

【0010】(2)多結晶半導体薄膜の粒界や微小欠陥
は、当該半導体の非晶質状態での融点以上で且つその半
導体の単結晶状態での融点未満の温度で熱処理すること
により、粒界等のみを溶融し、不対原子層を減少させて
トラップ密度を小さくして薄膜の電気的特性を高める。
このため、多結晶半導体薄膜の厚さの変化はなく平坦性
を維持することが可能となる。
(2) The grain boundaries and minute defects of the polycrystalline semiconductor thin film are formed by heat treatment at a temperature higher than the melting point of the semiconductor in an amorphous state and lower than the melting point of the semiconductor in a single crystal state. Only the boundaries are melted, the unpaired atomic layer is reduced, the trap density is reduced, and the electrical properties of the thin film are improved.
Therefore, the thickness of the polycrystalline semiconductor thin film does not change and flatness can be maintained.

【0011】[0011]

【発明の実施の形態】以下、図面を参照しながら本発明
に係る薄膜トランジスタの製造方法の一実施形態例を説
明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for manufacturing a thin film transistor according to the present invention will be described below with reference to the drawings.

【0012】(第1実施形態例)先ず、図1に示すよう
に、絶縁基体としての例えば耐熱ガラスより成る基板1
上に1000Å程度の膜厚のSiO2絶縁膜2を被着形
成し、さらに、SiO2絶縁膜2上に、多結晶シリコン
膜3を、例えば温度610℃のCVD法(気相成長法)
で400Åの厚さに堆積させる。
(First Embodiment) First, as shown in FIG. 1, a substrate 1 made of, for example, heat-resistant glass is used as an insulating base.
An SiO 2 insulating film 2 having a thickness of about 1000 ° is formed thereon, and a polycrystalline silicon film 3 is further formed on the SiO 2 insulating film 2 by, for example, a CVD method (vapor phase growth method) at a temperature of 610 ° C.
To a thickness of 400 °.

【0013】次に、多結晶シリコン膜3にエキシマレー
ザを照射温度が1300℃程度となるよう例えば220
mJ/cm2で照射して、多結晶シリコンの粒界のみを
溶融させる。かかるエキシマレーザの照射を行なった後
の多結晶シリコン膜3の厚さは、400Åで変化はみら
れない。
Next, the polycrystalline silicon film 3 is irradiated with an excimer laser at a temperature of about 1300.degree.
Irradiation at mJ / cm 2 melts only the grain boundaries of polycrystalline silicon. The thickness of the polycrystalline silicon film 3 after the irradiation with the excimer laser does not change at 400 °.

【0014】なお、上記エキシマレーザの照射温度は、
非晶質シリコンの融点温度(1100℃)よりも高く単
結晶シリコンの融点温度(1415℃)よりも低い範囲
で設定可能である。
The irradiation temperature of the excimer laser is:
It can be set within a range higher than the melting point temperature of amorphous silicon (1100 ° C.) and lower than the melting point temperature of single crystal silicon (1415 ° C.).

【0015】(第2実施形態例)本実施形態例は、先
ず、上記第1の実施形態例と同様に基板1上にSiO2
絶縁膜2,多結晶シリコン膜3を順次形成した後、図2
(a)に示すようにシリコンイオン(Si +)をドーズ量1
×1014/cm2でイオン注入し、多結晶シリコン膜3
を非晶質化させ、600℃で40時間のアニール(低温
アニール)を行なう。なお、このアニールは、多結晶シ
リコン膜3の結晶化が飽和しない状態で停止する。
(Second Embodiment) In the present embodiment, first, as in the first embodiment, SiO 2 is
After sequentially forming an insulating film 2 and a polycrystalline silicon film 3, FIG.
As shown in (a), the dose of silicon ion (S i + ) is 1
Ion implantation is performed at × 10 14 / cm 2 to form a polycrystalline silicon film 3.
Is made amorphous, and annealing (low-temperature annealing) is performed at 600 ° C. for 40 hours. This annealing is stopped in a state where the crystallization of the polycrystalline silicon film 3 is not saturated.

【0016】図2(b)は、多結晶シリコン膜3が上記
工程により非晶質化した非晶質部3Aと結晶化した単結
晶部3Bに変った断面状態を示しており、図3はその平
面である。
FIG. 2B shows a cross-sectional state in which the polycrystalline silicon film 3 has been changed into an amorphous portion 3A which has been made amorphous by the above process and a single crystal portion 3B which has been crystallized. That plane.

【0017】次に、図2(c)のようにエキシマレーザ
を220mJ/cm2で照射し、上記第1実施形態例と
同様に非晶質シリコンの融点温度と単結晶シリコンの融
点温度との間の温度で加熱することにより、非晶質部3
Aを溶融して単結晶部3Bに変え、粒径の大きい(〜
0.02μm)多結晶シリコン膜3が形成される。本実
施形態例においても多結晶シリコン膜3の厚さに変化は
なかった。
Next, as shown in FIG. 2C, an excimer laser is irradiated at 220 mJ / cm 2 , and the melting point temperature of the amorphous silicon and the melting point temperature of the single crystal silicon are changed in the same manner as in the first embodiment. By heating at an intermediate temperature, the amorphous portion 3
A is melted and changed to a single crystal part 3B, and the grain size is large (~
0.02 μm) A polycrystalline silicon film 3 is formed. Also in this embodiment, the thickness of the polycrystalline silicon film 3 did not change.

【0018】次に、このようにして形成された多結晶シ
リコン薄膜を用いて、チャネル長1μm,チャネル幅1
0μmとして薄膜トランジスタ(TFT)と、エキシマ
レーザの照射工程を省略したシリコン薄膜を用いて形成
した同様の構造の薄膜トランジスタの特性を図4〜図7
のグラフに基づいて比較する。
Next, a channel length of 1 μm and a channel width of 1
FIGS. 4 to 7 show the characteristics of a thin film transistor (TFT) having a thickness of 0 μm and a thin film transistor having a similar structure formed using a silicon thin film in which an excimer laser irradiation step is omitted.
Compare based on the graph.

【0019】図4に示すグラフは、エキシマレーザ照射
が施された薄膜トランジスタのゲート電圧とドレイン電
流との関係を示すものであり、図5のグラフに示す、エ
キシマレーザ照射をしない薄膜トランジスタとその特性
を比較すると、そのスイングが大きく立上り特性が良好
となっている。
The graph shown in FIG. 4 shows the relationship between the gate voltage and the drain current of the thin film transistor irradiated with the excimer laser. The graph shown in FIG. By comparison, the swing is large and the rising characteristics are good.

【0020】また、図6及び図7は、電子移動度とゲー
ト電圧との関係を示すグラフであり、図6に示すエキシ
マレーザ照射を施して成る薄膜トランジスタの電子移動
度は、図7に示すエキシマレーザ照射を施していない薄
膜トランジスタの電子移動度よりも著しく向上してい
る。
FIGS. 6 and 7 are graphs showing the relationship between the electron mobility and the gate voltage. The electron mobility of the thin film transistor irradiated with the excimer laser shown in FIG. 6 is shown in FIG. The electron mobility of the thin film transistor not subjected to laser irradiation is significantly improved.

【0021】上記した特性の比較から判るように、エキ
シマレーザを照射したことにより粒界となっている非晶
部分が溶融して、トラップ密度が減少し、各種特性が向
上したものと考えられる。
As can be seen from the comparison of the characteristics described above, it is considered that the amorphous portion serving as the grain boundary is melted by the irradiation of the excimer laser, the trap density is reduced, and various characteristics are improved.

【0022】以上、各実施形態例について説明したが、
本発明は、この他各種の変更が可能である。
The embodiments have been described above.
The present invention is capable of various other modifications.

【0023】例えば、上記各実施形態例においては、エ
キシマレーザを加熱手段として用いたが、加熱温度を非
晶質シリコンの融点以上で単結晶シリコンの融点未満の
温度とする加熱手段であれば他のものを用いてもよい。
For example, in each of the above embodiments, an excimer laser is used as the heating means. However, any other heating means can be used as long as the heating temperature is equal to or higher than the melting point of amorphous silicon and lower than the melting point of single crystal silicon. May be used.

【0024】[0024]

【発明の効果】以上の説明から明らかなように、本発明
に係る薄膜トランジスタの製造方法によれば、多結晶半
導体薄膜における粒界トラップを減少させて電気的特性
を向上させる効果がある。
As is apparent from the above description, the method of manufacturing a thin film transistor according to the present invention has the effect of reducing grain boundary traps in a polycrystalline semiconductor thin film and improving electrical characteristics.

【0025】また、粒界付近のみしか溶融しないため、
薄膜の平坦性を維持する効果がある。さらに、基本的結
晶粒径は維持されるため、粒径の制御性を良好にする効
果がある。
Further, since only the vicinity of the grain boundary is melted,
This has the effect of maintaining the flatness of the thin film. Further, since the basic crystal grain size is maintained, there is an effect of improving the controllability of the grain size.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る薄膜トランジスタの製造方法の第
1の実施形態例を示す断面図。
FIG. 1 is a sectional view showing a first embodiment of a method for manufacturing a thin film transistor according to the present invention.

【図2】本発明の第2実施形態例の断面図。FIG. 2 is a sectional view of a second embodiment of the present invention.

【図3】本発明の第2実施形態例の平面図。FIG. 3 is a plan view of a second embodiment of the present invention.

【図4】エキシマレーザを照射した薄膜を用いたトラン
ジスタのスイングを示すグラフ。
FIG. 4 is a graph showing a swing of a transistor using a thin film irradiated with an excimer laser.

【図5】エキシマレーザを照射しない薄膜を用いたトラ
ンジスタのスイングを示すグラフ。
FIG. 5 is a graph showing a swing of a transistor using a thin film which is not irradiated with an excimer laser.

【図6】エキシマレーザを照射した薄膜を用いたトラン
ジスタの移動度を示すグラフ。
FIG. 6 is a graph showing mobility of a transistor using a thin film irradiated with an excimer laser.

【図7】エキシマレーザを照射しない薄膜を用いたトラ
ンジスタの移動度を示すグラフ。
FIG. 7 is a graph showing the mobility of a transistor using a thin film which is not irradiated with an excimer laser.

【符号の説明】[Explanation of symbols]

3…多結晶シリコン膜、3A…非晶質部、3B…単結晶
部。
3 ... polycrystalline silicon film, 3A ... amorphous part, 3B ... single crystal part.

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 絶縁基板上に多結晶半導体薄膜を形成す
る工程と、 少なくとも前記多結晶半導体薄膜を構成する結晶の粒界
を溶融する一方、前記多結晶半導体薄膜の厚さを変えな
いアニール処理を前記多結晶半導体薄膜に施す工程と、 前記アニール処理が施された多結晶半導体薄膜を能動層
に有する薄膜トランジスタを形成する工程とを含む薄膜
トランジスタの製造方法。
1. A step of forming a polycrystalline semiconductor thin film on an insulating substrate, and an annealing treatment for melting at least grain boundaries of crystals constituting the polycrystalline semiconductor thin film while not changing the thickness of the polycrystalline semiconductor thin film To the polycrystalline semiconductor thin film, and a step of forming a thin film transistor having the annealed polycrystalline semiconductor thin film in an active layer.
【請求項2】 前記多結晶半導体薄膜が、化学的気相成
長法によって堆積された薄膜であることを特徴とする請
求項1に記載の薄膜トランジスタの製造方法。
2. The method according to claim 1, wherein the polycrystalline semiconductor thin film is a thin film deposited by a chemical vapor deposition method.
【請求項3】 前記多結晶半導体薄膜が、前記絶縁基板
上に非晶質半導体薄膜を形成し、この非晶質半導体薄膜
に結晶化が飽和しない程度のアニールを施すことによっ
て一部に非晶質部を残して結晶化した領域を含む多結晶
半導体薄膜であることを特徴とする請求項1に記載の薄
膜トランジスタの製造方法。
3. The polycrystalline semiconductor thin film is partially amorphous by forming an amorphous semiconductor thin film on the insulating substrate and annealing the amorphous semiconductor thin film to such an extent that crystallization is not saturated. The method according to claim 1, wherein the thin film is a polycrystalline semiconductor thin film including a crystallized region while leaving a quality part.
【請求項4】 前記アニール処理工程が、前記非晶質部
を溶融する工程であることを特徴とする請求項3に記載
の薄膜トランジスタの製造方法。
4. The method according to claim 3, wherein the annealing is a step of melting the amorphous portion.
JP25243998A 1989-11-16 1998-09-07 Manufacture of thin-film transistor Pending JPH11145484A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25243998A JPH11145484A (en) 1989-11-16 1998-09-07 Manufacture of thin-film transistor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP29791489A JP3287834B2 (en) 1989-11-16 1989-11-16 Heat treatment method for polycrystalline semiconductor thin film
JP25243998A JPH11145484A (en) 1989-11-16 1998-09-07 Manufacture of thin-film transistor

Related Parent Applications (1)

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JP2004186199A (en) * 2002-11-29 2004-07-02 Canon Inc Method of manufacturing crystalline thin film
US6828178B2 (en) * 2001-07-18 2004-12-07 Advanced Lcd Technologies Development Center Co., Ltd. Thin film semiconductor device having arrayed configuration of semiconductor crystals and a method for producing it

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JPH09218425A (en) * 1996-02-09 1997-08-19 Toshiba Electron Eng Corp Liquid crystal display device and its production
JP4098377B2 (en) * 1996-09-30 2008-06-11 株式会社東芝 Method for manufacturing polycrystalline semiconductor film
JPH11219133A (en) * 1998-02-02 1999-08-10 Tdk Corp Image display unit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6828178B2 (en) * 2001-07-18 2004-12-07 Advanced Lcd Technologies Development Center Co., Ltd. Thin film semiconductor device having arrayed configuration of semiconductor crystals and a method for producing it
JP2004186199A (en) * 2002-11-29 2004-07-02 Canon Inc Method of manufacturing crystalline thin film
JP4481562B2 (en) * 2002-11-29 2010-06-16 キヤノン株式会社 Method for producing crystalline thin film

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JPH03159116A (en) 1991-07-09
JP3287834B2 (en) 2002-06-04

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