JP2007122758A - Semiconductor memory device and read-out method therefor - Google Patents

Semiconductor memory device and read-out method therefor Download PDF

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JP2007122758A
JP2007122758A JP2005308963A JP2005308963A JP2007122758A JP 2007122758 A JP2007122758 A JP 2007122758A JP 2005308963 A JP2005308963 A JP 2005308963A JP 2005308963 A JP2005308963 A JP 2005308963A JP 2007122758 A JP2007122758 A JP 2007122758A
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read
bit line
memory cell
voltage
word line
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Takayuki Emori
孝之 江守
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Sony Corp
ソニー株式会社
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Abstract

A bit line voltage value at the time of data reading is sufficiently increased without adding an ion implantation step for adjusting a threshold voltage.
Each memory cell MCa includes a write transistor TW, a read transistor TR, and a capacitor C, and each of the write word line WWL and the read word line RWL is shared by a plurality of memory cells arranged in the row direction, A constant current driving means TD is provided between the bit line RBL and the reference potential GND at the time of reading from the semiconductor memory device in which the line RBL is shared by the plurality of memory cells MCs and MCu arranged in the column direction. The power supply voltage Vcc is applied to the read word line RWLs of the cell MCs, 0 [V] is applied to the read word line RWLu of the non-selected memory cell MCu, and the constant current driving means TD is turned on.
[Selection] Figure 2

Description

  The present invention relates to a reading method of a semiconductor memory device in which an element of a memory cell is constituted by two transistors and one capacitor, and a semiconductor memory device having a configuration to which the reading method can be applied.

  2. Description of the Related Art A semiconductor memory device having a two-transistor-one capacitor type memory cell that is a kind of so-called gain cell is known (see, for example, Patent Document 1 and Non-Patent Document 1).

FIG. 10 shows a circuit diagram of the memory cell described in Non-Patent Document 1.
The memory cell MCa shown in FIG. 10 includes a write transistor TW, a read transistor TR, and a capacitor C. The write transistor TW has a gate connected to the write word line WWL and one of a source and a drain connected to the write bit line WBL. The read transistor TR has a gate connected to the other of the source and drain of the write transistor TW, a source connected to the read bit line RBL, and a drain connected to a voltage supply line VSL for supplying the power supply voltage Vcc. The capacitor C has one electrode connected to the midpoint of connection between the read transistor TR and the write transistor TW, and the other electrode connected to the read word line RWL. One electrode of the capacitor C and the midpoint of connection between the read transistor TR and the write transistor TW connected to the capacitor C form a storage node SN of the memory cell MCa.

FIG. 11 is a circuit diagram of the memory cell described in Patent Document 1.
The memory cell MCb in FIG. 11 is different from the memory cell MCa in FIG. 10 in that the drain of the read transistor TR is connected to the read word line RWL.
As a result, the voltage supply line VSL is not required as shown in FIG. 10, and the arrangement space can be reduced. Further, since the capacitor C is connected between the gate and drain of the read transistor TR, the capacitor C can be formed by the overlap capacitance of the gate electrode with respect to the drain impurity region.

  Regarding data writing and reading, voltage control for various control lines is basically the same regardless of the type of memory cell, that is, whether it is the memory cell MCa or the memory cell MCb. Hereinafter, a data write operation and a data read operation in the memory cell MCa described in Non-Patent Document 1 will be described.

FIG. 12 shows a case where two memory cells MCa described in Non-Patent Document 1 are arranged in the column direction and share the read bit line RBL and the write bit line WBL. In this figure, one of the two memory cells is a selected memory cell MCs to be read from data, and the other is an unselected memory cell MCu that is not to be read from data.
13A to 13E are timing charts showing voltage changes in various lines during data writing and reading. This figure shows a case where data “1” and data “0” are written and read continuously.

As shown in FIG. 13A, in writing data “1”, a high level voltage, for example, 0.9 [V] is set to the write bit line WBL. Further, the voltage of the selected write word line WWLs (see FIG. 12) of the selected memory cell MCs is changed from 0 [V] to the power supply voltage Vcc at the timing when the bit line voltage is stabilized as shown in FIG. For example, it is raised to 1.8 [V].
Accordingly, the write transistor TW in FIG. 12 is turned on, and the high level (0.9 [V]) voltage of the write bit line WBL is transferred to the storage node SN. Here, when the storage node potential is at the high level, the storage data “1” is stored.
Thereafter, when the voltage of the selected write word line WWLs and the voltage of the write bit line WBL are lowered from the high level to the low level, the writing of the data “1” is completed.

In the state before reading, the reading bit line RBL is discharged and the voltage is kept at 0 [V] floating.
In reading data “1”, the voltage of the selected read word line RWLs (see FIG. 12) of the selected memory cell MCs is changed from 0 [V] to the power supply voltage Vcc, for example, as shown in FIG. Start up to 1.8 [V]. As a result, the potential of the storage node SN is raised to a level higher than the threshold voltage Vt_tr of the read transistor TR via the capacitor C. As a result, the read transistor TR is turned on, and charges are supplied from the power supply voltage Vcc to the read bit line RBL via the read transistor TR in the on state. Since the read bit line RBL has been in a floating state of 0 [V] immediately before reading, the voltage of the read bit line RBL rises, for example, by about 0.2 to 0.5 [V].
This voltage increase is amplified by a sense amplifier (not shown) connected to the read bit line RBL and read as data “1”.
Thereafter, when the voltage of the selected read word line RWLs falls from the high level to the low level, the reading of the data “1” is completed.

  In writing data “0”, as shown in FIG. 13A, a low level voltage, for example, 0 [V] is set to the write bit line WBL. Thereafter, the voltage of the selected write word line WWLs is raised from 0 [V] to the power supply voltage Vcc as in the case of writing data “1”. As a result, the write transistor TW is turned on, and the set 0 [V] is transferred to the storage node SN.

  In reading data “0”, the voltage of the selected read word line RWLs is raised from 0 [V] to the power supply voltage Vcc. In reading this data “0”, the voltage of the storage node SN does not rise above the threshold voltage Vt_tr of the read transistor TR. Accordingly, the read transistor TR remains off, and the voltage of the read bit line RBL remains floating at 0 [V] as shown in FIG. 13E.

During the above write and read operation periods, the voltage of the unselected read word line RWLu (see FIG. 12) of the unselected memory cell MCu is at a low level, that is, 0 [V] as shown in FIG. ] Is retained.
For this reason, the read transistor TR in the non-selected memory cell MCu is not turned on.
JP 2001-93988 A "A New SOI DRAM Gain Cell for Mbit DRAM's, H. Shichijo et al., Extended Abstracts of the 16th Conference on Solid State Device and Materials, A-7-3, 1984, pp.265-268"

  However, in the non-selected memory cell MCu, particularly when the data “1” is held in the storage node SN, the storage node holding voltage is 0.9 [V], so that the read transistor TR is 0.9. A gate bias of about [V] is applied. Further, between the source and the drain of the read transistor TR, the maximum is the power supply voltage Vcc, and the minimum is the power supply voltage Vcc minus the bit line voltage 0.2 to 0.5 [V] at the time of reading “1”. A voltage exceeding V] is applied. For this reason, an off-leakage current from the power supply voltage Vcc flows into the read bit line RBL more or less via the non-selected memory cell MCu, and the voltage of the read bit line RBL rises due to off-leakage.

In general, this off-leakage current is negligibly small for each non-selected memory cell MCu, but a large number of non-selected memory cells MCu are connected to the read bit line RBL, and the integrated value of the off-leakage current becomes considerably large. Further, the integrated value of the off-leakage current changes according to the combination of data bits stored in a large number of non-selected memory cells MCu connected to the read bit line RBL.
The fluctuation of the off-leakage current value fluctuates the bit line voltage during reading. This voltage variation due to off-leakage becomes a relatively large noise for the true value of the bit line voltage difference at the time of data reading, that is, a voltage difference of 0.2 to 0.5 [V].

  For the above reasons, it is necessary to suppress as much as possible the off-leakage current of the read transistor TR of the unselected memory cell MCu connected to the same read bit line RBL as the selected memory cell MCs.

  For this reason, the threshold voltage Vt_tr of the read transistor TR is normally set higher by several hundreds [mV] than the high-level storage node voltage (0.9 [V] in the above example) when “1” data is held. Has been. For this reason, in the above example where the high-level storage node potential is 0.9 [V], the threshold voltage Vt_tr of the read transistor TR must be at least 1.0 [V] (first request). .

  On the other hand, in order to suppress the cell area by reducing the capacitance value of the capacitor C as much as possible, it is desirable that the high-level storage node voltage at the time of holding “1” data is as close to the power supply voltage Vcc as possible (second requirement). ).

However, if the threshold voltage of the transistors in the cell including the read transistor TR is set large based on the first requirement, the high-level storage node voltage at the time of holding “1” data cannot be increased too much. This is because in the above example, when the threshold voltage Vt_tw of the write transistor TW is 1.0 [V], which is the same as the threshold voltage Vt_tr of the read transistor TR, the voltage 0.9 [V] set on the write bit line WBL. Is stored only up to 0.8 [V] obtained by subtracting the threshold voltage Vt_tw of the write transistor TW, that is, 1.0 [V] from the write voltage (power supply voltage Vcc) of the selected write word line WWLs. Cannot write to node SN. This is contrary to the second requirement.
That is, the first request and the second request are inconsistent under the condition that the capacitance value of the capacitor C is made as small as possible to suppress the cell area.

  In order to solve this contradiction, it is necessary to set the threshold voltage Vt_tr of the read transistor TR higher than the threshold voltage Vt_tw of the write transistor TW.

However, this solution has the following disadvantages.
First, the number of ion implantation steps for controlling the threshold voltage Vt_tr of the read transistor TR increases, resulting in an increase in cost.
Second, since the threshold voltage Vt_tr of the read transistor TR is high, the potential appearing on the read bit line RBL at the time of reading data “1” is a fairly low voltage of 0.2 to 0.5 [V]. The bit line voltage of 0.2 to 0.5 [V] is too low in consideration of the noise margin for the voltage fluctuation caused by the off-leakage described above. In particular, as the input voltage of a standard sense amplifier (single-ended type, current mirror type), when the power supply voltage is 1.8 [V], the input voltage is sufficiently higher than the maximum value of the voltage fluctuation caused by the off-leakage 0.6 [V]. Since V] or more is required, if the threshold voltage Vt_tr of the read transistor TR is set high, a standard sense amplifier cannot be used.

  The problem to be solved by the present invention is to sufficiently increase the bit line voltage value at the time of data reading without adding an ion implantation step for adjusting the threshold voltage.

In a first read method of a semiconductor memory device according to the present invention, each memory cell constituting a memory cell array has a gate connected to a write word line, one of a source and a drain connected to a bit line, A write transistor having the other connected to the storage node, a read transistor having the gate connected to the storage node, one of the source and drain connected to the bit line, and the other of the source and drain connected to the voltage supply line And a capacitor connected between the storage node and the read word line, and each of the write word line and the read word line in the memory cell array is a plurality of memory cells arranged in a row direction. A semiconductor memory device shared and shared by a plurality of memory cells in which the bit lines are arranged in the column direction In the reading method, a constant current driving unit is provided between the bit line and a reference potential, and the selected memory cell to be read is read out of the plurality of memory cells sharing the bit line and arranged in the column direction. A power supply voltage is applied to the word line, and 0 [V] is applied to the read word line of the non-selected memory cell that is not the read target, thereby turning on the constant current driving means.
In this reading method, preferably, auxiliary means is provided for each bit line, and the auxiliary means is operated during reading to assist charging of the bit line.

The operation in this reading method will be described.
In this reading method, the constant current driving means connected to each bit line is turned on at the time of data reading. Therefore, when the high level is held in the storage node of the selected memory cell to be read, the bit line is charged through the selected memory cell, while the constant current driving unit draws current from the bit line. For example, when the constant current driving means is a driver transistor that is driven with a constant gate bias, the driver transistor operates as a constant current source, and in a plurality of memory cells connected to the same bit line as the constant current driving means. The read transistor functions as a load. Therefore, at the time of data reading, a source follower output circuit is formed by the constant current driving means and a plurality of read transistors as loads.

In such a circuit, the point where the characteristic curve of the constant current driving means and the characteristic curve (load curve) of the transistor serving as a load intersect is the current driving capability of the constant current driving means and the size of the load (multiple readings). This is a stable operating point determined by the overall current driving capability of the transistor) and the load capacity of the bit line. Therefore, when considering the case where the magnitude of the load fluctuates, the read transistor is self-biased to return the operating point to the stable point.
Specifically, considering the case where the load current is too large in light of the current value corresponding to the stable point, the voltage between the source and the gate of the read transistor is reduced by the amount corresponding to the increase in the bit line potential, and the read transistor The load current flowing through is reduced. On the contrary, when the load current is too small in light of the current value corresponding to the stable point, the voltage between the source and gate of the read transistor increases as the bit line potential decreases, and the read The load current flowing through the transistor increases.

  In such a circuit that is self-biased and controlled to a stable operating point, stable operation is possible even when the threshold voltage of the reading transistor is small. The bit line voltage corresponding to a stable operating point takes a voltage value sufficiently higher than 0 [V], which is mainly determined by the division ratio between the on-resistance and the load resistance of the constant current driving means.

In a second read method of the semiconductor memory device according to the present invention, each memory cell constituting the memory cell array has a gate connected to a write word line, one of a source and a drain connected to a bit line, A write transistor with the other connected to the storage node, a read transistor with the gate connected to the storage node, one of the source and drain connected to the bit line, and the other of the source and drain connected to the read word line And a capacitor connected between the storage node and the read word line, and a plurality of memory cells in which the write word line and the read word line are arranged in a row direction in the memory cell array. And the bit line is shared by a plurality of memory cells arranged in the column direction. A reading method of a memory device, comprising: a constant current driving unit provided between the bit line and a reference potential; and a selected memory cell to be read among the plurality of memory cells sharing the bit line and arranged in a column direction A power supply voltage is applied to the read word line, an intermediate voltage having a value between the power supply voltage and 0 [V] is applied to the read word line of the non-selected memory cell that is not the read target, and the constant current driving means is turned on. Let
In this read method, the intermediate voltage is preferably set to a value equal to or higher than the maximum value of the voltage read to the bit line.
Preferably, auxiliary means is provided for each bit line, and the auxiliary means is operated during reading to assist charging of the bit line.

The operation of the second reading method will be described.
One of the differences between the second read method and the first read method described above is the configuration of the memory cell.
More specifically, the memory cell premised on the second read method is that a read word line is connected to the drain of the read transistor.

  The read word line is normally controlled to a high level only during reading. For this reason, in a non-selected memory cell, it is a normal way to maintain the read word line at a low level.

Another feature of the second read method is that the read word line is controlled to an intermediate voltage. A preferable intermediate voltage in the present invention is set to a value equal to or higher than the maximum value of the voltage read to the bit line. In particular, in this case, even if high level data is read out to the bit line and the potential becomes high level, the read transistor may be used to charge the bit line voltage, but the bit line voltage is reduced. There is no discharge.
Therefore, there is no path for sucking current from the bit line except for the constant current driving means. For this reason, the self-bias operation of the read transistor is stabilized by a constant drive current by the constant current drive means.

  In the semiconductor memory device according to the present invention, each memory cell constituting the memory cell array has a gate connected to the write word line, one of the source and drain connected to the bit line, and the other of the source and drain connected to the storage node. A write transistor, a gate connected to the storage node, one of a source and a drain connected to a bit line, and the other of the source and the drain connected to a voltage supply line, and the storage node A capacitor connected between the read word line, and each of the write word line and the read word line in the memory cell array is shared by a plurality of memory cells arranged in a row direction, and the bit line Is shared by a plurality of memory cells arranged in the column direction, and a constant current drive is provided between the bit line and a reference potential. Means are connected, an auxiliary means for each of the bit lines.

  In another semiconductor memory device according to the present invention, each memory cell constituting a memory cell array has a gate connected to a write word line, one of a source and a drain connected to a bit line, and the other of the source and the drain connected to a storage node. A write transistor connected to the storage node, a gate connected to the storage node, one of a source and a drain connected to a bit line, and the other of the source and the drain connected to a read word line, and the storage A capacitor connected between the node and the read word line, and each of the write word line and the read word line is shared by a plurality of memory cells arranged in a row direction in the memory cell array, The bit line is shared by a plurality of memory cells arranged in the column direction, and the bit line and a reference potential Constant current drive means is connected between, an auxiliary means for each of the bit lines.

  According to the present invention, there is an advantage that the bit line voltage value at the time of data reading can be sufficiently increased without adding an ion implantation step for adjusting the threshold voltage.

[First Embodiment]
FIG. 1 is a block diagram showing a memory cell array and main parts of a peripheral circuit including a sense amplifier, word line and bit line drive circuits in the semiconductor memory device according to the first embodiment.

  As shown in the figure, the memory cell array is composed of m × n (m, n: any natural number) memory cells MC11, MC12,..., MC21,. In the memory cell array, each memory cell in the same row is connected to the same write word line WWLj (j = 1, 2,..., N) and read word line RWLj, and each memory cell in the same column is connected to the same write bit line WBLi (i = 1, 2,..., M) and the read bit line RBLi.

The n write word lines WWLj and the n read word lines RWLj in the memory cell array are connected to and driven by the word line drive circuit WLD.
The m write bit lines WBLi and the m read bit lines RBLi in the memory cell array are connected to and driven by the bit line driving circuit BLD.

A driver transistor TDi as a “constant current driving means” and a sense amplifier SAi are connected to the memory cells in each column.
The driver transistor TDi is an NMOS transistor having the same size and threshold value set in each column, and is connected between the corresponding read bit line RBLi and a reference voltage, for example, a ground voltage. The gates of the m driver transistors TDi are commonly connected to a drive control line DCL to which a driver voltage is applied. As will be described in detail later, this driver voltage is held at a high level during reading, and turns on the driver transistor TD.

  The sense amplifier SAi is a single-ended amplifier, and operates by receiving power supply from the high-level power line SPL and the low-level power line SNL. The sense amplifier SAi amplifies and outputs the voltage of the read bit line RBLi connected to the input side.

FIG. 2A shows two memory cells belonging to the same column in the memory cell array, a driver transistor TD, and a sense amplifier SA. In this figure, one of the two memory cells is a selected memory cell MCs to be read from data, and the other is an unselected memory cell MCu that is not to be read from data.
FIG. 2B shows an equivalent circuit showing the connection relationship between the total n read transistors TR and the driver transistors TD of the selected memory cells MCs and all the non-selected memory cells MCu arranged in the same column. .

Since the memory cell of the present embodiment has the same basic configuration as that of FIG. 10, the details of the configuration and the basic operation of the cell are omitted.
As shown in FIG. 2B, the read transistor TR of the selected memory cell MCs and the non-selected memory cell MCu (and other non-selected memory cells) include a voltage supply line VSL for supplying the power supply voltage Vcc and a read bit. It is connected in parallel with the line RBL. In addition, the voltage of the read bit line RBL connected to the source of each read transistor TR is output via the sense amplifier SA.
Accordingly, a source follower circuit is formed in which each read transistor TR is a load and the driver transistor TD is a driver (current source).

Next, the operation of the source follower circuit will be described.
Of the n read transistors TR serving as a load of the source follower circuit, the read transistor TR of the selected memory cell MCs is turned on or off according to the voltage (V1s or V0s) of the storage node SN corresponding to the stored data.
Here, the voltage V1s is a storage node voltage after being boosted by the selective read word line RWLs via the capacitor C when data “1” is stored. The voltage V0s is a storage node voltage after the same boosting when storing data “0”.
For this reason, the read transistor TR of the selected memory cell MCs supplies an on-current (read current) Ir having a different value depending on the stored data to the read bit line RBL.

  In the other (n−1) non-selected memory cells MCu, the gate voltage (storage node voltage) of the read transistor TR is not boosted at the time of reading. However, the read transistor TR of the non-selected memory cell MCu causes a leakage current Ioff corresponding to the storage node voltage value (V1u or V0u) corresponding to the storage data to flow somewhat to the read bit line RBL. In the read bit line RBL, an addition current of the read current Ir and the leak current Ioff flows, and this addition current flows from the driver transistor TD to the ground voltage.

As will be described in detail later, when “1” data is read, the load of the source follower circuit is determined by the read transistor resistance of the selected memory cell MCs, and when “0” data is read, “1” data is stored. The load of the source follower circuit is determined by the read transistor resistance of the selected memory cell MCu. Then, the DC level of the voltage (read voltage) of the read bit line RBL is increased to a value mainly determined by the voltage division ratio between any one of the loads (resistance) and the resistance (on resistance) of the driver transistor.
Therefore, it is possible to obtain a read voltage at a level suitable as an input voltage for a standard sense amplifier such as a single-ended sense amplifier.

FIGS. 3A to 3F are timing charts showing voltage changes in various lines during data writing and reading. This figure shows a case where data “1” and data “0” are written and read continuously.
Hereinafter, the operation of the semiconductor memory device according to the present embodiment will be described with reference to FIG. In the following description, FIG. 2 will be referred to as appropriate.

As shown in FIG. 3A, in writing data “1”, a high level voltage, for example, 0.8 [V] is set to the write bit line WBL. Further, as shown in FIG. 3B, the voltage of the selected write word line WWLs (see FIG. 2) of the selected memory cell MCs is changed from 0 [V] to the power supply voltage Vcc, for example, 1 at the timing when the bit line voltage is stabilized. Raise to 8V.
As a result, the write transistor TW shown in FIG. 2 is turned on, and the high-level (0.8 [V]) voltage VH of the write bit line WBL is transferred to the storage node SN. Here, when the storage node potential is at the high level, the storage data “1” is stored.
Thereafter, when the voltage of the selected write word line WWLs and the voltage of the write bit line WBL are lowered from the high level to the low level, the writing of the data “1” is completed.

In the state before reading, the reading bit line RBL is discharged and the voltage is kept at 0 [V] floating.
In reading data “1”, the voltage of the selected read word line RWLs (see FIG. 2) of the selected memory cell MCs is changed from 0 [V] to the power supply voltage Vcc, for example 1.8, as shown in FIG. Launch in [V]. At substantially the same time, as shown in FIG. 3F, the driver voltage VD supplied to the gate of the driver transistor TD (see FIG. 2) is changed from 0 [V] to the voltage at which the driver transistor TD is turned on. For example, it is raised to 0.5 [V].

As a result, the driver transistor TD is turned on and the source follower circuit shown in FIG. 2B becomes operable, and the “1” data storage node voltage is set via the capacitor C in the selected memory cell MCs. It rises higher than the threshold voltage Vt_tr of the reading transistor TR.
As a result, the read transistor TR is turned on, and charges are supplied from the power supply voltage Vcc to the read bit line RBL via the read transistor TR in the on state.

  In this embodiment, the threshold voltage Vt_tr of the read transistor TR in the selected memory cell MCs is set to 0.4 [V], which is the same as the threshold voltage Vt_tw of the write transistor TW. For this reason, as compared with the case where only the threshold voltage of the read transistor TR is set higher by additional ion implantation, more current can flow and the bit line charging ability is improved. Compared to the case where there is no driver transistor TD, the bit line voltage is amplified by the source follower circuit and rises to a higher level. As a result, as shown in FIG. 3F, the voltage after reading “1” data on the read bit line RBL changes from 0 [V] to, for example, “0.85 [V]”.

This voltage increase is amplified by a sense amplifier (not shown) connected to the read bit line RBL and read as data “1”.
Thereafter, when the voltage of the selected read word line RWLs falls from the high level to the low level, the reading of the data “1” is completed.

  In writing data “0”, as shown in FIG. 3A, a low-level voltage VL, for example, 0 [V] is set to the write bit line WBL. Thereafter, the voltage of the selected write word line WWLs is raised from 0 [V] to the power supply voltage Vcc as in the case of writing data “1”. As a result, the write transistor TW is turned on, and the set low-level voltage VL (= 0 [V]) is transferred to the storage node SN.

In the state before reading, the reading bit line RBL is discharged and the voltage is kept at 0 [V] floating.
In reading data “0”, the voltage of the selected read word line RWLs (see FIG. 2) is raised from 0 [V] to the power supply voltage Vcc as shown in FIG. At substantially the same time, as shown in FIG. 3F, the driver voltage VD supplied to the gate of the driver transistor TD (see FIG. 2) is changed from 0 [V] to the voltage at which the driver transistor TD is turned on. For example, it is raised to 0.5 [V].

In reading this data “0”, the voltage of the storage node SN does not rise above the threshold voltage Vt_tr of the read transistor TR. Therefore, from this point of view, the read transistor TR remains off. However, the leakage current of the read transistor of the non-selected memory cell storing “1” data flows.
As a result, as shown in FIG. 3E, the voltage of the read bit line RBL rises to a smaller value, for example, 0.35 [V], when “1” data is read.

During the above write and read operation periods, as shown in FIG. 3D, the voltage of the non-selected read word line RWLu (see FIG. 2) of the non-selected memory cell MCu is held at a low level, that is, 0 [V]. Is done.
For this reason, the read transistor TR in the non-selected memory cell MCu is controlled to maintain the off state. However, as will be described later, it is not assumed that the read transistor TR of the unselected memory cell MCu is always turned off. That is, a slight on-current may flow through the read transistor TR depending on the logic of the stored data.

  Next, the storage node voltage in “1” data reading and “0” data reading will be described.

<For selected cells>
Since the power supply voltage Vcc is applied to the selected read word line RWLs in the selected memory cell MCs, the boosted potential V1s of the storage node SN holding the data “1” is expressed by the following equation (1-1). The Further, the boosted potential V0s of the storage node SN holding the data “0” is expressed by the following equation (1-2). In the following equations (1-1) and (1-2), the symbol “VH” represents the voltage of the storage node SN that holds the data “1” before boosting, and the symbol “CT” represents the storage node SN. Shows the total capacity connected.

[Equation 1]
V1s = VH + C / CT × Vcc (1-1)
V0s = 0 [V] + C / CT × Vcc
= C / CT x Vcc (1-2)

The symbol “C / CT” in the above expression is a coupling capacitance ratio at the time of boosting, and it is desirable that this value be large in terms of boosting, but if it is too large, the area of the capacitor C increases, which is not preferable.
As an example, it is assumed that the coupling capacitance ratio (C / CT) is set to a relatively small value of “0.3”. In this case, in the example shown in FIG. 3, using the power supply voltage Vcc = 1.8 [V] and “1” data storage node voltage VH = 0.8 [V] before boosting, When calculated, the boosted “1” data storage node voltage V1s = 1.34 [V]. Further, “0” data storage node voltage V0s after boosting becomes 0.54 [V].

<For non-selected cells>
In the unselected cell, 0 [V] is applied to the unselected read word line RWLu, so that the storage node voltage does not change from the voltage at the time of writing regardless of whether the data is “1” or “0”.
Therefore, the storage node voltage V1u of the non-selected memory cell holding the data “1” is expressed by the following equation (2-1). The storage node voltage V0u of the non-selected memory cell that holds the data “0” is expressed by the following equation (2-2).

[Equation 2]
V1u = VH (2-1)
V0u = 0 [V] (2-2)

As already described in the operation of the source follower circuit shown in FIG. 2B, n read transistors TR connected in parallel to the driver transistor TD serve as a load. The magnitude of the load varies depending on the four types of storage node voltages.
Therefore, the four types of load curves corresponding to the above four types of storage node voltages V1s, V0s, V1u, and V0u intersect the operating curve of the driver transistor TD, and each intersection can be an operating point.

FIG. 4 is a graph in which four types of load curves are superimposed on the drain voltage-current characteristics of the driver transistor.
In FIG. 4, the symbol “D” indicates a voltage-current characteristic curve (hereinafter referred to as driver) with the drain voltage of the driver transistor TD (ie, the read bit line voltage VRBL) as the horizontal axis and the drain current flowing through the driver transistor TD as the vertical axis. Curve). The symbol “L1s” indicates a load curve of the read transistor TR of the selected memory cell in which the storage node voltage V1s is set to the gate. Symbol “L0s” indicates a load curve of the read transistor TR of the selected memory cell in which the storage node voltage V0s is set to the gate. Symbol “L1u” indicates a load curve of the read transistor TR of the non-selected memory cell in which the storage node voltage V1u is set to the gate. The symbol “L0u” indicates a load curve of the read transistor TR of the non-selected memory cell in which the storage node voltage V0u is set to the gate.

First, the operating point at the time of reading “1” data will be described.
With respect to the selected memory cell in which data “1” is stored, the current values coincide at the intersection P1 between the driver curve D and the rightmost load curve L1s, and the read bit line voltage VRBL is stabilized. There is a stable point at each of the intersections P2 to P4 of the driver curve D and the other three load curves L1u, L0s, and L0u, but when reading “1” data at the rightmost stable point (intersection P1) The read bit line voltage VRBL1 is substantially determined. This is because the driver current and the load current match at the read bit line voltage VRBL1 at the rightmost stable point, and the left load current hardly flows.

Next, an operation point for reading “0” data will be described.
If only the selected memory cell storing data “0” is considered, the read bit line voltage VRBL is stabilized at the intersection P3 between the driver curve D and the third load curve L0s from the right. However, since the load curve L1u of the non-selected memory cell in which the data “1” is stored is usually on the right side, the maximum at the time of reading “0” data at the intersection of the load curve L1u and the driver curve D The read bit line voltage VRBL0 is effectively determined.

In the sense amplifier, the sense amplifier SA detects the difference between the read bit line voltage VRBL1 at the time of reading “1” data and the maximum read bit line voltage VRBL0 at the time of reading “0”, and discriminates the data. The voltage difference is designed to be several hundreds [mV] or more.
In the example of FIG. 3, the read bit line voltage VRBL1 = 0.85 [V] at the time of reading “1” data, and the maximum read bit line voltage VRBL0 = 0.35 [V] at the time of reading “0”. Yes, the voltage difference condition detectable by the sense amplifier SA is satisfied.

As a premise for setting the operating point as shown in FIG. 4, the driver curve D must be constant. In other words, it is desirable that the current path flowing out from the read bit line RBL is only a path via the driver transistor TD, and no other current outflow path is generated.
Therefore, regarding the applied voltage condition of the read transistor TR forming the load of the source follower circuit, the drain side voltage must be equal to or higher than the source side read bit line voltage. The reason is that if the drain voltage of the read transistor TR is lower than the read bit line voltage, the bit line current flows out through the path, and if the amount varies, the operating point fluctuates and stable operation cannot be performed. It is a factor.

  However, in this embodiment, since the power supply voltage Vcc is applied to the drain of the read transistor TR of the memory cell, there is no fear of such a current outflow path. In this respect, stable operation is possible.

In this embodiment, the driver transistor TD is provided to form a source follower circuit, and the read transistor serving as the load is turned on regardless of whether the stored data is “1” or “0”. It is assumed that
In particular, the operating point P2 at the time of reading “0” data is determined by the operating state of the reading transistor which is a load of the non-selected memory cell holding the “1” data. This operating point P2 is comprehensively determined by the current drive capability of the driver transistor TD, the number of “1” data holding non-selected memory cells MCu connected to the same read bit line RBL, the read bit line capacitance, and the like. Therefore, it is not always necessary that the read transistor TR of the non-selected memory cell MCu holding “1” data is turned off. For this reason, it is not necessary to increase the threshold voltage of only the read transistor TR in the memory cell.

In this regard, a more detailed operation will be described.
First, at the time of reading “0” data, if the number of read transistors in the non-selected memory cell holding “1” data is large and the read bit line voltage is going to rise from the standard value, the voltage between the gate and the source of each read transistor is increased. Since it becomes smaller, the current driving capability is lowered, and it works to suppress the rise of the read bit line voltage. Conversely, if the number of read transistors in the non-selected memory cell holding “1” data is small and the read bit line voltage is lowered, the voltage between the gate and the source of each read transistor increases, and the current driving capability is increased. It works to suppress a decrease in the read bit line voltage.
This operation is the same in the selected memory cell MCs at the time of reading “1” data.

As is clear from the above, in the source follower circuit, it is not necessary to always turn off the read transistor, and the operating point is self-biased so as to absorb the influence of the magnitude of the threshold voltage. Therefore, the influence of the threshold voltage of the read transistor on the operating point is small.
As a result, the threshold voltage of the read transistor does not need to be higher than that of other write transistors, and may be a standard value.

  In the source follower read, the read bit line voltage is controlled to a positive voltage mainly determined by the voltage division ratio between the on-resistance of the driver transistor serving as a constant current source and the resistance of the read transistor as a load. For this reason, the read bit line voltage VRBL1 at the time of reading “1” data can be set to a value higher by several hundreds [mV] than when the source follower read is not performed. As a result, it is possible to obtain a read bit line voltage having an appropriate value as an input voltage of a standard sense amplifier (single-end type, current mirror type). For example, the read bit line voltage VRBL1 at the time of reading “1” data can be 0.8 [V] or more when the power supply voltage is 1.8 [V].

In summary, in this embodiment, the threshold voltage of the read transistor can be a standard value. Therefore, it is not necessary to add an ion implantation process for controlling the threshold voltage.
Also, the read bit line voltage value can be a value suitable for the input voltage of a single-ended sense amplifier or a current mirror sense amplifier that is a standard sense amplifier.

[Second Embodiment]
First, the outline of the second embodiment will be described. In the second embodiment, the present invention is applied not to the memory cell MCa of FIG. 10 but to the memory cell MCb of FIG.
In the data read of the memory cell array composed of the memory cell MCb of FIG. 11, the power supply voltage Vcc is applied to the read word line RWL of the selected memory cell, and the intermediate voltage VM is applied to the read word line RWL of the unselected memory cell. The intermediate voltage VM is arbitrary as long as it is a voltage between the power supply voltage Vcc and a reference voltage (for example, the ground voltage 0 [V]). In the present embodiment, the intermediate voltage is assumed to be 0.4 to 0.6 times the power supply voltage Vcc.
Hereinafter, the circuit configuration and operation of the second embodiment will be described in order. FIG. 1 is also applied to the second embodiment.

FIG. 5A shows two memory cells belonging to the same column in the memory cell array, a driver transistor TD, and a sense amplifier SA. In this figure, one of the two memory cells is a selected memory cell MCs to be read from data, and the other is an unselected memory cell MCu that is not to be read from data.
FIG. 5B shows the connection relationship between the total n read transistors TR and the driver transistors TD of the selected memory cells MCs and all unselected memory cells MCu arranged in the same column by an equivalent circuit. .

  Since the memory cell of this embodiment has the same basic configuration as that of FIG. 11, the details of the configuration and the basic operation of the cell are omitted.

  FIG. 5B is different from FIG. 2B of the first embodiment in that the drain of the read transistor TR of the selected memory cell MCs is connected to the selected read word line RWLs that is controlled by the power supply voltage Vcc at the time of reading. On the other hand, the drain of the read transistor TR of the non-selected memory cell MCu is connected to the non-selected read word line RWLu controlled by the intermediate voltage VM at the time of reading.

  Other structures in FIG. 5B are the same as those in FIG. The basic operation of the source follower circuit is the same as that of the first embodiment except that the intermediate voltage VM is applied to the non-selected memory cell MCu instead of the power supply voltage Vcc at the time of reading. Therefore, the graph of FIG. 4 showing the relationship between the driver curve D and the load curves L1s to L0u can also be applied in this embodiment.

FIG. 6A to FIG. 6F are timing charts showing voltage changes in various lines during data writing and reading. This figure shows a case where data “1” and data “0” are written and read continuously.
The voltage control is different from that in FIG. 3 in reading “1” data and “0” data, in the case of FIG. 3D, the voltage of the unselected read word line RWLu was held at 0 [V]. However, in the case of this embodiment shown in FIG. 6D, when the selected read word line RWLs is raised to 1.8 [V], the non-selected read word line RWLu is supplied to, for example, 0.9 [V] at almost the same timing. The intermediate voltage VM is applied. Other voltage control is the same as in FIG.

  Next, the storage node voltage in “1” data reading and “0” data reading will be described.

<For selected cells>
With respect to the selected memory cell, the storage node voltage is boosted to a predetermined voltage from the voltage transferred to the storage node SN at the time of data writing, assuming that there is no attenuation due to the leakage current. This predetermined voltage is a voltage obtained by multiplying the power supply voltage Vcc applied to the selected read word line RWLs by the capacitance ratio (coupling capacitance ratio) of the capacitor C to the total capacitance CT.
The boosted storage node voltage is expressed by the same formulas (1-1) and (1-2) described in the first embodiment.

<For non-selected cells>
The storage node voltage of the unselected memory cell is not boosted in the first embodiment, but is boosted in the present embodiment.
In the non-selected cell, an intermediate voltage (eg, 0.9 [V]) is applied to the non-selected read word line RWLu, so that the voltage to be boosted is smaller than that of the selected memory cell.
The storage node voltage V1u of the non-selected memory cell holding the data “1” is expressed by the following equation (3-1). Further, the storage node voltage V0u of the non-selected memory cell holding the data “0” is expressed by the following equation (3-2).

[Equation 3]
V1s = VH + C / CT × VM (3-1)
V0s = 0 [V] + C / CT × VM
= C / CT x VM (3-2)

As described above, in the present embodiment, boosting is performed also in the non-selected memory cell MCu, so that the read transistor TR is generally easily turned on. As a result, in the example shown in FIG. 6E, the read bit line RBL at the time of reading “0” data has risen to 0.7 [V]. In the case of this example, the voltage difference between the read bit lines RBL at the time of reading “1” data and at the time of reading “0” data is slightly small at 0.15 [V].
However, this voltage difference can be made larger by optimizing the value of the intermediate voltage VM.

  Next, the reason why the intermediate voltage VM is applied in the cell configuration in which the read word line RWL is connected to the drain of the read transistor TR will be described.

As a premise for setting the operating point as shown in FIG. 4, the driver curve D must be constant. In other words, it is desirable that the current path flowing out from the read bit line RBL is only a path via the driver transistor TD, and no other current outflow path is generated.
Therefore, regarding the applied voltage condition of the read transistor TR forming the load of the source follower circuit, the drain side voltage must be equal to or higher than the source side read bit line voltage. The reason is that if the drain voltage of the read transistor TR is lower than the read bit line voltage, the bit line current flows out through the path, and if the amount varies, the operating point fluctuates and stable operation cannot be performed. It is a factor.

  In the present embodiment, such an outflow path of current is prevented by applying the intermediate voltage VM to the drain of the read transistor TR of the memory cell. In this respect, stable operation is possible.

In the present embodiment, as in the first embodiment, the driver transistor TD and the read transistor TR group form a source follower circuit when reading data.
In the source follower circuit, for the same reason as described in the first embodiment, it is not necessary to always turn off the reading transistor, and the operating point is self-biased so as to absorb the influence of the threshold voltage. Therefore, the influence of the threshold voltage of the read transistor on the operating point is small.
As a result, the threshold voltage of the read transistor does not need to be higher than that of other write transistors, and may be a standard value.

  In the source follower read, the read bit line voltage is controlled to a positive voltage mainly determined by the voltage division ratio between the on-resistance of the driver transistor serving as a constant current source and the resistance of the read transistor as a load. Therefore, the read bit line voltage VRBL1 (see FIG. 4) at the time of reading “1” data can be set to a value that is several hundreds [mV] higher than that in the case where the source follower read is not performed. As a result, it is possible to obtain a read bit line voltage having an appropriate value as an input voltage of a standard sense amplifier (single-end type, current mirror type). For example, the read bit line voltage VRBL1 at the time of reading “1” data can be 0.8 [V] or more when the power supply voltage is 1.8 [V].

In summary, in this embodiment, the threshold voltage of the read transistor can be a standard value. Therefore, it is not necessary to add an ion implantation process for controlling the threshold voltage.
Also, the read bit line voltage value can be a value suitable for the input voltage of a single-ended sense amplifier or a current mirror sense amplifier that is a standard sense amplifier.

  The following third to fifth embodiments relate to improvements of the first and second embodiments. Therefore, the applicable memory cell may be either FIG. 10 or FIG.

  The point to be improved here is that only the read transistor TR of the selected memory cell MCs is the main transistor that charges the read bit line RBL when “1” data is read. At this time, if the scale of the memory cell array is large, the load capacity of the read bit line RBL becomes large because the number of read transistors of the non-selected memory cell MCu serving as a load is large. Therefore, there is a problem that it takes time to charge.

  In the following third to fifth embodiments, an object is to solve this problem by providing means for assisting the read transistor TR of the selected memory cell MCs at the time of reading “1” data.

[Third Embodiment]
FIG. 7 shows selected memory cells MCs and auxiliary memory cells MCaux that belong to the same column in the memory cell array, a driver transistor TD, and a sense amplifier SA. This auxiliary memory cell MCaux is means for assisting the reading of the “1” data, and in the memory cell array of FIG. 1, in addition to the effective memory cell group of n × m, one more stage, a memory cell row. And m auxiliary memory cells MCaux are arranged in the memory cell row in the row direction, and each is inserted so as to be connected to the corresponding read bit line RBL and write bit line WBL one by one. If it is desired to further increase the read bit line charging capability when reading “1” data, it is possible to provide two or three or more auxiliary memory cells MCaux.

As shown in FIG. 7, the auxiliary memory cell MCaux is the same as the selected memory cell MCs in terms of circuit configuration. That is, the auxiliary memory cell MCaux includes the write transistor TW, the read transistor TR, and the capacitor C, similarly to the memory cell MCa (FIG. 2A) of the first embodiment. However, the gate of the write transistor TW is connected to the auxiliary write word line WWLaux, and the capacitor C is connected to the auxiliary read word line RWLaux. Similar to the selected memory cell MCs, the read transistor TR is connected to a voltage supply line VSL that supplies the power supply voltage Vcc.
In the auxiliary memory cell MCaux, “1” data is always written, and “1” data is rewritten even during refresh.

The voltage control for the memory cell is executed in the same manner as in FIG.
At this time, regarding the control of the auxiliary memory cell MCaux, for example, when the selected read word line RWLs of FIG. 3C is raised to a high level (1.8 [V]), the auxiliary read word line RWLaux is set to 0 [V ] To control.
For this reason, the read transistor TR of the auxiliary memory cell MCaux is turned on, thereby assisting the charging of the read bit line RBL by the read transistor TR of the selected memory cell MCs. At this time, the boosted voltage of the storage node SN of the auxiliary memory cell MCaux is a value obtained by the equation (2-1).

  Next, the reason why the auxiliary memory cell MCaux is provided will be described in more detail with reference to FIGS.

  The “1” data reading shown in FIG. 3 is performed in a state in which the read bit line RBL is discharged and is in a floating state of 0 [V]. At the time of reading “1” data, as shown in FIG. 3C, the selected read word line RWLs is shifted to a high level of 1.8 [V].

At this time, the speed at which the large load capacitance of the read bit line RBL is charged greatly affects the read speed. At the time of reading “1” data, normally, the sum of the ON current of the selected memory cell MCs (the read current Ir in FIG. 2B) and the ON current of the non-selected memory cell (Ioff in FIG. 2B). Accordingly, the read bit line RBL is charged.
The slowest charging speed in reading “1” data is when all the non-selected memory cells MCu (see FIG. 2B) hold the stored data “0”. At this time, there is only one read transistor TR in the selected memory cell MCs, and the read bit line RBL must be charged.

  Therefore, in this embodiment, although not particularly shown in FIG. 3, the voltage of the auxiliary read word line RWLaux in FIG. 7 is set to 0 almost simultaneously with the transition of the selected read word line RWLs in FIG. Keep [V].

  Thereby, the read transistor TR of the selected memory cell MCs that charges the read bit line RBL is assisted by the read transistor TR of the auxiliary memory cell MCaux, and the charge speed of the read bit line RBL is shortened. As a result, the time for reading “1” data can be shortened.

[Fourth Embodiment]
In the present embodiment, the “1” data read method using the auxiliary memory cell MCaux as in the third embodiment is applied to the semiconductor memory device having the cell array of the memory cell MCb shown in FIG.

  FIG. 8 shows selected memory cells MCs and auxiliary memory cells MCaux, driver transistors TD, and sense amplifiers SA belonging to the same column in the memory cell array.

As shown in FIG. 8, the auxiliary memory cell MCaux is the same as the selected memory cell MCs in terms of circuit configuration. That is, the auxiliary memory cell MCaux includes the write transistor TW, the read transistor TR, and the capacitor C, similarly to the memory cell MCa (FIG. 5A) of the second embodiment. However, the gate of the write transistor TW is connected to the auxiliary write word line WWLaux, and the capacitor C and the drain of the read transistor TR are connected to the auxiliary read word line RWLaux. The source of the read transistor TR is connected to the read bit line RBL.
In the auxiliary memory cell MCaux, “1” data is always written, and “1” data is rewritten even during refresh.

The voltage control for the memory cell is executed in the same manner as in FIG.
At this time, regarding the control of the auxiliary memory cell MCaux, for example, in FIG. 6C and FIG. 6D, the selected read word line RWLs and the non-selected read word line RWLu are set to the high level (1.8 [V] or the intermediate voltage VM. The auxiliary read word line RWLaux is controlled to the intermediate voltage VM almost simultaneously with the rise to = 0.9 [V]).
For this reason, the read transistor TR of the auxiliary memory cell MCaux is turned on, thereby assisting the charging of the read bit line RBL by the read transistor TR of the selected memory cell MCs. At this time, the boosted voltage of the storage node SN of the auxiliary memory cell MCaux becomes a value obtained by the equation (3-1).

  In this embodiment, in addition to the advantages of the first and second embodiments, there is an advantage of the third embodiment, that is, an advantage that the “1” data read speed can be shortened.

[Fifth Embodiment]
The present embodiment shows a modification of the third and fourth embodiments.

  FIG. 9 shows selected memory cells MCs and auxiliary means belonging to the same column in the memory cell array, driver transistor TD and sense amplifier SA.

The selected memory cell MCs may be either the memory cell MCa of FIG. 10 or the memory cell MCb of FIG.
In the fifth embodiment, as a means for assisting the read transistor TR of the selected memory cell MCs when “1” data is read, the auxiliary transistor Taux is provided between the voltage supply line VSL for supplying the power supply voltage Vcc and the read bit line RBL. It is connected.
The auxiliary transistor Taux of the present example is composed of a single NMOS transistor, but the NMOS transistor can be replaced by, for example, a PMOS switch.

  The auxiliary gate voltage V1aux supplied to the gate of the auxiliary transistor Taux is a voltage that transits from a low level to a high level when “1” data is read. The timing of the transition is substantially the same as that when the selected read word line RWLs in FIG. 3C or 6C is transitioned to a high level.

When the cell array is constituted by the memory cells MCa, the auxiliary gate voltage V1aux is a value obtained by the above equation (2-1) as in the third embodiment.
On the other hand, when the cell array is configured by the memory cell MCb, the auxiliary gate voltage V1aux is a value obtained by the equation (3-1), as in the fourth embodiment.

  The present embodiment has the same advantages as the fourth embodiment, and further has the advantage that the area of the cell array can be more easily reduced because the scale of the auxiliary means (auxiliary transistor Taux) is small.

In the first to fifth embodiments described above, the case where the write bit line and the read bit line are provided as the bit lines has been described. However, this may be a common bit line. The bit line in this case functions in the same manner as the write bit line WBL at the time of data writing, and functions in the same manner as the read bit line RBL at the time of data reading. The driver transistor TD is connected to the common bit line. However, the driver transistor TD does not hinder the function of the write bit line WBL by controlling the driver transistor TD not to be turned on at the time of data writing.
In addition, various modifications can be made without departing from the spirit of the present invention.

1 is a block diagram showing a memory cell array and main parts of a peripheral circuit in a semiconductor memory device according to an embodiment of the present invention. (A) is a circuit diagram which shows the structure which belongs to the same column regarding 1st Embodiment, (B) is an equivalent circuit schematic of the part which contributes to the reading. (A)-(F) is a timing chart which shows the voltage change of the various lines of 1st Embodiment. It is a graph which shows the relationship between a drive curve and a load curve. (A) is a circuit diagram which shows the structure which belongs to the same column regarding 2nd Embodiment, (B) is an equivalent circuit schematic of the part which contributes to the reading. (A)-(F) are timing charts which show the voltage change of the various lines of 2nd Embodiment. It is a circuit diagram which shows the structure which belongs to the same row regarding 3rd Embodiment. It is a circuit diagram which shows the structure which belongs to the same row regarding 4th Embodiment. It is a circuit diagram which shows the structure which belongs to the same row regarding 5th Embodiment. It is a circuit diagram of the memory cell used as a prior art. It is a circuit diagram of the other memory cell used as a prior art. It is a circuit diagram which shows the same memory cell as FIG. 10 in the same column. (A)-(E) is a timing chart which shows the voltage change of the various lines of FIG.

Explanation of symbols

  MC, MCa, MCb ... memory cell, MCs ... selected memory cell, MCu ... unselected memory cell, MCaux ... auxiliary memory cell, SA ... sense amplifier, TD ... driver transistor, TW ... write transistor, TR ... read transistor, SN ... Storage node, C ... capacitor, Taux ... auxiliary transistor, WWL ... write word line, WWLs ... select write word line, WWLu ... non-select write word line, RWL ... read word line, RWLs ... select read word line, RWLu ... non-select Read word line, RBL ... Read bit line, WBL ... Write bit line, VSL ... Voltage supply line, Vcc ... Power supply voltage, VM ... Intermediate voltage, VRBL ... Read bit voltage, VD ... Driver voltage, V1aux ... Auxiliary gate voltage, L1s Etc ... Load curve, D ... Driver curve, P1 etc. Operating point

Claims (11)

  1. Each memory cell constituting the memory cell array is
    A write transistor having a gate connected to the write word line, one of the source and drain connected to the bit line, and the other of the source and drain connected to the storage node;
    A read transistor having a gate connected to the storage node, one of a source and a drain connected to a bit line, and the other of the source and the drain connected to a voltage supply line;
    A capacitor connected between the storage node and the read word line;
    In the memory cell array, each of the write word line and the read word line is shared by a plurality of memory cells arranged in a row direction,
    A method of reading a semiconductor memory device in which the bit lines are shared by a plurality of memory cells arranged in a column direction,
    A constant current driving means is provided between the bit line and a reference potential;
    Among the plurality of memory cells that share the bit line and are arranged in the column direction, a power supply voltage is applied to a read word line of a selected memory cell to be read, and 0 [V] is applied to a read word line of an unselected memory cell that is not a read target. Is applied to turn on the constant current driving means.
  2. Provide auxiliary means for each bit line,
    The reading method of the semiconductor memory device according to claim 1, wherein the auxiliary unit is operated during reading to assist charging of the bit line.
  3. The method of reading a semiconductor memory device according to claim 2, wherein the auxiliary means is an auxiliary memory cell that is connected to each bit line and holds high-level data.
  4. The method of reading a semiconductor memory device according to claim 2, wherein the auxiliary means is an auxiliary switch connected between the bit line and the voltage supply line and turned on at the time of reading.
  5. Each memory cell constituting the memory cell array is
    A write transistor having a gate connected to the write word line, one of the source and drain connected to the bit line, and the other of the source and drain connected to the storage node;
    A read transistor having a gate connected to the storage node, one of a source and a drain connected to a bit line, and the other of the source and the drain connected to a read word line;
    A capacitor connected between the storage node and the read word line;
    In the memory cell array, each of the write word line and the read word line is shared by a plurality of memory cells arranged in a row direction,
    A method of reading a semiconductor memory device in which the bit lines are shared by a plurality of memory cells arranged in a column direction,
    A constant current driving means is provided between the bit line and a reference potential;
    Among the plurality of memory cells sharing the bit line and arranged in the column direction, a power supply voltage is applied to a read word line of a selected memory cell to be read, and a power supply voltage is applied to a read word line of an unselected memory cell that is not a read target. A method of reading a semiconductor memory device, wherein an intermediate voltage having a value between 0 [V] is applied to turn on the constant current driving means.
  6. The method of reading a semiconductor memory device according to claim 5, wherein the intermediate voltage is set to a value equal to or higher than a maximum value of the voltage read to the bit line.
  7. Provide auxiliary means for each bit line,
    6. The method of reading a semiconductor memory device according to claim 5, wherein the auxiliary means is operated during reading to assist charging of the bit line.
  8. The method of reading a semiconductor memory device according to claim 7, wherein the auxiliary means is an auxiliary memory cell connected to each bit line and holding high-level data.
  9. The method of reading a semiconductor memory device according to claim 7, wherein the auxiliary means is an auxiliary switch connected between the bit line and the voltage supply line and turned on at the time of reading.
  10. Each memory cell constituting the memory cell array is
    A write transistor having a gate connected to the write word line, one of the source and drain connected to the bit line, and the other of the source and drain connected to the storage node;
    A read transistor having a gate connected to the storage node, one of a source and a drain connected to a bit line, and the other of the source and the drain connected to a voltage supply line;
    A capacitor connected between the storage node and the read word line;
    In the memory cell array, each of the write word line and the read word line is shared by a plurality of memory cells arranged in a row direction,
    The bit line is shared by a plurality of memory cells arranged in a column direction;
    Constant current driving means is connected between the bit line and a reference potential,
    A semiconductor memory device having auxiliary means for each bit line.
  11. Each memory cell constituting the memory cell array is
    A write transistor having a gate connected to the write word line, one of the source and drain connected to the bit line, and the other of the source and drain connected to the storage node;
    A read transistor having a gate connected to the storage node, one of a source and a drain connected to a bit line, and the other of the source and the drain connected to a read word line;
    A capacitor connected between the storage node and the read word line;
    In the memory cell array, each of the write word line and the read word line is shared by a plurality of memory cells arranged in a row direction,
    The bit line is shared by a plurality of memory cells arranged in a column direction;
    Constant current driving means is connected between the bit line and a reference potential,
    A semiconductor memory device having auxiliary means for each bit line.
JP2005308963A 2005-10-24 2005-10-24 Semiconductor memory device and read-out method therefor Pending JP2007122758A (en)

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