JPS63146462A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To prevent the data on as memory cell from being destructed by a bit line driving circuit, by forming the memory cell region and the bit line driving circuit of a CMOS dynamic RAM in the respective different regions, and separating electrically both of them. CONSTITUTION:P-type well regions 12-14 are formed on an N-type substrate. In the well region 12, a memory cell array 15 only is formed, and a dummy cell 16 and a line driving circuit 17 are formed in the well region 13. Peripheral circuits 18 are formed in the independent well region 14 and on the substrate 11 and usual. The destruction of the data on the memory cell array caused by the minority carrier which generates as the bit driving circuit 17 operates can be prevented by this constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a semiconductor memory device, and particularly to a dynamic RAM having a CMOS structure.

(Prior art) In a dynamic RAM with a CMOS structure, data is destroyed when minority carriers generated in peripheral circuits such as address buffers and data output buffers are absorbed into storage nodes (capacitors) of memory cells. In order to prevent this, a structure has been considered in which a memory cell array is formed in a well to insulate such peripheral circuits from the memory cell array.

FIG. 5 shows a pattern plane of a dynamic RAM having such a structure, where ① is, for example, an N-type semiconductor substrate, and this semiconductor substrate ① has ゛P-type well regions 2.
3 are formed respectively.

A memory cell array 4, dummy cells 5, and a bit line drive circuit 6 are formed in the P-type well region 2, and the bit line drive circuit includes a bit line precharge circuit, a bit line equalization circuit, a sense amplifier, and a switching circuit for column selection. A portion formed by a P-channel type MOS (MOS) transistor in circuit B is formed on substrate 1. Similarly, a peripheral circuit 7 having a CMOS structure is formed within the PU well region 3 and the substrate 1.

By insulating the memory cell array 4 and the peripheral circuit 7 in this manner, it is possible to prevent the influence of minority carriers on the memory cells as described in ``2''.

However, even with this structure, data destruction as described above may occur. This is due to the coupling between the bit line, word line, and each control signal line for driving the bit line drive circuit B and the P-type well region 2 in which the memory cell array 4 is formed.
This is because the PN junction between the well region 2 and the N type diffusion layer formed in the well region 2 is biased in the forward direction, thereby generating minority carriers.

Another major cause is the generation of minority carriers due to the operation of the bit line drive circuit B formed in the P-type well region 2 together with the memory cell array 4. This is because the bit line drive circuit 6, which consists of four bit line precharge circuits, a bit line equalization circuit, a sense amplifier, and a switching circuit for column selection, cannot operate the MOS transistors in a pentode operation that generates a large number of minority carriers. This is because there are many.

The generation of minority carriers due to coupling with the signal line as described above can be prevented by biasing the P-type well region 2 below Vss (for example, -3V), but the operation of the bit line drive circuit 6 If a well bias is applied due to fluctuations in the well potential caused by this, the power consumption in the bias circuit becomes extremely large.

In addition, the application of this well bias increases the threshold voltage of, for example, an N-channel MOS transistor in the sense amplifier due to the so-called substrate bias effect, which reduces the current drive capability of the sense amplifier and reduces the operating speed of the memory. It also invites

(Problems to be Solved by the Invention) The present invention has been made in view of the above-mentioned points.In conventional semiconductor memory devices, minority carriers are generated due to the operation of the bit line drive circuit, and interference with each signal line occurs. It is an object of the present invention to provide a highly reliable semiconductor memory device that improves the problem that destruction of stored data is caused by the generation of minority carriers due to coupling, and prevents the generation of such minority carriers.

[Configuration of the Invention (Means and Effects for Solving Problems) That is, in the semiconductor memory device according to the present invention, only a memory cell array is formed in a specific well region of a conductivity type different from that of the semiconductor substrate, The memory cell array and bit line drive circuit are insulated. In this way, the number of signal lines wired in the well region where the memory cell array is formed can be reduced, and the influence of minority carriers generated due to the operation of the bit line drive circuit can be prevented.
It is possible to improve the operational reliability of the semiconductor memory device. Furthermore, since a well bias can be applied only to the well region where the memory cell array is formed, there is no increase in power consumption or decrease in operating speed.

(Example) Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a pattern plane of a semiconductor memory device according to an embodiment of the present invention. For example, an N-type semiconductor substrate 11
P-type well regions 12, 13, and 14 are formed in these regions, respectively. Only the memory cell array 15 is formed in the P-type well region 12, and in the past, the memory cell array 1
The dummy cell 6 and bit line drive circuit 17, which were formed in the same well as 5, are formed in the P-type well region 13.

The bit line drive circuit 17 includes a bit line precharge circuit,
It consists of a bit line equalization circuit, a sense amplifier, and a column selection switching circuit, and the portions of these circuits formed by P-channel type MOS transistors are formed within the substrate U. Similarly, the peripheral circuit 18 consisting of circuits other than the bit line drive circuit 17
are formed in the P-type well region 14 and the substrate 11.

In this way, the memory cell array 15 is connected to the bit line drive circuit 1.
By insulating the bit line drive circuit 17 from the bit line drive circuit 7, it is possible to prevent storage data from being destroyed by minority carriers generated with the operation of the bit line drive circuit 17. Furthermore, since only the memory cell array 15 is formed in the P-type well region 12,
The only signal lines wired to this well region 12 are bit lines and word lines. As a result, the generation of minority carriers due to coupling with the signal line as described above is also reduced.

FIG. 2 shows a specific circuit configuration of a semiconductor memory device including the bit line dynamic circuit 17, dummy cell IB1, and memory cell array 15 as described above. In FIG. 2, the one shown as 171 is an N-channel type M.
(OS) a bit line precharge circuit consisting of run transistors Ql and Q2; and an N-channel MOS) bit line equalization circuit consisting of a run transistor Q3. These circuits are controlled by a control signal Φ1, and precharge and equalize the potentials of the bits BL and BL, respectively.

The bit line drive circuit 17 includes a circuit 171 consisting of a bit line precharge circuit and an equalization circuit, a sense amplifier 172, and a column selection switching circuit 1 consisting of N channel type MOS transistors Q4 and Q5.
73, and is formed in the P-type well region 13 as explained in FIG.

However, a P-channel type MOS (P-channel type MOS) transistor portion of a circuit usually having a CMOS configuration, such as the sense amplifier 172, is formed on the substrate IT. The switching circuit 173
The control is performed by energizing the control signal Φ2.

Dummy cell IB is the first and second cell 181.162
Either cell 161 or 1B2 is selected by activation of dummy word lines DWLO and DWLl. The second dummy cell 1B is formed in the P-type well region 13 together with the bit line drive circuit 17.

Although the memory cell array 15 is composed of a large number of memory cells, only memory cells 151 and 152 connected to the bit lines BL and BL and selected by activation of the word lines WLO and WLl are shown in this figure. ing. This memory cell array 15 is formed in the PJJ1 well region 12 and is insulated from all other circuit sections.

Reference numeral 181 denotes a human output buffer, which is one circuit section constituting the peripheral circuit 18. As mentioned above, the peripheral circuit 17
A mold well region 14 and a substrate 11 are formed.

FIG. 3 shows the well bias VWL applied to the P-type well region 12.
(<ground potential V ss) is shown. Since only the memory cell array 15 is formed in the P-type well region 12, the P-type well region 12 is
Even if the well bias VWL is applied to the mold well region 12, the well bias VWL is not applied to other circuit parts, so that there is no reduction in operating speed due to power consumption or substrate bias effects as described above. Therefore, due to coupling with bit lines and word lines, the P-type well region 12
and the N-type diffusion layer formed in this well region 12.
It becomes possible to more effectively prevent the generation of minority carriers due to forward biasing of the junction.

In addition, by applying the well bias VWL, in the P-type well region 12, the PN junction capacitance between the bit line BL or the N-type diffusion layer that is in contact with the BL and the P-type well region 12 is reduced, so that no voltage is added to the bit line. It is possible to reduce the parasitic capacitance caused by this, and even higher speeds can be achieved.

FIG. 4 shows another embodiment of the present invention, in which a dummy cell IB is also formed in the P-type well region 12 along with the memory cell array 15.

Further, other circuit parts are formed in other areas as in FIG. 1. That is, the □ bit line drive circuit 17 is formed in the P-type well region 13 and the substrate 11, and the peripheral circuit 18 is formed in the P-type well region 14 and the substrate 11.

Even if the memory cell array 15 and the dummy cells 16 are formed in the same area in this way, the generation of minority carriers and the substrate current accompanying the operation of the dummy cells 16 are generally very small; effect can be obtained.

Furthermore, a method in which word lines and dummy word lines have complementary potential fluctuations, which is a method often used in semiconductor memory devices with a large storage capacity, is used, in which the word line WLO is set to "0".
When the potential changes from 1 to 1 and the memory cell 151 is selected, the dummy word line DWLO for selecting the dummy cell 181 connected to this bit line BL changes to 1.
When using a method in which the potential changes from 1 to 0'' level, potential fluctuations in the well region 12 due to coupling between the word lines WLO1WL1 and the P-type well region 12 and dummy word lines DWLO, DWLI and the P-type well region Since the fluctuation in the potential of the well region 12 due to the coupling with the well region 12 is canceled out, the potential of the well region 12 becomes further stable, and the generation of minority carriers can be further prevented.

Furthermore, if a well bias is applied to the P-type well region 12 where the memory cell array 15 and dummy cells 16 are formed,
The reliability of this semiconductor memory device is further improved.

In the above description, separate P-type well regions 13 and 14 were used to form the bit line drive circuit 17 and the peripheral port 8, but the same well region may be used.

Further, the present invention can also be applied to a semiconductor memory device in which an N-type well region is formed in a P-type semiconductor substrate and a P-channel MOS transistor is used as a data transfer transistor of a memory cell. In this case, the bias applied to the N-type well region is a positive potential.

[Effects of the Invention] As described above, according to the present invention, it is possible to prevent storage data from being destroyed due to the generation of minority carriers accompanying the operation of a bit line drive circuit, and to provide a highly reliable semiconductor memory device. Furthermore, since a well bias can be applied only to the region where the memory cell array is formed, there is no increase in power consumption or decrease in operating speed.

[Brief explanation of the drawing]

FIG. 1 is a pattern plan view illustrating a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a diagram showing a specific circuit configuration of the semiconductor memory device, and FIG. 3 is a diagram showing the formation of a memory cell array. FIG. 4 is a pattern plan view illustrating another embodiment of the present invention, and FIG. 5 is a pattern plan view illustrating a conventional semiconductor memory device. . DESCRIPTION OF SYMBOLS 11... Semiconductor substrate, +2.13.14... P-type well region, 15... Memory cell array, 16... Dummy cell, 17... Bit line drive circuit, 18... Peripheral circuit. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (4)

[Claims] (1) In a semiconductor memory device having a CMOS structure, a plurality of well regions of a conductivity type different from that of the semiconductor substrate are formed in a semiconductor substrate, and a memory cell array consisting of a plurality of memory cells and a bit line drive circuit are each formed in different well regions. A semiconductor memory device characterized in that it is formed in. (2) The semiconductor memory device according to claim 1, wherein the bit line drive circuit comprises a bit line precharge circuit, a bit line equalize circuit, a sense amplifier, and a column selection switching circuit. (3) Dummy cells are formed in the well region where the memory cell array is formed.
The semiconductor storage device described in . (4) The semiconductor memory device according to any one of claims 1 to 3, wherein a well bias is applied to the well region in which the memory cell array is formed.