GB2032211A

GB2032211A - High Performance Dynamic MOS Read/Write Memory

Info

Publication number: GB2032211A
Application number: GB7931003A
Authority: GB
Original assignee: Texas Instruments Inc
Current assignee: Texas Instruments Inc
Priority date: 1978-09-07
Filing date: 1979-09-06
Publication date: 1980-04-30
Also published as: DE2935121C2; HK28788A; DE2935121A1; GB2032211B

Abstract

A random access read/write MOS memory device consisting of an array of rows and columns of one-transistor memory cells employs a bistable sense amplifier circuit at the centre of the dynamic type in that coupling transistors connect the column line halves to the cross-coupled driver transistors. Active load devices connected to the column line halves provide pull-up of the voltage on the one-going column line half to a full Vdd level. An improved circuit is used for the address inputs, data inputs, or the like, to permit undershoot of the voltage on input lines, while not requiring substrate bias on the semiconductor chip. Buffers function to latch the data or address to allow the inputs to change states. The buffer is activated by TTL level inputs, exhibits low capacitance at its input, and switches states fast enough to allow rapid multiplexing of the addresses. Noise immunity is improved by selective implants of some of the transistors. A heavily doped guard ring, N+ for a P-type substrate, connected to Vdd, surrounds the transistors in the input stages to avoid the effects of injection of minority carriers by forward biasing of PN junction regions at the input. <IMAGE>

Description

SPECIFICATION High Performance Dynamic MOS Read/Write Memory This invention relates to semiconductor memory devices and more particularly to an improved, high performance, MOS random access read/write memory.

Semiconductor memory devices of the type made by the N-channel silicon-gate MOS process and employing one transistor dynamic cells are now the most widely used in computers and digital equipment. One continuing problem in these devices is the sense amplifier which must detect the small change in voltage on a digit line caused by a cell being addressed. As the number of cells on a digit line increases and the cell size decreases, the ratio of the storage cell capacitance to the digit line capacitance, and thus the voltage change produced when a cell is accessed, also decrease. The trend toward use of 5V power supplies rather than 12V also reduces the signal level. These factors make the performance of the sense amplifier more critical.

Also, the continuing trend toward higher speeds and lower power dissipation place additional constraints on the sense amplifier design.

Examples of prior sense amplifiers are disclosed in U.S. Patent No.3,909,631 and 4,050,061 issued to N. Kitagawa, No.4,081,701 issued to White McAdams and Redwine, and pending Applications S.N. 682,687 filed May 3, 1976 (refiled June 30, 1978 as S.N. 920,755) by Kitagawa and McAlexander, and S.N. 691,734 filed June 1, 1976 (refiled June 30, 1978 as S.N.

920,756) by Kitagawa and White, all assigned to Texas Instruments, as well as articles in Electronics Magazine, September 13, 1973 at pp.

116~121, February 19, l976atpp. 116-121, and May 13,1976 at pp.81-86 and U.S. Patent 4,061,999. The prior sense amplifiers have not been adequate for new designs of MOS RAMs of very high density-64K bits, operating on a single 5V supply with access times of 100 to 1 50 nsec.

or faster.

Another of the design problems in these devices is the input circuits which must detect and latch on TTL level address signals, data signals, or controls, and yet tolerate some degree of noise and extraneous voltage spikes. As the operating speed or access time of memory devices increases, the constraints upon the design of the input increases because the rate of switching of the multiplexed addresses is faster and noise on the address lines is at a higher level.

Use of no substrate bias rather than~5 substrate bias lowers MOS threshold voltages, and logic levels are lower for 5V rather than 12V power supplies, so the permissible noise level is lower.

Present specifications for MOS RAMs require that the input voltages on all the address and other input lines be allowed to go to -1 V. These inputs include RAS, CAS, W, data-in as well as seven or eight address lines for 16K or 64K RAM of current design. This requirement was easily accommodated when the part used a substrate bias which prevented a forward bias voltage across any of the input diodes and so prevented injection of minority carriers.

Examples of prior input buffers are disclosed in U.S. Patent 4,031,415 issued to Redwine and Kitagawa, and U.S. Patent 4,110,639 issued to Redwine, both assigned to Texas Instruments.

Semiconductor memory devices such as the widely used 4K, 16K or 64K dynamic MOS RAMs employ a large number of clock voltages which are generated on the chip itself. An external clock such as a chip enable clock or a row of column address strobe is used to initiate a series of internal clocks which have a wide variety of different delay times. In some cases, as many as twenty to twenty-five internal clocks are needed for the circuitry in a dynamic RAM chip. The delay periods must be precise, and the rise and/or fall rates correct. The output level usually needs to be a full supply level rather than a threshold lower than the supply voltage, and often the clock must drive a rather large capacitive load. Power dissipation is always a factor since the dissipation of the chip must be kept to a minimum, particularly when standby operation is provided.

Summary of the Invention In accordance with one embodiment of the invention, a random access read/write MOS memory device consisting of an array of rows and columns of one-transistor memory cells employs a bistable sense amplifier circuit at the centre of each column. The sense amplifier is of the dynamic type in that coupling transistors connect the column line halves to the cross-coupled driver transistors.

Active load devices connected to the column lines halves provide pull-up of the voltage on the one-going column line half to a full Vdd level. An improved circuit is used for the address inputs, data inputs, or the like, to permit undershoot of the voltage on input lines, while not requiring substrate bias on the semiconductor chip.

Buffers function to latch the data or address to allow the inputs to change states. The buffer is activated by TTL level inputs, exhibits low capacitance at its input, and switches states fast enough to allow rapid multiplexing of the addresses. Noise immunity is improved by selective implants of some of the transistors.

A heavily doped guard ring, N+ for a P-type substrate, connected to Vdd, surrounds the transistors in the input stages to avoid the effects of injection of minority carriers by forward biasing of PN junction regions at the input.

In one specific embodime t of the invention the sense amplifier is of the dynamic type as seen in U.S. Patent 4,061,999 in that coupling transistors connect the column line halves to the cross-coupled driver transistors. The sources of the driver transistors are connected to ground through a sequentially timed, three step grounding arrangement employing two transistors, similar to Application S.N. 920,755, one transistor being dual channel implanted to provide two different threshold voltages. Active load devices as in U.S. Patent 4,081,701 connected to the column line halves, provide pullup of the voltage on the one-going column line half to a full Vdd level.

In accord with another embodiment of the invention, a random access read/write MOS memory device employs bistable latch or buffer circuits as the address inputs, data inputs, and the like. The buffers function to latch the data or address to allow the inputs to change states. The buffer is activated by TTL level inputs, exhibits low capacitance at its input, and switches states fast enough to allow rapid multiplexing of the addresses. Noise immunity is improved by selective implants of some of the transistors, and by use of filter capacitors connected between input nodes and Vss rather than Vdd.

In accord with another embodiment of the invention a clock generator for producing internal waveforms for an MOS dynamic RAM or the like provides a preselected delay period between input and output clocks. A pair-delay circuit including two transistor stages produces the desired delay, a driver circuit provides the necessary high level output. A pair of series transistors in the output of the pair-delay, with the nodenod,@ between the series transistors being precharged, provides precise control of the delay over a wide range.

Input signals are permitted to go to voltage levels less than zero so that diodes in the input, as must be present for protection against static charge, are forward biased. Yet injection of minority carriers into substrate is not detrimental to the operation of memory cells and logic circuits on the chip.

This is accomplished by surrounding part of the input circuit with a guard ring of N+ material connected to a Vdd supply.

Brief Description of the Drawings The novel features believed characteristic of the invention are set forth in the appended claims.

The invention itself, however, as well as other features and advantages thereof, will be best understood by reference to the detailed description which follows, read in conjunction with the accompanying drawings, wherein: Figure 1 is an electrical diagram in block form of a semiconductor dynamic memory device which may use the features of the invention; Figures 2a-2g are graphic representations of voltage vs time or other conditions vs time existing for various parts of the device of Figure 1; Figure 3 is an electrical schematic diagram of a part of the device of Figure 1 showing the sense amplifier of one feature of the invention in detail in a memory array; Figure 4a-41 are graphic representations of voltage vs time existing at various parts of the circuit of Figure 3;; Figure 5 is an electrical schematic diagram of a part of the device of Figure 1 showing the input circuit of one feature of the invention in detail; Figures 6a-6f are graphic representations of voltage vs time existing at various parts of the circuit of Figure 5; Figure 7 is a plan view of a small part of a semiconductor device, greatly enlarged, containing the input circuit of one feature of the invention; Figure 8 is an electrical schematic diagram of a prior art clock generator circuit for an MOS RAM; Figures 9a-9e are graphic representations of voltage waveforms appearing at various points in the circuit of Figure 8 as well as in the circuit of Figure 10; and Figure 10 is an electrical schematic diagram of an improved clock generator circuit for use in the device of Figure 1 according to a feature of the invention.

Detailed Description of Specific Embodiment Referring to Figure 1, a memory device which may utilize the various features of the invention is illustrated in block diagram form. This is a random access, read/write memory of the dynamic type, made by an N-channel, selfaligned, silicon gate MOS process. All of the memory device of Figure 1 is included in one silicon chip of about 1/30 of a square inch in size which usually would be mounted in a standard dual-in-line package having sixteen pins or terminals. The device includes in this example an array 10 of 65,536 memory cells, with the array split into two halves 1 Oa and 1 Ob of 32,768 cells each, in a regular pattern of 256 rows and 256 columns. Of the 256 row or X lines, there are 128 in the array half 1 Oa and 128 in the half 1 Ob.The 256 column or Y lines are each split in half with one half being in each of the halves 1 Oa and 1 Ob.

There are 256 sense amplifiers 11 in the centre of the array; these are differential type bistable circuits made according to one feature of the invention, and each one is connected in the centre of a column line. Thus 128 memory cells are connected to each side of each sense amplifier by a column line half. The chip requires only a single 5V supply Vdd, along with a ground terminal Vss.

No internal charge pump is needed because no substrate bias is employed.

A row or X address decoder 12, split into two halves, is connected by sixteen lines 13 to eight address buffers or latches 14 (made according to a feature of the invention) via output circuits 1 5.

An eight-bit X address is applied to inputs of the address buffers 14 by eight address input lines 16. The X decoder 12 functions to select one of the 256 lines as defined by an eight bit address on the input terminals 16; of the selected row line is in the half 1 Ob of the cell array then a row of dummy cells 17 on the opposite side of the sense amplifiers 11 is also activated, while if a line in the half 1 Oa is selected then a row of dummy cells 18 is activated. The address signals on the input lines 16 are multiplexed; the Y address is also applied to these input lines and is latched into a set of eight buffers 19 (constructed into the sense amplifier precharge balance operation.Vtr is precharged to Vdd and at the start of the active portion of the cycle, Vtr is pulled to less than Vdd to ensure that the active loads remain totally inactive until one of the column lines 38a or 38b falls to Vdd-2Vt and also ensures that additional parasitic capacitances on the nodes 72 and 73 are not seen by the column lines 38a and 38b until after the sense amplifier latching has occurred.

The Input Buffer Circuit With reference to Figure 5, an input buffer circuit 14 according to one feature is illustrated.

This circuit consists of a balanced flip-flop including a pair of driver transistors 80 and 81 with the drains at nodes 82 and 83 being crosscoupled to the opposite gates to provide bistable operation. Input transistors 84 and 85 are connected in parallel with the driver transistors. A dc reference voltage of about 1.5 V is connected to the gate of the transistor 85 via a line 86 and a transistor 87. The input signal to be detected, amplified and latched upon is applied via an input terminal 16, 30 or 36 through a pair of series transistors 88 and 89 to the gate of the transistor 84. The reference voltage is selected to be half way between the worst case TTL low level of 0.8 V and the worst case TTL high level of 2.2 V. The input signal and the reference voltage are latched onto nodes 91 and 92 and held on the capacitors 93 and 84 when a Pmf clock goes to Vss.Pmf, as applied to the gates of transistors 87, 88 and 89, is seen in Figure 6a. In the prior art in order to get good conduction through the transistors 84 and 85 and thereby set the flip-flop, the voltage at the nodes 91 and 92 was boosted above the threshold voltage by capacitors connecting these nodes to a special clock, and device sizes and physical layout were kept balanced and symmetrical to maintain reliable operation.

Different methods are used in the present invention, as will be explained.

The output stage of the buffer functions to sense the change in voltage on the nodes 82 and/ 83 when the flip-flop operates. A transistor 95 is connected between Vdd and a node 96, which in turn is connected through the source-to-drain paths of a pair of transistors 97 and 98 to nodes 99 and 100. The gates of all three of these ~~~ transistors 95, 97 and 98 are connected to a Pm clock as seen in Figure 6b. Thus, during the precharge part of the cycle, when Pm is high, the internal nodes are precharged; the transistors 95, 97 and 98 are on, which equalizes the voltages on the nodes 99 and 100 and precharges these nodes to a level of Vdd-Vt. At the time Pmis high and the nodes 99 and 100 are high, Pm, seen in Figure 6c, is at a low level near or equal to Vss.

Transistors 101 and 102, connected between the Pm clock and nodes 82 and 83, are on when Pm is high, precharging the nodes 82 and 83 to a low level or Vss. This holds a pair of transistors 103 and 104 off. No dc current flows in the buffer circuit.

The 1.5 V reference voltage is applied to the node 92 through the. transfer and latching transistor 87 when Pmf is high, while the TTL signal input level is applied to the node 91 through transistors 88 and 89. The input will have a set up time tsu as seen in Figure 6d, representing the time that the input signal must be valid before Pmf goes low, allowing the capacitance of the node 91 to be fully charged.

When the Pmf clock goes low the transistors 87, 88 and 89 turn off to trap the TTL level on the node 91 and Vref level on the node 92. A slight dip in the voltage levels on the nodes 91 and 92 will result due to overlap capacitance coupling from the gates of the transistors 87 89. As Pm goes high, transistors 101 and 102 can begin to be conductive; if the voltage on one or both of the nodes 91 and 92 is above Vt for 84 or 85, the transistors 84 and/or 85 can be conductive. More current will flow through the transistor with the highest gate voltage. The voltage on both nodes 82 and 83 will start to rise with Pm as seen in Figure 6e. If a TTL "1" level is applied to the input 16 and latched on the node 91 , then the transistor 84 will conduct more at this point than transistor 85.The node 82 will be pulled to Vss, turning off transistor 81 and allowing the node 83 to continue to rise, latching the flip-flop. The transistor 104 will be off and the transistor 103 on, leaving node 100 at its precharged high level of Vdd-Vt, and node 99 will be discharged to Vss.

The nodes 99 and 100 are the outputs of the first stage of the input buffer 14. The current drive capability of the transistors 101 and 102 is limited, so typically two more buffer stages, represented by the output stages 15 or 23, are used to drive the address decoders with the A and A inputs, for example.

Operation for a "0" level TTL input is similar but the flip-flop latches in the opposite state. The node 92 will be higher than the node 91 after Pmf goes low. The transistor 85 will pull the node 83 to Vss, turning off transistor 80. This allows the node 82 to continue to rise with Pm. The transistor 104 will turn on, discharging the node 102 while transistor 103 will be off allowing the node 101 to stay high.

As thus far described, the input buffer is very similar to the prior art buffers as used in the 4116 memory devices, for example.

In accordance with one feature, low Vt or depletion mode transistors are used as the input transistors 84 and 85. This eliminates the need for booting the nodes 91 and 92. The transistors 84 and 85 are designed to have a negative operating threshold voltage and so the transistors will be on after Pmf goes low. That is, these transistors 84 and 85 are implanted or otherwise treated in the manufacturing process-to exhibit threshold voltages of about zero or slightly negative. Using single ion implant Vt adjust, for example, the transistors 87, 88, 89, 97, 98, 101 and 102 are made to have an intermediate threshold, greater than that of transistors 80, 81, 84 and 85, but less than that of transistors 80, 81,84 and 85. The transistors 103 and 104, on the other hand, are double implanted to provide a threshold voltage of about 0.8 V or above.One TTL level is 0.8 V. The higher threshold of transistors 103 and 104 functions to delay the turn on of these transistors until node 82 or 83 has increased to a higher level than would be required if all devices has the same threshold, thereby reducing the effect of the voltage noise bump on nodes 82 and 83 when Pm rises as seen in Figure 6e. The transistor 95 is designed to have a higher threshold than the transistor 97 and 98.

This is accomplished by double implant adjust or by using a narrow channel width and longer channel length. Transistors 97 and 98 will remain in the triode region of operation even when the transistor 95 is in saturation. Also, with transistors 97 and 98 having a lower threshold, the nodes 99 and 100 can be precharged to Vdd minus the threshold voltage of transistor 95 taking into account the body effect transistors 97 and 98 turn on ahead of transistor 95 when Pm goes high. This permits the nodes 99 and 100 to being equalizing before they begin to be precharged through transistor 95.

The capacitors 93 and 94 are connected from the nodes 91 and 92 to Vss rather than to Vdd as was done in the prior art. A noise spike on Vss will level,.shift the source electrodes of transistors 84 and 85 and will increase the threshold of these transistors due to the body effect. With the capacitors 101 and 102 using Vss as one electrode, this noise couples equally into nodes 91 and 92 and increases the gate voltage by the amount of the increased source voltage thus keeping the gate-to-source voltage constant.

Therefore, this added immunity will permit practical sensing even with noise occurrences.

The clock Pm seen in Figure 6c is a pulsed signal to minimize the time that a dc current path exists from a Vdd level to Vss through either transistors 1 Ol and 84 or transistors 102 and 85.

Figure 7 shows a layout of a small part of a semi-conductor chip which contains all of the 64K memory of Figure 1 and its peripheral circuitry. Figure 7 includes only a portion of one of the sixteen address buffers 14 and 19, the dimensions of the part shown being about one mil by two mils. The entire chip is about 150x225 mils. An input line 16 is connected by a metal line 106 to one end of an elongated irregularlyshaped N+ moat region 106 which contains the sources and drains of the transistors 88 and 89.

The gates of these two transistors, as well as the gate of the transistor 87, are defined by a polycrystalline silicon segment 107. Extended portions 108, 109 and 110 of the segment 107 provide the gates of the transistors 87, 88 and 89, respectively. The reference voltage Vref supply 86 is a metal line connected to the source 111 of the transistor 87, while the drain 112 of this transistor is connected by a metal line 113 to the gate of the input transistor 85 (not shown), via a metal-to-moat contact 114. The Pmf clock input is a metal line 11 5 connected to the polysilicon segment 107 at a metal-to-poly contact 11 6. One end of the moat 1 06, at the drain of the transistor 88, is connected to the gate of the transistor 84 by a metal line 11 7 and a metal-to-moat contact 118.An extended part 11 9 of the moat 106, integral with the drain of transistor 88 and the source of transistor 89, provides the lower plate of a capacitor 120. The upper plate of this capacitor is defined by a polysilicon segment, which is connected to Vdd via a metal strip 121 through a metal-to-poly contact 1 22. Surrounding all of these elements is an N+ diffused moat region 123 which functions as a guard ring to collect minority carrier electrons that might be injected into the silicon substrate by noise sources. The guard ring region 123 is connected to Vdd at a metal-to-moat contact 124.

In this description of Figure 7, the term moat is used to mean the area where thick field oxide is not grown, so it is the area covered by a-nitride oxidation mask in the field oxidation step of the manufacturing process. So, the moat includes all of the N+ diffused regions as well as the channel regions under gate oxide, i.e. all active areas.

It is of note that the circuit of the improved buffer is of reduced complexity compared to previous input buffers. The need for booting capacitors and the delay circuit for generating booting signals is eliminated. This reduced component count results in a smaller layout. Also, critical clock timing is simplified compared to the prior art which required booting of the input and reference nodes before the bistable circuit could be switched, setting constraints on the clock timing. In this circuit, as soon as Pmf goes off, the data-in is latched and the bistable circuit can begin switching. Not only is the timing simplified, but also switching time is faster. The addresses A, A are present on the lines 13 or 24 in a shorter time, i.e. less propagation delay, after the address is present on the lines 16 and RAS or CAS occurs.

Further, the increased current conduction at lower voltages due to the reduced Vt of the transistors 80, 81, 84 and 85 provides faster switching time.

Noise immunity is increased because of the high Vt of the transistors 103 and 104; the noise on the nodes 82 and 83 when the clock Pm goes high is less likely to be reflected in the output.

Also, the immunity to noise on Vss is improved by the fact that the capacitors 93 and 94 are connected to Vss rather than Vdd.

The N-channel integrated circuit memory device of Figure 1 employs a positive five volt level as a logic "1", and this positive voltage is stored on some nodes that are temporarily isolated from the power supply. The pn junction surrounding each such node is reverse biased and so a large depletion region extends into the substrate below and around the junction. A small leakage current will flow across the depletion region due to hole-electron pairs generated within this region, but this leakage is so low that the stored potential can last a long time. Induced junction storage nodes as used in the capacitors according to one feature of the invention like the buffers 14), from which it is applied to column decoders 20,21 and 22 via output circuits 23 and lines 24.A one-of-64 selection is made by the column decoders 20 and 21, so that one group of four columns is connected to sets of four data and data bar lines 25 and 26, based on six bits of the eight bit Y address. A one-of-four decoder 22 selects one pair of the four pairs of lines 25 and 26, based on two bits of the eight bit Y address, and connects the selected pair to a data 110 control circuit 27 via a pair of lines 28. A single bit data input is applied by an input terminal 30 to a data input latch 31, and the output of this latch is coupled to the data 110 control 27. The latch 31 may be of the same circuit design as the address latch circuits 14. One-bit data output is connected from the data I/O control 27 through a buffer 32 to a data out terminal 33.

The X address must appear on the inputs 16 when a row address strobe signal, referred to as RAS, is applied to an input 34. Likewise, the Y address must appear during a column address strobe signal CAS on an input 35. A read/write control W on an input 36 is the other control signal for the device. These three inputs are applied to clock generator and control circuitry 37 which generates a large number of clocks and control signals to define the operation of various parts of the device. When RAS goes low as seen in Figure 2a, clocks derived from RAS cause the buffers 14 to accept and latch the eight bits then appearing on the input lines 16. When CAS goes low as seen in Figure 2b then clocks generated in the circuitry 37 cause the buffers 19 to latch on the Y address on the inputs 16. The row and column addresses must be valid during the time periods shown in Figure 2c.For a read cycle, the W signal on input 36 must be high during the period seen in Figure 2d, and the output on the terminal 33 will be valid during the time seen in Figure 2e. For a write cycle, the W signal must be low as seen in Figure 2f, and the data-in bit must be valid during the time seen in Figure 2g. The data-out pin stays in a high impedence state.

In Figure 3, a portion of the cell array is shown in schematic form. Four identical sense amplifiers 11 are positioned at the centre of the array, connected to four column line halves 38a or 38b.

Sixty-three other sets of four sense amplifiers and column lines are included in the array. Connected to each column line half 38a or 38b are 128 onetransistor cells each having a storage capacitor 40 and a transistor 41. The cells are of the type described in U.S. Patent 4,012,757. Row lines 43 are connected to the gates of all of the transistors 41 in each row; there are 256 identical row lines 43 in the array. Also connected to each column line half 38a or 38b is a dummy cell 17 or 18 which consists of a storage capacitor 44, an access transistor 45 and a grounding transistor 45'. The gates of all dummy cells in a row are connected to a line 46 or 47.When the X address selects one of the lines 43 on the left, the associated transistor 41 is turned on to connect the capacitor 40 for this selected cell to the column line half 38a, while at the same time the dummy cell select line 47 on the opposite side is activated, connecting the capacitor 44 in one of the cells 18 to the column line half 38b. The dummy cell capacitance 44 is about 1/3 that of the storage cell capacitance 40. The dummy cell is pre-discharged to a logic zero before every active cycle.

The improved sense amplifier consists of a bistable circuit having a pair of driver transistors 50 and 51, each with its gate connected to the drain 52 or 53 of the other to provide a cross coupled flip-flop. The drains 52 and 53 are connected to nodes 54 and 55 at the ends of the lines 38a and 38b through the source-to-drain current paths of a pair of coupling transistors 56 and 57. The gates of the transistors 56 and 57 are both connected to a source of a clock voltage Ptr, seen in Figure 4j, which is above Vdd for most of the cycle then drops to Vdd during the active part of a cycle.The nodes 54 and 55 and column line halves 38a and 38b are precharged through the source-to-drain current paths of a pair of transistors 58 and 59 connected to a voltage source Psp; this voltage source, shown in Figure 4g, is Vdd during the precharge part of the cycle, drops to an intermediate level, then drops to zero during the active part of the cycle. The gates of the transistors 58 and 59 are connected to a clock voltage Psl seen in Figure 4h.

The sources of the driver transistors 50 and 51 are connected together at a node 60, and this node 60 is connected by a line 61 to the same node in all of the 256 sense amplifiers 11 in the array. The line 61 is connected to a transistor 62 and a dual channel transistor 63 and 64 which function as grounding paths. The gate of the transistor 62 is connected to a clock Psb1 seen in Figure 4b, and the common gate of the dual transistor 63 and 64 is connected to a clock Psb2 seen in Figure 4c. This grounding arrangement is similar to that of Application S.N. 682,687 filed May 3, 1976, refiled June 30, 1 978 as S.N.

920,755, assigned to Texas Instruments. Instead of using separate clock sources for the dual transistors 63 and 64, however, an important feature is the use of a single clock source. The two current paths of the dual transistor 63 and 64 turn on at different times because the channel area of the transistor 64 is ion implanted to raise its threshold so that it turns on later than the transistor 63 even though the same clock is applied to its gate. The dual transistor 63 and 64 (actually one large transistor with different channel implants) is much larger than the transistor 62, in channel width to length ratio.

Alternatively, the channel length of 64 would be longer than that of 63.

As described thus far, operation of the sense amplifier is similar to that of U.S. Patent 4,061,999, as used in the 4027 and 4116 dynamic RAM devices. The column line halves 38a and 38b along with nodes 54 and 55 are precharged to nearVdd during the precharge part of an operating cycle when both Psp and Psl are high. At this time Ptr is high so the nodes 52 and 53 are precharged also. The transistors 50 and 51 are off because the transistors 62-64 are all off, Psb1 and Psb2 being low. AfterF7has gone low, turning off the transistors 58 and 59, and before Psb1 goes high, an X address reaches one of the lines 43 at the same time that one of the dummy cell address lines 46 and 47. is activated.This causes an imbalance in the voltage on the nodes 54 and 55, and the same differential is coupled to the nodes 52 and 54 because the voltage Ptr is higher than Vdd. The nodes will separate no more than perhaps fifty millivolts at this point. Then, when Psb1 goes high and the small transistor 62 turns on, the sensing operation is initiated and the nodes separate more as the bistable circuit including the transistors 50 and 51 goes toward a stable condition with one transistor conducting and the other cut off. A slight delay from Psb1, the clock Psb2 goes high to complete the sensing operation by latching the bistable circuit and obtaining a good one/zero set on opposing digit lines.By capacitor 65 along with the parasitic capacitances of the transistors 56 and 57, the voltage Ptr is dynamically level shifted from greater than Vdd down to Vdd; the drop in voltage on the node 60 toward Vss as Psb1 then Psb2 go high is coupled to the gates of the transistors 56 and 57. This results in maintenance of a low conductivity channel between nodes 54 and 52 and between nodes 55 and 53, through the transistors 56 and 57. While latching is initially occurring between the transistors 50 and 51, the column lines 38a and 38b are capacitively isolated from the sensing nodes 52 and 53. When one or both of the nodes 52 and 53 falls by one Vt below Ptr, then the channel conductance will increase and the digit lines will follow in accordance with the now determined and latched state of the bistable circuit. Ptr is clamped at Vdd just after Psb2 goes high.

According to an important feature, an active pull-up circuit is employed to allow storage of a full Vdd level. This circuit comprises a pair of pullup transistors 66 and 67 connecting the nodes 54 and 55 to Vdd, along with control transistors 68 and 69 connecting the gates of the transistors 66 and 67 to the nodes 54 and 55, and capacitors 70 and 71 connecting the gates to a boosting clock Pb occurring after Psb2. The gates of the transistors 68 and 69 are connected to a trap voltage Vtr which stays at a level of about 1 Vt below Vdd during the active part of the cycle then at Vdd during the precharge part.

After the sensing operation is essentially completed and Psb2 has come on to render first the low threshold transistor 63 then after a slight delay the higher threshold transistor 64 conductive, a definite logic one and logic zero are set up on the column lines 38a and 38b. Then, about four nanoseconds after Psb2 goes high, the selected X line (but not the dummy cell select line) is slowly boosted to a level of (Vdd+Vt) to permit restoration of a full Vdd level in the capacitor 40 for the selected cell. The voltage on the dummy cell select line 46 or 47 is not boosted because the dummy cell capacitor 44 never stores a one; it is always discharged or at logic zero. At the same time the X line 43 is being boosted, the clock Pb goes high to activate the active load circuits. The clock Pb causes level shift at either node 72 or 73 via the gated capacitors 70 and 71.Only one of these nodes will have retained a logic one because the column lines will be near the one/zero set at this time; conduction through the transistor 68 or 69 for the zero-going side will discharge node 72 and 73 and cause the gated capacitor 70 and 71 to exhibit very little capacitance so Pb will not charge the node 72 or 73 for this side. The other node 72 or 73 which retained a one, at near Vdd, will be shifted to greater than Vdd thereby allowing this column line half to be pulled back up to Vdd through transistor 66 or 67. At the same time as Pb occurs, the clock Psb is pulled to Vss.

Selection of one group of four of the 256 column lines 38a and 38b by a Pyh voltage occurs a slight delay from when Psb2 goes high.

This ensures quiet sensing because only sensing signals occur in the vicinity of the sense amplifier during the critical time of the sensing operation.

The one-of-64 column decoder 20 and 21, physically located in the space between the sense amplifiers 11 and the data and data bar lines 25 and 26, produces only one Pyh signal on a line 74 to activate only one set of four transistors 75 coupling nodes 54 to lines 25 and one set of four transistors 76 coupling nodes 55 to lines 26. The remaining sixty-three sets of sense amplifiers 11, although operative for refresh on every read or write cycle, will not be coupled to the data and data bar lines because the Pyh signal on the line 74 will be low for these.

Upon completion of the active portion of a read or write cycle, the precharge portion of the cycle is activated by RAS going high. The selected V - line 43 and dummy cell line 46 or 47 are first pulled low to isolate the selected bit cells and dummy cells. Psi goes high toward Vdd, shorting the column lines 38a and 38b to Psp, rapidly equalizing the voltages on the nodes 54 and 55 via Psp through the transistors 58 and 59 to a voltage slightly above Vss. A slight overlap ~ between turning on transistor 58 and 59 by Psl and bringing Psp high promotes rapid equalization at near Vss.Then, as Psp is pulled back to a full Vdd, and the column lines 38a and 38b also are pulled back up to Vdd, Psi is boosted above Vdd, promoting equalization as the node 54 and 55 voltages increase. The capacitors 44 in the dummy cells are discharged to Vss by Psd going to Vdd. The clocks Psb1 and Psb2 are pulled low just prior to equalization of the column lines 38a and 38b. The subsequent precharging of the column lines 38a and 38b and the nodes 52, 53 and 60 and boots Ptr to greater than Vdd through transistors 56 and 57. Pb is pulled low also prior to equalization so that no interference is injected #2 input 11 turns on a transistor 36, discharging the output 13 quickly to Vss.

Several disadvantages exist in the prior art circuit of Figure 8. These have been corrected in the new circuit as will be explained.

First, the delay circuit including the pair of transistors 1 6 and 17 is inadequate for good control over the delay time 14. This is because the transistor 17 starts to turn on as soon as its gate voltage exceeds its threshold voltage, regardless of the device sizes. Thus, if the transistor 16 is made small and the transistor 17 is made large to create more delay, the voltage on the node 21 will start to discharge starting at about the same time as previously. This is illustrated in Figure 9d where the line 21' is the voltage on the node 21 with a given size ratio for the transistors 16 and 17 and the line 21" is the voltage with transistor 16 smaller and transistor 1 7 larger. Note that the fall time is slower, whereas the desired waveshape is the dotted line 21 a.The voltage on the node 20, the gate of the transistor 17, is shown by a line 20'; as soon as this voltage reaches Vt, about 0.8 volts, the transistor 17 begins to conduct and discharges the node 21.

Secondly, in some applications of the clock generator circuit of Figure 8, the time period 37 between the end of ~ and the beginning of < )1 is extended. During this time period, the node 20 floats since tis off and the input ~ 1 is low. In this condition the conduction state of the transistor 17 becomes indeterminate. Noise on the ground line may drive the source of the transistor 17 negative, turning it on and causing charge to be lost from the node 21. This tends to cause the voltage on the node 21 to drop below (Vdd-Vt), and if it does then the transistor 23 will conduct with the result being that the charge which should boot the node 22 high when O1 goes high, as seen by the line 22', will instead go through the transistor 23 into the node 21.Circuit operation can collapse rapidly because of a 2Vt drop in the voltage to the node 29; this would occur if the node 22 is not booted high.

An additional problem is that the excessive power is dissipated through the series path of the transistors 34 and 36 when the input #2 comes on to reset the circuit. This occurs because the transistors 36 and 35 are turned on at the same time, causing the output nodes 13 and the node 29 to discharge simultaneously while leaving the transistor 34 in the triode region of operation so it continues to conduct during the discharge period.

Turning now to Figure 10, an improved clock generator circuit is illustrated; this circuit eliminates disadvantageous features of the prior art circuit. The transistor 17 is connected to ground through a series transistor 37 having a gate driven by the node 20. A gated capacitor 38 connects a node 39 to the node 20, and this node 39 is precharged to (Vdd-Vt) by 4) through a transistor 40. The transistor 17 is kept cut off by precharging its source at the node 39 to (Vdd-Vt), which means that even if the node 20 floats and the transistor 37 is turned on by noise on Vss, the node 39 will have to be discharged all the way to ground before the transistor 17 could conduct.A threshold adjusting ion implant into the channel of the transistor 37 during manufacture raises the threshold voltage of this transistor to further increase the noise margin. Thus, the node 21 is well protected, and therefore the node 22 is protected from discharge, so one of the problems mentioned above is avoided.

The enhanced noise margin of the transistor 1 7 also results in better control over the delay time 14 through the delay circuit, and gives a more desired waveshape on the node 21, resembling the line 21 a in Figure 9d. The reason for this change is understood by reference to Figure 9e, where the line 20' is the voltage on the node 20 as before, the line 21 b is the voltage on the node 21, and the ;ine 39' is the voltage on the node 39.

Initially the nodes 21 and 39 are at (Vdd-Vt) and the node 20 is at ground. The Millar type capacitance consisting of the capacitor 38 is charged and as the nodes 20 begins to rise the capacitor 38 boosts the voltage on the node 39 until the transistor 37 is turned on. As the voltage on the node 20 continues to rise, the node 39 is discharged rapidly but the node 21 does not begin to discharge until the node 20 exceeds the voltage on the node 39 by a threshold voltage Vt.

At this point, time 41 in Figure 9e, the transistor 17 turns on and the node 21 discharges rapidly.

The circuit of Figure 10 provides much lower power dissipation than the prior art circuit of Figure 8. The power dissipation associated with resetting the driver stage is reduced by connecting the transistor 36 to ground through the node 29 and the transistor 35, rather than directly to ground as in Figure 8. Also, the transistor 35 has an ion-implanted channel region to raise its threshold so that the noise margin for the node 29 is improved. With the connection of the transistor 36 of Figure 10, the output 13 cannot be discharged until the gate voltage of the transistor 34 falls below the #2 reset voltage.The transistor 35 goes on first when 2 goes high, beginning to discharge the node 29, then later, when the voltage on the node 29 has dropped to a level lower than the voltage of 2 the transistor 36 comes on so the output 13 can begin to discharge. At this point the transistor 34 is cut off because its gate, node 29, is lower than its source or output node 13, and so no d.c. current path exists from Vdd to Vss in contrast to the situation in the Figure 8 circuit.

Column Address Precharge Clocks In the memory device of Figures 1 and 3, the capacitors 40 discharge with time and must be refreshed about every four milliseconds to maintain the data stored in the memory. Refresh is accomplished by applying a row address (Figure 2c) and a RAS signal (Figure 2a) but no column address or a CAS signal. The row addresses are incremented after each refresh cycle so every row is refreshed within a time period of 4 ms. In typical computer operations, long periods of time may transpire during which no CAS signal appears for a given memory chip because this chip will not be accessed for data, merely refresh.

This presents a problem for precharge circuits used for column address or associated with the CAS signal. A CAS related precharge clock internal to the chip would drop from its intended amplitude of Vdd to a value of Vdd-Vt. Any nodes that are precharged normally to Vdd-Vt by means of source followers would drop an additional threshold voltage to Vdd-2Vt. These drops in voltage could cause circuit malfunction once the CAS signal is activated after an extended period of refresh-only with just RAS occurring. To prevent this mode of failure, a RAS related precharge clock is used to keep the CAS related precharge clock pumped up to its intended Vdd value over an indefinite period of time. The usual circuitry used to generate the CAS related precharge clock is not changed by the addition of the circuit of Figure 11.This circuit makes use of the fact that CAS will be high (will not go low as in Figure 2b) while RAS will go low as in Figure 2a for a refresh cycle.

In Figure 11, #S-rnlated clock ~R#and CAS related clock OC are used. These are of approximately the same timing as RAS and CAS signals for the purpose of this explanation, and are generated by the circuitry 37 for use in precharging various other circuits within the chip.

Under RAS-only refresh operation, ~C is high, at Vdd, when bR is low during the RAS active state.

Consequently, a node 140 will be high, Vdd-Vt, prior to ~R going high. So, when 4vR goes high the node 140 will be booted above Vdd by the capacitance associated with the transistor 141, allowing the full Vdd level of ~R to be transferred to the node 142. Prior to the positive-going transition of # the node 142 is at the Vss potential of#RwhiIe the node 143 has been charged to Vdd-Vt potential through a transistor 144. OC is at Vss when #Cis high so that the transistor 145 does not prevent the node 143 from charging up through the transistor 144.

When 4)R makes its positive transition, the node 143 is booted above Vdd via the capacitor 146.

By making the size of the capacitor 146 of sufficient magnitude relative to the size of transistor 147 and any parasitic capacitance associated with the node 143, the transistor 147 can be assured of being driven into triode operation, thus assuring that ~C is kept at Vdd potential by resupplying any charge that may have leaked off of OC. The transistor 141 is used to prevent the positive-going transition of w from causing any conduction in the transistor 147 if ~C is low during other modes of operation.If ~C is low when ~R goes high, transistor 141 will be off and will not allow the node 142 to follow the bR transition. The transistor 148 is used as a capacitive isolation device such that the gate of transistor 141 can be booted above Vdd and allow the full transition of ~R to be coupled to the node 142. The transistor 145 discharges the node 133 when CAS is active, preventing any current path through the transistor 147 while ~C is low (Figure 2b). The transistor 144 is a long channel device of narrow width to keep down power consumption when ~C is high.Charging of the node 143 through the transistor 144 need only occur some time before any substantial leakage has occurred on ~C, which is consistent with a long channel, narrow width transistor 144. if the capacitor 146 is constructed as an MOS gated capacitor it is possible to delete the transistors 141 and 146 and the node 140 and connect bR bctly to the node 142. Since ~C is high when #C is low, the node 143 is held low, preventing inversion from occurring in the capacitor 146, so with no inversion region the capacitor consists only of the physical overlap of the node 143 electrode and the N+ diffusion of the node 142.

This overlap capacitance is very small compared to the inversion capacitance and the coupling to the node 143 from the positive transition of 4 > R can easily be suppressed by the transistor 145.

An example of the use of the output signal on the line 149 is in generation of clocks such as Pmf or Pm of Figure 6 for column address buffers of Figure 5 or for the ~C precharge of column decoders of Figure 12.

Column Address Discharge Circuit Referring to Figure 12, a circuit is shown for generating column select voltage for applying to the lines 74 of Figure 3. When the column address signals become valid on the lines 24, one or more of the twelve AY and AY address bits on the lines 24 will discharge the decoder output 150 for a non-selected decoder 20, 21 as seen in Figure 1 3c (left side). There are sixty-four of the decoders 20, 21 and only one will remain with its output node 150 in its precharged condition, Figure 1 3c (right side).Once all of the sixty-three non-selected decoders have settled, leaving only one decoder in its precharged condition, the Y signal of Figure 2d, applied to the line 151 from control circuitry (not shown), goes high and this voltage is applied via transistor 152 to the selected line 74 to allowthe data on addressed column lines 38a, 38b of Figure 3 to be gated out via transistors 75, 76 to the I/O lines 25, 26 and on to the I/O buffers. For the non-selected decoders 20, 21 since the node. 1 50 has been discharged the Y signal of Figure 2d is not allowed to pass through the transistor 152 and so the line 74 remains at Vss. The potential on the line 74, however, is trapped on this node with very high impedence to any other node, so the additional circuitry of this improvement is needed.

If both of a pair of the lines 25, 26 are pulled to Vss due to data from the selected sense amplifiers 11 or bit lines 38a, 38b, one of the bit lines 25, 26 goes to its high state due to data being written into the addressed cell, then coupling due to gate overlap capacitance occurs between an I/O line 25. 26 and a line 74, tending to push this line 74 toward a positive voltage above Vss. The magnitude of this voltage is a 40 in the memory cells of the array 10 have the same type of leakage as pn junctions.

When a hole-electron pair is formed, usually by thermal agitation, the electron will be attracted by the N+ diffused region or induced N region, where it is a majority carrier, and the hole will go into the substrate where it is also a majority carrier.

Electrons thus entering the storage node will tend to discharge the positive potential. In the case of a forward biased diode, such as the junction between the N+ moat region 106 and the substrate when a negative voltage is applied to the input line 105, the opposite occurs and electrons are pumped from the N-diffusion into the P-type substrate 30 as minority carriers, and holes flow in the opposite direction. Electrons injected into the P-type substrate will tend to combine with holes in the P-type material but a large number will diffuse for a length of several mils in the substrate and last for several ms.

before recombining. Storage cells in the array 10 are within the diffusion length for minority carriers from the input nodes. If sufficient numbers of the minority carriers reach a storage node such as a capacitor 40 they can completely discharge the node when captured by the depletion region surrounding the node.

A primary feature of one embodiment is the addition of the N+ diffused collection ring 123 tied to Vdd and completely surrounding the input diode created by the N+ moat 106, which is the first diode seen by an input signal. The ring 123 functions to collect a large percentage of the injected minority carriers, thereby reducing the number that reaches the storage nodes to an acceptable level. A polysilicon resistor 125 may be used in series with the line 105 coming from the input pad to reduce the current flow into the input diode and thus reduce the injection of minority carriers.

A test shows that the current flowing in the substrate due to minority carrier injection is three times as great without +5 V connected to the collector ring 123 as it is with +5 V so connected.

In the MOS dynamic RAM using the ring 123, this' reduction is sufficient to allow the circuit to operate with a -1.0 volt specification for undershoot for the input voltages on all inputs simultaneously. This has been heretofore impossible for an N-channel MOS RAM without substrate bias.

Referring to Figure 5, the left-hand part of the circuit shows the bias circuit of the invention. The input between the terminal or pad 16 and the line 106 includes a resistor R1 isolated from the substrate and a resistor R2 which is coupled to the substrate by a diode D. The resistor R2 ordinarily would be a diffused or implanted N type region in the surface of the P type single crystal silicon substrate, so the diode D is a PN junction, although it is preferable that a Schottkey barrier diode be provided at this point as it would have a lower forward bias voltage than the other PN junctions in the circuit and thus begin to conduct well before the others. The resistor R1 typically would be implanted polysilicon over the field oxide as disclosed in U.S.Patent 4,110,000 assigned to Texas Instruments, although it could be other material so long as it provides a high resistance and does not include a PN junction to the substrate nor a depletion region into the substrate beneath it. The magnitude of the resistor R1 is much greater than that of the resistor R2, and is high as the RC time constant specified for the input circuit will permit.

In operation of the input circuit, when the bonding pad 16 goes sufficiently negative, the N type moat regions of the resistor R2 (as represented by the diode D) and of the transistor 88 will become forward biased and current will flow from the substrate to the pad 16. This current flow will cause a voltage drop across the series resistance such as resistors R1 and R2, biasing the moats at a higher potential than the pad. This voltage on the moats will depend upon the current being drawn and the value of the series resistance.A negative voltage on a moat with respect to the substrate results in injection of minority carriers, some or most of which can be collected by the guard ring 123; to minimize injection of carriers into the substrate in excess of that which can be collected, the resistor R1 in series with the injecting node biases the injecting node more positive so injection is reduced. Most of the substrate-to-moat PN junction current should come from D, rather than transistors 88, 89, etc. because R2 and D are surrounded by the guard ring and located on the edge of the chip away from critical circuitry; with most of the diode current coming from D, R1 should bias the node N close to the forward bias voltage or about -0.6 V.

The resistor R3 is optional; this resistor will further bias the nodes downstream of N closer to the forward bias voltage. Since R2 is supplying most of the current, any additional current supplied by the moats associated with the buffer will bias the node 106 even more positive than the node N, so injection will be even less than if it were at the voltage of node N 1.

Referring to Figure 5, the right-hand part of the circuit illustrated is a voltage reference generator according to another feature. The line 105 and Vref input are connected to an output node 130 for a source follower which includes a driver transistor 131 along with a long chain of load transistors 132. The gates of all of these transistors are connected together and to a node 133. The series source-drain paths of transistors 131 and 132 are connected between Vdd and Vss. The level on the output node 130 is somewhat more than a threshold voltage lower than that on the internal node 133. The long chain of transistors 132 function as a single transistor with a long, narrow channel, i.e. a low width to length ratio. In a preferred example, seventeen identical transistors of the standard size make up the chain of load transistors 132.

The source follower merely functions to increase the current output capability of the reference voltage generator. The node 133 cannot be loaded with any appreciable current drain.

However, the source follower introduces a voltage drop, so the voltage on the node 133 is adjusted accordingly. Three sets of transistors 1 34 with gate shorted to drain are connected between the node 133 and Vss so the drop across this combination is about 3Vt. Each set includes three standard sized transistors in parallel to increase the effective width to length ratio. Another long chain of transistors 1 35 is connected between the node 133 and Vdd. These have all of their gates connected to Vdd, so the chain functions as one transistor of very low channel width to length ratio. In one preferred example, there are thirty-six transistors 135 in series. The advantage of using multiples of a standard sized transistor is that the transistor is known and extensively characterized so its specifications are predictable.Any factor or process variation which affects one will affect the others in the same way. As described thus far the circuit is substantially the same as in the prior art.

The variation in the output voltage at the node 86 with changes in the supply voltage Vdd and the threshold voltage Vt is illustrated in Figure 8.

According to the invention, a compensating circuit consisting of three transistors 1 36 is connected to the node 133 in order to flatten out the curves of Figure 8, particularly for low Vt levels. The source-to-drain paths of the three transistors 136 are connected in series and the series combination is connected between Vdd and the node 133. The gates are individually connected to the drains of the transistors 136.

This compensating circuit is cut off at high threshold values so it has no effect in the circuit operation; the voltage drop from Vdd to node 133 is not great enough to exceed the three Vt drop of the three transistors. For low threshold values, the transistors 136 will conduct, holding up the node 133 voltage. At Vdd of 5V and Vt of 0.117, Vref is 1.53 with the compensation transistors 136 but only 1.08 without it, for example. The demarcation line in the graphs of Figure 8 is the point at which the transistor 136 begins to conduct. As the threshold voltage varies in different manufacturing lots, and the supply voltage varies under changing operating conditions, the Vref stays much more constant so the inputs to the memory device of Figure 1 will be much more correctly responsive to the standard TTL levels.

The Clock Generator: With reference to Figure 8, a prior art clock generator circuit will be described; an improvement on this circuit to solve some of the inherent problems as will be explained. These may be used in Figure 1 in the generator 37 to produce the clocks of Figure 4.

The clock generator circuit of Figure 8 receives a clock input 1 at an input terminal 10, and receives a second clock input O2 at input terminals 11 and 12 to produce a clock output 3 at an output terminal 13. The leading edge of the output 3 is delayed by a time period 14 from the leading edge of the input 1, as seen in Figures 9a and 9b; this delay is introduced by a pair of stages including the transistors 16 and 17. The output 4)3 terminates when the input @2 goes high, so the trailing edge of 3 almost coincides with the leading edge 2.

In the delay part of the circuit, a pair of transistors 18 and 19 having their gates driven by $function to discharge a node 20 to Vss before an operating cycle begins, and to charge a node 21 to (Vdd-Vt). A node 22 is also precharged to (Vdd-Vt) via an isolating transistor 23. The remainder of the circuit functions as a driver. The node 21, precharged high, holds the gates of transistors 24 and 25 high during O. So long as the transistor 25 is conductive the output 13 is held low. When the input O1 starts to go high at time 26, the node 22 is booted by the gate to drain capacitance of the transistor 27.The voltage on the node 22 is seen in Figure 2c as a line 22'; this voltage stays high throughout the period 28 which is the rise time of the input cD1 , so the transistor 27 stays in the triode region of operation during this period. As a result, the voltage on a node 29, seen in Figure 9c as a line 29', will almost track the leading edge of the input $1. This voltage 29' charges a bootstrap capacitor 30 in the driver stage to the Vdd level, and primes the driver stage so that it may produce an output when the voltage 21' on the node 21 discharges. During the rise time 28 for 1 1-the node 21 remains high due to the delay in charging the gate of the transistor 1 7 through the transistor 16.This holds the node 31 and output 13 down because the transistors 24 and 25 are held on, allowing the capacitor 30 to charge through the transistor 24. The transistor 23 is maintained near cutoff so charge will not be lost from the node 22 during the period 28. Near the end of the rise time 28, approximately at a time 32, the node 21 begins to be discharged by the input 1 propagating through the delay transistors 1 6 and 17, as seen by the line 21' of Figure 2c. This discharges the node 22 through the transistor 23, seen by the line 22', so the transistor 27 turns off and the node 29 is isolated with a voltage of about Vdd at this time as seen by the line 29'. When the node 21 discharges, the transistors 24 and 25 turn off, and so the node 31 and the output 13 can rise quickly toward Vdd by conduction through the transistors 33 and 34. As the node 31 goes toward a higher voltage, the node 29 is boosted to a level higher than Vdd via the capacitor 30. This causes the drop across the transistor 34 to be virtually zero, so the output 13 goes to Vdd.

The circuit is reset by the input o2 which occurs before 4 > goes high for the next cycle. If the circuit need not be reset prior to 4 > . then the @2 inputs 11 and 12 are not needed. When O2 goes high, the transistor 35 is turned on by the input 12 and this discharges the nodes 29, turning off the transistors 33 and 34. At the same time, the function of the overlap capacitance between the lines 25, 26 and the line 74 via transistors 75, 76, the parasitic capacitance associated with the line 74, and the magnitude of the voltage swing on the I/O line 25, 26. Since the line 74 is of high impedence to Vss, this voltage remains capacitively stored on the line 74 and will only dissipate due to normal P-N junction leakage.If the magnitude of this coupled voltage on a line 74 is sufficient, it can cause gradual discharge of one of the column lines 38a, 38b. If the active cycle is of sufficient length of time, this bit line can become discharged toward Vss, causing the selected storage cell to lose the high state which is to be written into it.

For a high speed dynamic RAM, the time interval between the node 150 going low as in Fig.13c and the Y signal going high as in Figure 13d is made as short as possible consistent with proper operation. If on some devices this time interval should be reduced due to processing variations, a small positive voltage could be trapped on a line 74 before discharge of the node 150 is completed. This small voltage to that coupled to the line 74 is described above. This condition can cause poor yields and pattern sensitivities that show up only at certain timing or temperature conditions.

Accordingly, to correct these problems, the circuit of Figure 12 employs a discharge transistor 1 53 connecting each of the sixty-four lines 74 to Vss with a Y signal as in Figure 13e applied to its gate through a series transistor 154. The gate of the transistor 154 is connected to the node 150.

For the unselected decoders 20, 21, the discharge of the node 150 precedes the discharge of Y to Vss. This causes a positive voltage well above Vt to be trapped on the gate of the transistor 1 53 since the transistor 154 is turned off before Y goes low. The transistor 153 is therefore on and presents a low impedence path to Vss for discharge of any voltage that may be on or be coupled onto the line 74. This prevents the gradual unintentional discharge of a column line and loss of data in a write operation. For the selected decoder 20, 21, the node 150 remains in its precharged or high condition so that the transistor 154 is on when Y goes to Vss. Thus the gate of transistor 1 53 goes low withnnd the transistor 153 turns off, so the line 74 can follow Y as it would normally for a selected decoder.

While this invention has been described with reference to an illustrative embodiment, this description is not intended to be construed in a limiting sense. Various modification of the illustrative embodiment, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to this description. It is, therefore contemplated that the appended claims will cover any such modifications or embodiments as fall within the true scope of the invention.

Claims

1. A high-speed semiconductor read/write memory device formed in a single integrated semiconductor circuit in a face of a semiconductor body comprising: an array of rows and columns of memory cells having a single transistor and a single capacitor for each cell, a sense amplifier connected to a pair of sense nodes at the centre of each column, a plurality of high-speed buffer circuits each having an input connected to receive an address bit from external to the device and an output, decoder means connected to receive said outputs from the buffer circuits and functioning to select said rows and columns according to the address bits, clock generator means having inputs connected to receive input controls from external to the device and functioning to generate clocks for operating said sense amplifiers and said decoder means, all of said circuitry operating on a single lowvoltage supply input to the device.

2. A sense amplifier for the semiconductor memory device of claim 1, comprising: a pair of cross-coupled driver transistors, a pair of coupling transistors, a pair of grounding transistors, and a pair of pull-up transistors, each of the transistors having a current path and a control electrode, means connecting the current path of each of the coupling transistors in series with the current path of a separate one of the driver transistors between one of the sense nodes and a grounding node and connecting the current paths of both of the grounding transistors in parallel between the grounding node and reference potential, the current paths of the pull-up transistors being connected separately between the sense nodes and a supply of a given voltage level, means for precharging the sense nodes to said voltage level prior to an active operating cycle, means for addressing memory cells in the array at a given time in the beginning of said operating cycle, means for applying a clock voltage to turn on one of the grounding transistors at a first time subsequent to the said given time beginning an active operating cycle and for applying a clock voltage to turn on the other of the grounding transistors at a second time subsequent to the first time, said one of the grounding transistors being much smaller than the other of the grounding transistors, coupling means separately connecting the control electrodes of the pull-up transistors to the sense nodes, the coupling means being~ conductive only for a given voltage differential during the active operating cycle, means to boost the voltage on the control electrode of one of the pullup transistors to higher than said voltage level at a time in the active operating cycle just following the second time, means to maintain the voltage on the control electrodes of the coupling transistors at higher than said voltage level prior to the beginning of active operating cycle and shifting the level to said voltage level during the active operating cycle.

3. A memory device with a sense amplifier according to claim 2 wherein all of said transistors are insulated gate field effect transistors, the current path of each of the transistors being a source-to-drain path and the control electrode being a gate.

4. A memory device with a sense amplifier according to claim 3 wherein the coupling means are insulated gate field effect transistors, and a voltage is applied to the control electrodes thereof to define the conductivity thereof, and wherein said voltage differential is about two threshold voltages for the field effect transistors.

5. A memory device with a sense amplifier according to claim 1 wherein the voltage on the control electrodes of the coupling transistors is higher than said voltage level until said first time in an active operating cycle.

6. A sense amplifier according to claim 1 wherein the means for precharging comprises a pair of precharge transistors having current paths separately connecting a precharge node to said sense nodes.

7. A sense amplifier according to claim 6 wherein the precharge node varies in voltage from said voltage level to an intermediate level then to reference potential during an active operating cycle then slowly rises back to said voltage level after an active operating cycle.

8. A high-speed buffer circuit of improved noise immunity for the semiconductor memory of claim 1 comprising: a bistable differential voltage detector having first and second field effect transistors, each having a source-to-drain path and a gate, the gates of the first and second transistors providing inputs to the detector, means for coupling an input terminal to the gate of said first transistor, means for coupling a reference voltage to the gate of said second transistor, a pair of output transistors each having a source-to-drain path and a gate with the sourceto-drain paths being separately connected in series between the source-to-drain paths of the first and second transistors and a clocked supply voltage, third and fourth field effect transistors each having a source-to-drain path and a gate, the source-to-drain paths of the third and fourth field effect transistors being separately connected from the gates of said pair of output transistors to reference potential, means for improving noise immunity including means for increasing the threshold voltages of the third and fourth transistors to a level significantly higher than that of said pair of output transistors.

9. A circuit according to claim 8 wherein the detector has a pair of capacitors separately connected at one end to the gates of said first and second transistors, the other end of the capacitors being connected to ground rather than to a supply voltage.

10. A circuit according to claim 8 wherein the detector includes a pair of field effect transistors each of which has a source-to-drain path in parallel to a separate one of the first and second transistors and has a gate cross coupled to the drain of the opposite one, said pair of transistors having a threshold voltage about the same as that of the first and second transistors.

11. A circuit according to claim 8 wherein the threshold voltage of the first and second transistors is significantly less than that of an enhancement in the enhancement mode field effect transistor.

12. A circuit according to claim 9 wherein the gates of the third and fourth transistors are separately connected to the drains of the first and second transistors.

13. A circuit according to claim 10 wherein the threshold voltage of the third and fourth transistors is significantly higher than that of the pair of output transistors and the threshold voltage of the first and second transistors is significantly lower than that of the pair of output transistors.

14. A circuit according to claim 8 including fifth and sixth field effect transistors, each having a source-to-drain path and a gate, the source-todrain path of the fifth transistor coupling the reference voltage to the gate of the second transistor, the source-to-drain path of the sixth transistor connecting the input terminal of the gate of the first transistor, and a clock voltage source connected to the gates of the seventh and eighth transistors and having a trailing edge occurring prior to said clocked supply voltage.

1 5. An input circuit for the semiconductor memory according to claim 1, comprising: a bistable differential voltage detector having first and second field effect transistors with gates of the transistors providing inputs to the detector, a third field effect transistor having a sourceto-drain path coupling an input terminal to the gate of one of said transistors, the source-to-drain path including a heavily doped region in said face of one conductivity type opposite that of subjacent material, a guard ring of said one conductivity type surrounding said heavily doped region but spaced therefrom, with means connecting the guard ring region to a voltage supply.

16. A circuit according to claim 15 wherein the body of semiconductor material is predominantly P-type, the field effect transistors are N-channel, and the guard ring is N+.

17. A circuit according to claim 15 wherein the semiconductor body includes a large number of capacitive type storage cells near the input terminal, and the guard ring region prevents minority carriers injected at said heavily doped region from reaching the storage cells.

18. A circuit according to claim 15 wherein the third field effect transistors is surrounded by the guard ring region but the first and second field effect transistors are outside the guard ring region.

19. A circuit according to claim 1 wherein the voltage supply is about +5 volts.

20. A circuit according to claim 15 wherein no substrate bias is applied to the semiconductor body to reverse bias the Pn junction between said heavily doped region and the body.

21. An input circuit for the semiconductor device of claim 1, comprising: a controlled switching device having a current path and a control element, the switching device including an input region in the face of the body of one conductivity type opposite that of subjacent semiconductor material, a protective region surrounding and spaced from said input region and composed of said one conductivity type to collect minority carriers injected into the body from said input region, and means connecting the protective region to a bias voltage.

22. A circuit according to claim 21 wherein the current path of the switching element is in series between an input terminal for the semiconductor device and utilization means on the face of the body.

23. A circuit according to claim 22 wherein the switching device is a field effect transistor and the current path is a source-to-drain path, the input region being part of the souce-to-drain path.

24. A circuit according to claim 23 wherein the utilization means includes a gate of a field effect transistor located on said face outside said protective region.

25. An input buffer circuit for the semiconductor memory device of claim 1 wherein the device has a large number of enhancement mode transistors, the buffer circuit comprising: a bistable differential voltage detector having first and second field effect transistors with the gates of the transistors providing inputs to the detector, means for coupling an input terminal to the gate of one of said transistors, said first and second field effect transistors having a threshold voltage significantly less than that of said enhancement mode transistors.

26. A circuit according to claim 25 wherein the detector has a pair of outputs, and third and fourth field effect transistors having gates connected to said output.

27. A circuit according to claim 25 wherein the detector includes a pair of field effect transistors each of which has a source-to-drain path in parallel to a separate one of the first and second transistors, each of said pair of field effect transistors being cross-coupled with the other and having a threshold voltage about the same as that of the first and second transistors.

28. A circuit according to claim 25 wherein the gates of said first and second field effect transistors do not have boosting signals coupled thereto for raising the input level, and wherein no substrate bias is provided for the transistors.

29. A memory device according to claim 1 including a clock generator circuit comprising: an input for receiving a reference clock voltage; a delay circuit connected to the input and producing a delayed voltage at an output; a driver circuit connected to receive said output and producing a high level delayed clock voltage; the improvement wherein the delay circuit includes a pair of controlled switching devices each having a current path and a control element, the current paths of the pair of switching devices being connected in series between said output and a reference potential, the control elements of the pair of switching devices being connected together and coupled to the input, means for separately precharging said output and a node between the current paths of the pair of switching devices prior to an operating cycle.

30. A memory device according to claim 1 including a clock generator circuit comprising: an input for receiving a reference clock voltage; a delay circuit connected to the input and producing a delayed voltage at an output; a driver circuit connected to receive said output and producing a high level delayed clock voltage at an output terminal;; the improvement wherein the driver circuit includes a pair of controlled switching devices each having a current path and a control element, the current path of one of the pair of switching devices being connected between said output terminal and a high voltage node, the current path of the other of the pair of switching devices being connected between said high voltage node and a reference potential, the control elements of the pair of switching devices being connected together and to a reset clock voltage occurring after said delayed voltage.

31. A circuit according to claim 29 or 30, wherein the pair of switching devices are insulated gate field effect transistors, the current paths are source-to-drain paths, and the control elements are gates.

32. A circuit according to claim 31 wherein another switching device has a current path connecting the output terminal to reference potential and a control element connected to receive the delayed voltage.

33. A circuit according to claim 32 wherein the switching device having its current path connected between said high voltage node and reference potential is ion-implanted to provide a higher threshold voltage than the other of the pair of switching devices.

34. A circuit according to claim 31 wherein the driver circuit includes a third switching device having a source-to-drain path connected between a voltage supply and said output terminal and having a gate connected to said high voltage node.

35. A circuit according to claim 34 wherein means are provided for charging said high voltage node at a time prior to said delayed voltage.

36. In a memory device according to claim 1, an input circuit comprising: an input terminal on the face of the semiconductor body, a voltage detector having a first field effect transistor with a gate of the first transistor providing an input to the detector, a first resistor on said face but not forming a PN junction with the body, a second resistor on said face and forming a junction with the body, a second field effect transistor having a sourceto-drain path, the source-to-drain path, including a heavily doped region in said face of one conductivity type opposite that of subjacent material, coupling said input terminal to the gate of said first transistor, and a guard ring of said one conductivity type separately surrounding said heavily doped region and said second resistor but spaced therefrom, with means connecting the guard ring to a voltage supply.

37. A circuit according to claim 36 wherein the semiconductorbody includes a large number of capacitive type storage cells near the input terminal, and the guard ring prevents minority carriers injected at said heavily doped region from reaching the storage cells.

38. A circuit according to claim 36 wherein said second resistor is more remotely located away from said storage cells than the heavily doped region.

3,9. A circuit according to claim 37 wherein the voltage supply is about +5 volts and no substrate bias is applied to the semiconductor body to reverse bias the PN junction between said heavily doped region and the body.

40. A memory device according to claim 1 containing a reference voltage generator circuit comprising: a plurality of control devices each having a current path and a control electrode, a first set of the control devices having current paths connected in series with one another between a voltage supply and a node, the control electrodes of all of said first set being connected in common to said voltage supply, a second set of the control devices having current paths connected in a series/parallel array between said node and reference potential, the control electrodes of each of the control devices of the second set being connected to one end of the current path of such control device, and a compensating circuit including a third set of the control devices much less in number than the first set and having current paths connected in series between said voltage supply and said node, the control electrodes being connected on one end of the current path for each of the control devices of the third set.

41. A circuit according to claim 40 wherein the control devices are insulated gate field effect transistors, the control electrodes are gates, and the current paths are source-to-drain paths; including a source follower circuit having an input connected to said node; wherein the source follower circuit comprises a plurality of field effect transistors each having a source-to-drain path and a gate, the source-to-drain paths being connected in a series between a voltage supply and reference potential, the gates being connected together and to said node.

42. A circuit according to claim 40 wherein each one of the control devices has a current path of the same size and shape as the other of the control devices; wherein each one of the field effect transistors has a source-to-drain path of substantially the same width-to-length as that of the other of the field effect transistors; wherein the course follower has an output connected as one input to a differential input detector for a semiconductor memory device; wherein the other input of the detector is connected to an input terminal of the memory device; wherein the input terminals of the memory device have TTL logic levels applied thereto and the nominal voltage at the output of the source follower is + 1.5 V; wherein said voltage supply is about +5 V.

43. A memory device according to claim 1 wherein row and column address inputs to said buffer circuits are multiplexed, and a row address strobe signal is applied to the device for column addresses; wherein the data in the capacitors is refreshed by applying row address and row address strobe without column address strobe; and wherein a circuit is included for generating a precharge clock for column address which is held at a high voltage level by pumping in response to the row address strobe.

44. A memory device according to claim 1 wherein the decoder means includes a column decoder producing an output to a plurality of output actuator lines, and means for positively discharging said output actuator lines when not selected by the column decoder to prevent unwanted build-up of voltage thereon.

45. A memory device according to claim 1 wherein the row line for a selected row is driven to a voltage higher than said supply input.