JPS58181319A - Timing generating circuit - Google Patents

Abstract

PURPOSE:To eliminate the dispersion in the leading of input pulses and the fluctuation, by detecting that a gate voltage of a power supply voltage MOSFET receiving the input pulse reaches a prescribed value and switching other MOSFEs from on to off. CONSTITUTION:When an input pulse phiIN rises to a high level, charge-up is done to a bootstrap capacitance CB through the MOSFETQ5. As a voltage of a node N1 rises, the MOSFETQ6 is turned on and the voltage of a node N2 rises. The gate voltage of the MOSFETQ5 rises with the self-bootstrap operation and the input pulse phiIN is given to the node N1 without causing any level loss. When the voltage of a node N2 exceeds a threshold voltage VTH of the MOSFETQ9, the MOSFETQ9 is switched on and the MOSFETQ7 is switched off. The node N2 is changed to a low level and the MOSFETsQ2, Q4 and Q5 are set off.

Description

[Detailed Description of the Invention] This invention is based on MO8PI? (insulated gate type zone effect transistor)

A timing generation circuit as shown in FIG. 1 was conceived prior to the present invention.

The configuration of this circuit is as follows. Transmission game Ren) M O8F K T Q 11'9 is a manual pulse φ, or 1, MO8F of source voltage (Voo)till
This is reported to KTQI's Kate. This MO8FKTQ-
A bootstrap capacitor CB is provided between the gate and the source. In addition, the ground potential 111iMO8FETQ connected in series to the MO8FETQ+, *
Or is provided. Above MO8jKTQt +Ql
and the gate source voltage V is made common to n1. The output MO8F” T is connected in series between 0 and ground potential.
Q * * Q 4 are provided.

In order to secure the charge-up time to the foot strap capacity oB mentioned above, the following: M extension circuit e is constructed above 5M.
OS F E T Q Suga, Q, 4 and UQs 't)i
WjlJ (m is n.Manual pulse φ work, r receiving power supply voltage -1 0s FETQ+* and precharge (reset) pulse sr spending ground potential @M08FKTQ,,,
are connected in series. This series MO8PK! T
Qtm.

The ground potential lIIIM that receives the signal from the alarm point of all
9 to O8FlteQzB and the above precharge pulse φ'.
Power supply voltage 11M o s y K 'r qIa-
1tLI column type uVc connected. Then, the delayed signal from the connection point II of this series MO8FET Q+Q+i is transmitted to the gate of the upper kJMO8νITQ,,Q, on one side, and on the other hand, the power supply voltage V is applied to the gate. .

MO8FKTQttk and the above M
It is transmitted to the gate of O87ITQi.

On this (b) road, the above 1g08F]! jTQ+
l.

Because the above delay time (charge-up time to capacity * Cs) is uniquely fixed due to Q・S, etc.,
The following drawbacks t-1ir.

11 I K% Above MO8FITQs If the rise of the photoelectric voltage to the disconnected bootstrap capacitor oB is fast as shown in Fig. 2, the potential of node N rises at the peak, so M O8 ? B T Q t *q
, and as the electricity flowing through QleQak becomes larger and the consumption of electricity increases, the output pulse φ becomes a trap. When the low level of +7T rises to high level 911K, the low level margin cannot be secured. On the other hand, as shown by the dots in the figure, if the rise of the charging voltage is slow, the level of the charging voltage will be insufficient, and the output pulse φ. UT's startup 9 is also delayed.

This means that even if the rise of the manual pulse is constant, MO8FIITQI and QCs + QCs
Since the rise and delay times of the node N vary due to the variation in the node N, the above-mentioned sympathy problem arises.

Second, the output pulse φ with respect to the human power pulse φ. +7
When trying to set a large delay time of T, it is difficult to match the photoelectric time to the node N with the delay time, and it is greatly affected by variations in device characteristics.
Actually, the dust makes it extremely difficult.

Thirdly, if the rise of the human power pulse changes, due to the reasons mentioned in Section 1, the current consumption increases, the low level margin is insufficient (Kkft'), and the driving capacity of the output hull x becomes insufficient. Therefore, stable operation as desired cannot be expected.

The purpose of this invention is to reduce the variation in the rise of human pulses,
It is an object of the present invention to provide a timing generation circuit that is not affected by fluctuations.

Another object of the present invention is to provide an output pulse that has a large delay time with respect to an input pulse. Timing generation circuit that can be obtained? It is about providing.

Further objects of the invention will become apparent from the following description and drawings.

Hereinafter, this invention will be explained in detail along with a first embodiment.

FIG. 3 shows a gl diagram of an embodiment of the present invention.

In this embodiment, MO8F older brother TeQ1 shown in FIG.
The following process is applied to the bootstrap output circuit consisting of Ql and bootstrap valley it Os.
or may be provided. That is, the implementation column circuit of FIG.
The voltage detection means described above is provided in place of the slow circuit shown in the figure.

Upper 1kl: MO8PK'rQ, gate voltage? Receives power supply voltage - MosymTQsK@column form with ground potential 111
M08FKTQy is connected. This MO8FIT
Q, and the gate and drain are crossed with each other and a ground potential fog MO8FKTQ- is provided. This M
The voltage 1111MOlilFKTQs is connected in series with OBPETQe and receives the precharge pulse φ.
Or is provided. Also, the above MO8IF11iTQyK
are connected in parallel n MO8PETQ+ receiving the above precharge pulse φ.

Or is provided. And the above MO8: EFKτQ,
Either the drain output signal or the above button 0EIFK.
TQ*, Ql (transmitted to the D gate r1 On the other hand, the power supply voltage V... or cut MO8 applied to the gate
It is transmitted through the FEITQIl meeting to the gate of the MO8FputQs.

The operation of this actual 2111i91.1 circuit will be explained using the timing diagram KW shown in FIG.

JMMO8νl with high level precharge pulse
T Q @ * Q @・ is on. Once, MOBIXTQs was turned on and MO8F'KTQ was turned off. By turning off this 4DMO11FITQ document, the MO
MO87 is used for the gates of 8FIIIiQllQ4 and Ql.
ITQ, the tram voltage Voo-V□(MO
8FI? These MO8FICTQ*, Ql and la are precharged to the threshold DC voltage) level.
Turn on w or b.

Therefore, the output pulse φ. U'ril''t1 becomes low level and fakes.

After the above precharge pulse φ has a low level margin, when the manual pulse rises to high level, MOB
IXTQs kA is used to charge up the bootstrap capacitor On.

According to the voltage rise of this node N, MO8FETQ@T
Since the Ql inductance increases when H is turned on, the voltage at the node N increases in accordance with the ratio to the conductance of the MO8PET Q7 which is turned on. Further, the voltage immediately applied to the channel of mosFKTQs that is turned on increases as the voltage of the above-mentioned manual pulse generator increases.

Once, during the above precharge period, MO8FITQ
Since the MO8 capacitance between the gate electrode and the channel of
The gate voltage of O8FITQs increases and the human pulse -
Node NIK is transmitted without loss of engineering or level. When the footstrap voltage rises above the power supply voltage, MO8FITQ+I+'' is turned off to prevent the bootstrap voltage from flowing out.

Then, when the voltage at the node Nl exceeds the threshold direct voltage "rHk" of MO8FETQ, MOEIFETQ9 is switched from off to on.At this time, the positive feedback loop of MO8PITQ? Work 9, steeply MO8FKTQ1. or ON, MO87K
TQT is provided off-VC9J.

Once, node N changes to low level, so
MO811 TeQ Karasu +Q4 and Ql or off. This A
Pootstrap effect JJ from K? Accordingly, the output pulse φ. , :I? rises to a high level.

Also, when the voltage at the υ node N increases due to the bootstrap effect mentioned above, MO8FICTQs becomes OFF state 11! IC
Therefore, it is possible to prevent the bootstrapped voltage of 9 MI from being lost to the human power pulse φ□, 11.

In this actual model, the level of the charge-up voltage to the bootstrap capacitor CB is shifted according to the conductance ratio of MOBPETQe and Qa, and MO8IFITQ
A voltage ratio test is conducted using the -threshold direct voltage VTH' as a reference voltage. Accordingly, by setting these circuit constants HA and P1, the Pootstrap circuit can be activated at the optimal timing. Therefore, even if there is a fluctuation in the human power pulse φ, it is possible to follow this and maintain a low level margin and sufficient total driving force ta without causing any more than necessary current loss.

In addition, for Hekapulse φ machining, there is a large slow grinding time nott.
lcapulse φ. CF? ``If you want to obtain this, it can be realized very easily by making the conductance tube of MO8PKTQ smaller and by slowing down the pulse φ itself.

Furthermore, the charge-up voltage to the Pootstrap capacitor aB? By monitoring and controlling the operation timing of the bootstrap [giwI], the influence of device variations is greatly reduced, and a large degree of design freedom is obtained.

This 1N! Although the circuit of this embodiment is not limited to any particular extent, it can be used as a timing generation path in a dynamic RAM (hereinafter referred to as D-RAM) as described below.

Figure 5A shows a partial circuit diagram of a D-RAM to which the present invention is applied.

In the circuit shown in the fgSM diagram, the N-channel M08FI
N channel GFICT (engineering n5) is assigned to CT1.
ulated-Gate FLeld ]Cffect
Transl-Btor) kshiotlK and explain.

1-bit M-01L consists of a capacitor C for information storage and MO8F]CTQM for address selection, %1
The information of # and 'O# is stored in the form of capacitor CBKtfj.

To read out the offset signal amount information, use MOS P KT Q, koN.
This is done by connecting #c column data #DL to #c and sensing what kind of change occurs in response to the potential of data fIIDII or the charge accumulated in #0. The potential 'tt source voltage voltage that was previously charged in the floating capacitance CO of data #DL.

Then, the information stored in CfI is 't' (vo
.

potential), data @D at address time
The potential (VD,)%□〃 of I is V. . T with the potential of
Or if it's '0' (OV) then (Vl)%
1 l is ('011vGo 'II (VW-vth
))/'O.

However, vl is M, O! The gate voltage of lFBTQM is the voltage of VthuMO8FllTQM.

Here III! The difference between l'l' and logic 10', that is, the detected signal amount mV, is Δvs = (vDL)1' (vDb door o' = (vw
”th)・Cs/C.

becomes. When V, = Voo, the signal amount Δv8 becomes Δ
vll=(voa “th)”0810°.

Since the memory cells are small and many memory cells are connected to common data, it is possible to create a highly integrated memory matrix. , 0F110o becomes a very small -. Therefore, Δva is a signal with very little tracking.

Is this a standard signal for reading? Dummy cell D-011 as a standard for detection! L is used. D-ORr, Fi
*Yapashita CD is made under the same manufacturing conditions and design constants as M-OJItL, except that the volume is 11 or half the size of CB. cds is MO before address
8FKTQDIK connects the photoelectric to ground potential (the other 11L
The pole is vo. (fixed to) Therefore, the signal change amount Δv3 applied to the common column data dDL at the time of addressing is gradually changed by the following equation with that of the memory cell (ΔV8) by lWJ. However, vDW is the M8PITQplO gate voltage, and Vth'1 is the I/h1 voltage of the M08FETQD.

Δvl"(vDW-vth')"cd, /c.

When vDW=v0°, ΔVR is calculated by the following equation.

ΔvR=(vo.−vth′)·cd8/c.

As mentioned above, "da" is set to about half of 08n.

Therefore, tyo of Δ716ΔvB is half the truth.

Therefore, whether the level modification given to the data #DL of the memory cell is smaller than that of the dummy cell (ΔvR) is %11, %ol information i=f'll, WIJr!
Is the layout of each circuit 8AI the path of such a potential change during address?
, timing signal (sense amplifier control signal) φ −c'
It is a sense amplifier that expands during the sensing period (the details will be described later), and its input/output nodes are connected to the nine phase data 1DL1-t and DLt-+, which are arranged in parallel. . Data #DL1 (+
D-I-MKH is made equal to the number of memory cells combined to increase the detection limit, DLI I + DLI t
(1) One dummy cell is connected to each of them.

Further, each memory cell is coupled between one word #WL and one of the complementary pair data. Since each word forest WL#'i intersects both data line pairs, even if the noise component generated in the word forest WL is coupled to the data line,
The noise component is equally distributed between both data blocks, and is canceled out by the differential sense amplifier 8A.

If a pair of complementary data DL, , DL, , are selected, a pair of dummy words DWL,- are selected so that a dummy cell is always connected to the other data cell. One of Otori and DWLII is selected.
Ru.

Operation of the sense amplifier This sense amplifier SA is a pair of cross-coupled MO
8P K T GL8s and Qss k, and due to their positive feedback action, the value of the small signal increases dynamically.

This positive feedback operation is started at the same time as the start of power supply by M O8F RT Qs+o or timing signal (sense amplifier control ia signal) φa, and based on the potential difference given during addressing, the data potential (vH
) is the transport speed, and the lower one (Vl) is descending at a high speed while the difference between the two is widening. In this way, when V falls to the threshold L/'hwi voltage V□ of the cross-coupled M8FlfT, the positive feedback operation ends, and the fall of vH is vo. While remaining at the b potential which is smaller and larger than VTh, ■L eventually reaches Ov as 1jIk.

The memory cell 111 that is destroyed during addressing is the potential of vH or vTJ obtained by this sensing operation? Uke is recovered (rewritten) by taking K.

Theory jl'l' level compensation However, Vyo or V. . If the value falls below a certain level, an error will occur that will be read as an error after reading and rewriting several times. The active restore circuit AR is provided to prevent this malfunction.
'A move to boost to 11th place. 0811 and OB
The eye is an M type 8 type variable capacitance element whose static capacitance t changes according to the voltage applied to the terminal KEfln on the left side of the figure.Logically, the threshold voltage vThr is a high voltage as a reference. It should be understood that a capacitor can be used, and a capacitor cannot be used at a lower voltage.

Timing signal (active restore control No. 15) φr
gVc MO8FITGL84, Qs,'t)
54, the capacitive element CB is photoelectrically activated to allow the data string at the potential of vH to pass, and then when the timing signal (active restore control signal) φr8 becomes high level, the M module belonging to that data string is activated. 8FK T Qss or QE+7 gate potential or V. The potential of pvH, which is smaller than 0 p, is turned to 0°. This incident, Qas,
Qsy power loss/J1 and T6* each V?
h is set smaller than that of the bone mound MO8FET.

The time-based operation of the D-RAM transistor circuit will be explained with reference to the timing diagram of FIG. 5B.

Read operation precharge period φ1° or high level (higher than voo) MO8
FMTQ81-Qll- or interrogation, complementary data 1 pair DL
The floating gtco of I 1 + DL+-H is precharged to 0 to V . Konoto-MO8FKTQ8. are conductive at the same time, so even if an imbalance occurs in the precharging by QB@*Qss, the complementary data line pair DLI l +
DL, , and are short-circuited and set to the same potential condition.

MO87ICTQsi” and other Qs themselves have their respective sources.
MO8 with no markings to prevent voltage loss between drains
The FETK ratio is set to a low value.

At this time, the timing signal (discharge control signal) φ
By 1°K, the MO8FETQ (1* or conductive redder cell D-OWL) is similarly reset to a predetermined state.

Row address period timing signal (address buffer control signal) φAll
The row address signal Ao supplied from the address barafam DB at the timing of 1. rh L, A1 is decoded (M
At the same time as the rise of the n word 1 control signal φ, the memory cell D-0KL and the cell D-○KL7)"
1/twisting starts n, 6°, resulting in complementary data pairs DL, , , DL, .

As mentioned above, a voltage difference of approximately Δv8/2 is generated between the two cells based on the content of the self-admiration in the memo I cell.

Sensing timing signal (sense amplifier te11 @signal) φ1
At the same time as the MO81F starts to conduct TQstol' due to □, the sense amplifier 8Al starts a positive feedback operation r, and a detection signal of 9ΔV B / 2 is generated at the time of address. Amplify.

After the amplification operation is almost completed t, the timing signal (active restore control signal) φ, 6+m] is activated as described above.
Active restore time INIART1'' logic% 11 level 1: tVo.

Data output operation timing signal (address/(Software 1l111j841
eccentric sign) φ,. Address Nokutsufa ADB in sync with; 6
>Input column address signal M1+ or A
j is decoded by row/column decoder RO-DOR n1?
y,, is selected by the timing signal (column switch system signal) φ K at the t column address! Storage information of memory cell M-011L or column switch Q
- Common data fusion through 8Wl meeting OD L 1 +OD
It is spread to L.

Next, the main amplifier/data output buffer 0/DOB operates according to the timing signal (data output) (signal and main amplifier control signal) φoPK, and the output terminal of the chip receives the storage information to take up the gap. Send to UT. Note that during writing, OA&DOB is set to a timing signal (data output) (signal control signal) φR1.

Write operation row addressing period precharge, addressing, sensing - operation is 11
1: This is exactly the same as the heel setting operation of II5. Therefore, the pair of mutual data DL1, DLa, 4C is manually written information (DLnt)--the memory information of the empty cell to which convolution is to be performed is read out.

Since this information li1 is to be converted to Kurotsubaki by the convolution operation described later, it can be assumed that the operation up to this point has essentially been the selection of the row address. In synchronization with the read operation during the write period and the I'ffl-like timing signal (column switch control signal) Common data ODL,,ODL
is combined with.

Next, the tiling signal (data manual buffer control signal) φ
□, a synchronized write signal 6tn, 6tn supplied from the data buffer D in synchronization with the memory cell M-0 via the column switches 0-8W, l]
]Write to 1tL and 1fL. At this time, sense amplifier 8
The column data pair DL, since the column data is also working and the data is input from the human power buffer D.
,, The emotion that affects DL Otori-6 is determined by the information of human power D t n.

Refreshi 5-@Saku Refreshi 3-Ni Memory Cell M-OBLlfC Information that is being lost and hated? Once the evening ram common data L
The next information is read to the sense amplifier 8m1 and the active restore circuit AR.

Therefore, the memory cell M-ox is set to the level restored to 1 by K.
This is done by writing to L. Therefore, the refresh operation is similar to the row addressing or sensing period operation described in the read operation.

However, in this case, the column switches 0 to 8 WIFi are made inactive and refresh is performed for all columns simultaneously and for each row in order.

Timing signal φE in the above D-RM M.

φ , φ The timing PA in Figure 3 per K that forms isophones
The number of occurrences of Y is used (not shown).

In *, the timing signal φA must be brought up precisely in synchronization with the end timing of memory cell selection. In this real 1a game, the above dummy cell is followed by a dummy word - or! New die word I on Figure 5A
In addition to the IM, a timing signal (b) path of 3m is provided in which the word m selection signal at the 7th word-far jllII is made into a human input pulse φ.

(not shown). and its output pulse φ. 0. is used as the timing signal φa.

As a result, since the timing signal φPA can be formed in synchronization with the selection end timing Kat of the memory cell distributed to the far end of the word line, malfunctions can be prevented. Since there is no need to provide a time margin more than necessary, i% stray operation can be achieved.Furthermore, the timing signal φA can be formed to follow fluctuations and dispersions in the word selection operation.

This invention is not limited to the above embodiment.

Origin of bootstrap operation? The voltage detection means used is
Lye electric EF ratio for M recommendation M Os F I T %kH 4
There are many types that can be modified for one circuit and 1R size.

Furthermore, the timing generation circuit according to the present invention has the above-mentioned D-
It can be used with widely available materials other than RAM.

[Brief explanation of the drawing]

Figure 1 is before this invention! The IEZ diagram is a timing diagram of the timing generation circuit that can be considered. Figure 3 is a circuit diagram showing an embodiment of this invention. The timing diagram 111E5 to be explained is a 1111 circuit diagram of a D-RAM to which the present invention is applied, and the diagram 11E5B is a timing diagram explaining its operation in detail.

Claims (1)

[Claims] 1. Manual pulse? Received electric si voltage 911M08FIC
TQ, the bootstrap valley 1tCB provided between the gate and source of this MO8FETQ, and the MOE
Connected in series with IPITQ+ and connected to the ground potential MO8
The output MO8IFITQs is connected in series between the n1 power supply voltage terminal and the ground potential terminal.
, Ql and the above MOB F Z T Q, manual pulse at the gate of I? Transmission gate MO8FKTQ, which conveys
Then, the MO87 is checked to see that the gate voltage of 'rQl has reached the predetermined voltage.
1liT Qm, Ql and Qsk A timing generation circuit with voltage detection means for switching from on to off. 2. The voltage detection means receives the gate voltage of the MO8FKTQ+, the ground potential 11M087ITQγ, which is connected in series to the MO8FKTQ, and the gate and drain voltage of the MO8FKTQ+. Crossing Wj line and ground potential 11M0
8PlTEQ, this (2) MOEIPI[1TQs is connected in series with the power supply voltage 111M087ETQ, which receives the precharge pulse φ, and the above MO8FIT
MO8FFiTQ connected in parallel with Qy and receiving n1 upper period precharge pulse φ, +o and rt, the above MO
8FIl+TQ, drain output MOIIFIT above
Claim 1i [1] The timing generation circuit according to claim 1, wherein the signal is transmitted to the gates of Q + Q4 and Ql. 3. The above human power pulse is a dynamic type MO8RMM
Friend dummy word line set up in? This is the word selection pulse at the end of the continuous selection, and the above output MO8F]
, Qa activates the sense amplifier.
Or the timing generation circuit described in the second tomb.