JP2000124418A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the transistor of a non-selective cell connected to the same word line from turning ON so as to lessen it in power consumption in a DRAM cell. SOLUTION: Transistors T1 and T2 are connected between a data line (e.g. bit line) and a prescribed node ND and turned ON/OFF corresponding to an applied voltage of a selection line (e.g. word line). The transistors T1 and T2 are possessed of a first control electrode G1 connected to a selection line and a second control electrode G2 that controls a threshold voltage corresponding to the applied voltage of control lines CL1 and CL2. A control circuit 2 is connected to the control lines CL1 and CL2. The control circuit 2 sets the threshold voltage of a selection transistor lower than its initial value and/or raises the threshold voltage of the other non-selective transistor. By this setup, when a voltage is applied to a selection line to turn a selection transistor ON, a non-selective transistor connected to the same selection line can be surely put in an OFF state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device having a transistor for controlling data line connection, such as a DRAM cell.

[0002]

2. Description of the Related Art FIG. 12 is a circuit diagram showing a configuration of a conventional DRAM cell. In the DRAM cell 100, a transistor T having a gate connected to the word line WL and a memory capacitor CAP are connected in series between a data line (bit line BL) and a ground potential. And usually,
The substrate of the transistor T is dropped to the ground potential. Although not particularly shown, a large number of DRAM cells 100 are arranged and connected in a matrix to form a memory cell array.

In this DRAM cell 100, a word line W
While L is kept at the low-level potential, the transistor T is turned off, and the amount of charge stored in the transistor-side electrode (storage node electrode) of the capacitor does not change. When a high-level potential is applied to the word line WL, the transistor T is turned on. At this time, usually, the transistors T of most cells connected to the word line WL are turned on.

At the time of writing, a precharge voltage, for example, a voltage V _DD / 2 which is half of the power supply voltage is applied to all bit lines, and a bit line BL connected to a cell to be written corresponds to “1” or “0”. Write voltages, for example, power supply voltages V _DD and 0 V are applied. In this state, when the transistor T is turned on, the storage node ND is charged by the write voltage for the cell to be written. On the other hand, when the transistor T of the unselected cell is turned on, the bit line potential (V _DD / 2) is almost changed to the storage node ND.
Transmitted to the side. Strictly speaking, the amplitude of the original stored data is
It decreases according to the capacitance ratio of the capacitor to the bit line capacitance. Normally, since the capacitance of the capacitor is considerably smaller than the capacitance of the bit line, the stored data of the amplitude V _DD is replaced by minute data of a small amplitude v centered on V _DD / 2. Even if it is minute data, the amplitude is drastically reduced as compared with the original data, so that it is substantially the same as destroying the data.

At the time of reading, although the same phenomenon as the above-mentioned unselected cell at the time of writing occurs, since this is amplified by a sense amplifier and read, storage data can be read. At the time of reading, data destruction occurs in unselected cells connected to the activated word line as in the case of writing.

[0006]

In this DRAM, the activation of the word line WL turns on most of the transistors T of the cells connected to the word line WL, and as described above, data is destroyed. A series of operations such as reading, amplifying, and writing of a small signal are performed on all the memory cells connected to the selected word line WL during a write cycle or a read cycle. And
In the read cycle, only information on the bit line BL corresponding to the memory cell to be selected is taken out as read information. In the write cycle, new data is written to the cell selected as the last write in the above series of operations, and the original data is written again to the non-selected cells.

Therefore, in the conventional DRAM, there is a disadvantage that useless operations, that is, read and rewrite are frequently performed on unselected cells connected to the selected word line, and wasteful power consumption is increased. Was.

An object of the present invention is to prevent unnecessary transistors in a group of transistors connected to the same selection line (for example, a word line) such as transistors in a DRAM cell from conducting, thereby reducing power consumption. It is to provide a small number of semiconductor devices.

[0009]

A semiconductor device according to the present invention is connected between a data line and a predetermined node, and its conduction or non-conduction is controlled in accordance with a voltage applied to a selection line connected to a control electrode. A semiconductor memory device having a transistor for controlling transfer of charge corresponding to storage data between the data line and a predetermined node, wherein the transistor includes a first control electrode connected to the selection line, And a second control electrode for controlling a threshold voltage of the transistor according to an applied voltage of the control line.

In the semiconductor memory device of the present invention, when the plurality of transistors are connected to the same selection line, and the plurality of control lines of the plurality of transistors have a plurality of individually connected control lines, the plurality of control lines are connected to each other. The threshold voltage of a specific transistor among the plurality of transistors may be reduced from an initial value when the second control electrode is not biased or uniformly biased, and / or the threshold voltage of another transistor may be reduced. A control circuit is connected to turn on the specific transistor in response to the application of a voltage to the select line, and to turn off the other transistors connected to the same select line. Preferably, the control circuit controls a threshold voltage difference between the specific transistor and the other transistor to be equal to or larger than a potential difference of the predetermined node that changes according to a storage state.

As this semiconductor storage device, a DRAM is preferable. Further, the second control electrode may be formed on an active layer (well or SOI layer) in which a channel of the transistor is formed in a semiconductor substrate,
Further, the insulating layer may be embedded in an insulating layer in the SOI structure. When the second control electrode is embedded in the insulating layer, the control electrode can be an insulated gate type. Even when biased in the positive direction, the reactive current does not flow from the second control electrode to the SOI layer side, thereby reducing the reactive power. Yes, it is.

In the semiconductor memory device of the present invention configured as described above, unnecessary transistors in the group of transistors connected to the activated select line are prevented from conducting, and as a result, unnecessary power is not consumed. For example, DRAM
In this case, even if a word line is activated, a transistor of a non-selected cell connected to the word line is not turned on. For this reason,
The stored data in the non-selected cells is not destroyed. Therefore, read the stored data before this data destruction,
The operation of rewriting after data destruction is unnecessary, and power consumption is correspondingly reduced.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a semiconductor memory device according to the present invention will be described by taking a DRAM as an example.

First Embodiment FIG. 1 is a diagram showing a main configuration of a DRAM according to this embodiment. FIG. 2 is a sectional view showing a schematic configuration of a transistor forming a memory cell. In the memory cell array of the DRAM 1, each memory cell is composed of a memory capacitor and a transistor.

As shown in FIG. 1, memory cell MC1 has
It comprises a memory capacitor CAP1 and a transistor T1. The plate electrode of the memory capacitor CAP1 is connected to a supply line of the reference voltage V _SS . The transistor T1 is connected between the node electrode of the memory capacitor CAP1 and the bit line BL1. The connection point between the transistor T1 and the memory capacitor CAP1 is
This becomes storage node ND1. Similarly, the memory cell MC2
Is composed of a memory capacitor CAP2 and a transistor T2. The plate electrode of the memory capacitor CAP2 is connected to a supply line for the reference voltage V _SS . Node electrode of memory capacitor CAP2 and bit line BL2
Is connected to the transistor T2. The connection point between the transistor T2 and the memory capacitor CAP2 becomes the storage node ND2.

The transistors T1 and T2 each have a first control electrode G1 for controlling the switching of the transistor.
And a second control electrode G2 for controlling a threshold voltage. The first control electrodes G1 of the transistors T1 and T2 are commonly connected to a word line WL. Transistor T
The first and second control electrodes G2 are connected to different control lines CL1 or CL2, respectively.

In the cross-sectional structure of the transistors T1 and T2 shown in FIG. 2, a p-well in which p-type impurities are introduced at a predetermined concentration as a transistor active layer is provided on the surface side of a semiconductor substrate 4 such as an n-type silicon wafer. 6 are formed. On the p well 6, a gate insulating film 7 made of, for example, silicon oxide and a first insulating film made of, for example, n-type polysilicon.
A control electrode G1 (hereinafter, also referred to as a surface gate electrode) is stacked. On the inner surface side of the p-well on both sides of the surface gate electrode G1, n-type impurities are introduced to form source / drain impurity regions 8. Also, a second control electrode G2 (hereinafter, referred to as a metal or n-type polysilicon) is formed.
A well electrode is also provided on the p-well 6 so as to control the well potential.

Although not shown, the transistors T1,
A plurality of conductive layers are laminated on T2 and the well electrode G2 via an insulating layer. For example, the surface gate electrode G
When 1 does not double as the word line WL, word lines electrically connected to the surface gate electrode G1 are stacked via an interlayer insulating layer. Also, transistors T1, T2
Lines BL1 and BL2 and memory capacitor CAP as conductive layers connected to the source or drain of
1, CAP2 node electrode layers are stacked via an interlayer insulating layer. Further, plate electrode layers of the memory capacitors CAP1 and CAP2 also serving as reference potential wirings are laminated on the node electrode layers via capacitor dielectric films. The structure of the memory capacitor is not limited, and may be a stack type, a trench type, a cylinder type, or the like. The DRAM 1 according to the present embodiment is called “bulk type” because the surface portion of the semiconductor bulk (p-well) is depleted in the cell transistor.

The memory cells having such a configuration are repeatedly arranged in a matrix to form a memory cell array.

In the entire memory cell array of this embodiment, control lines are provided for at least the number of cells connected to at least one word line. As shown in FIG. 1, a control circuit 2 is provided in a peripheral circuit, and control lines CL1, CL2,.
Is connected. The control circuit 2 controls the threshold voltage of each transistor in the cell group connected to the activated word line so that only the transistor of the selected cell is turned on and the transistors of the other cells are turned off. I do.

Next, after explaining the operation of the DRAM, the conditions necessary for the control circuit 2 to achieve the conduction control of the transistor and the specific control amount (shift amount) of the threshold voltage are estimated.

In general, in a DRAM, activation of a word line may cause all transistors in a cell connected to the word line to become conductive, which may cause data destruction. A series of operations such as reading, amplifying, and writing a small signal is performed on a memory cell during a write cycle or a read cycle. Then, in the read cycle, only information on the data line corresponding to the memory cell to be selected is taken out as read information. In the write cycle, new data is written to the cell selected as the last write in the above series of operations, and the original data is written again to the non-selected cells.

In this embodiment, the operation of the control circuit 2 prevents the transistors of the non-selected cells from conducting even when the word line is activated, thereby preventing data destruction of the non-selected cells. Therefore, the last write in the above series of operations need only be performed on the selected cell.

Hereinafter, the operation of the DRAM will be specifically described.
Here, the memory cell MC1 of FIG. 1 is selected, the memory cell MC2 is not selected, and the selected memory cell MC1 is selected.
It is assumed that data writing or reading is performed for only one.

The potential of the word line WL in the initial state is maintained at a low level (for example, a ground potential). The bit line BL1 to which the selected cell MC1 is connected is activated by a column decoder (not shown). That is, at a predetermined timing before reading, the bit line BL1 is precharged to a predetermined potential, for example, the power supply voltage V _CC / 2. A predetermined word pulse is applied to the word line WL by a row decoder (not shown), whereby the potential of the word line WL rises from a low level to a high level (for example, the power supply voltage V _DD ). As a result, the transistor T1 of the selected cell is turned on, but the transistor T2 of the non-selected cell is kept off by the operation of the control circuit 2. When the transistor T1 of the selected cell is turned on, a minute potential change is superimposed on the precharge voltage and appears on the bit line BL1 according to the potential of the storage node ND1.

Thereafter, when a sense amplifier (not shown) is activated, the sense amplifier amplifies the bit line voltage using the precharge voltage as a reference voltage, and thereby the bit line BL is amplified.
Binary information having a large amplitude according to the presence / absence of one minute potential change can be obtained. The binary information takes, for example, the power supply voltage V _DD when the read data is “1” and the ground line potential when the read data is “0”, and is temporarily held in the bit line BL1.

In the case of reading, the same data as the original is selected by the binary information held on the bit line BL1.
Written again in C1. In the case of writing,
After the binary information held by the bit line BL1 is forcibly rewritten with an external write voltage, the rewritten data is written to the selected cell MC1. Specifically, similarly to the case of the above-described read, the word line W is output by the row decoder.
A predetermined word pulse is applied to L, whereby the potential of the word line WL rises from a low level to a high level.
As a result, the transistor T1 of the selected cell is turned on in accordance with the bit line potential, and data is written. That is, when there is no potential difference between the bit line BL1 and the storage node ND1, the transistor T1 does not turn on because there is no need to change the storage node potential, but when the potential difference is, for example, the power supply voltage _VDD , the transistor T1 turns on. Storage node ND1 is charged with bit line potential BL1. In addition, even at the time of this writing, by the operation of the control circuit 2,
The off state of the transistor T2 of the unselected cell is maintained,
Data destruction of the unselected cell MC2 is prevented.

In the DRAM operating as described above, the potential when the word line WL is selected (activated) is Vwh, the potential when the word line WL is not selected (inactive) is Vwl, and the bit line B when writing is performed.
The potential of L1 is set to the power supply voltage V _DD when the data to be written is “1”, and is set to the ground potential (0 V) when the data to be written is “0”. The potentials of the storage nodes ND1 and ND2 are Vnh when the storage data is “1” and Vnl when the storage data is “0”.
And take Assuming that the initial threshold voltage of the transistors T1 and T2 is Vthm, the condition for writing "1" to the selected cell is as follows.

[0029]

Vwh−Vthm ≧ Vnh (1)

The high-level storage potential Vnh is equal to the power supply voltage V
For _DD, in order to satisfy the equation (1), the activation voltage Vwh of the word lines than the power supply voltage V _DD, the threshold voltage V
thm or higher, in which case the word line is boosted. Note that this equation (1) is also a sufficient condition when "0" is written.

On the other hand, the condition that the transistor T2 of the unselected cell MC2 connected to the same word line WL is maintained in the off state is as follows.

[0032]

Vwh−Vthm ≦ Vnl (2)

The high-level storage potential Vnh is changed to the power supply voltage V
Assuming that _DD and the low-level storage potential Vnl are 0 V, the above equations (1) and (2) are rewritten, and the following equations (1 ′) and (2 ′) are obtained.

[0034]

Vwh−Vthm ≧ V _DD (1 ′) Vwh−Vthm ≦ 0 (2 ′)

Further, in order to prevent the storage data from leaking from the transistor T2 of the non-selected cell, the leakage current in the sub-shreshhold region must be small. Therefore, the initial threshold voltage Vthm is generally low. 0.
It must be 7V or more. That is, the following equation (3) is also one of the conditions.

[0036]

Vthm ≧ 0.7 (3)

The above equations (1 '), (2') and (3)
Since the formulas do not stand up, conventionally, the word line is activated in consideration of the formulas (1 ') and (3) to read out the data of all the cells connected to the same word line, and the formula (2') Are not restored, and the data of the unselected cells destroyed have been restored by rewriting.

On the other hand, in the present embodiment, the transistor threshold voltage of the selected cell is lowered from the initial value to Vthl, and the transistor threshold voltage of the non-selected cell is raised to the threshold value and set to Vthh. To achieve the simultaneous establishment of two expressions. These two threshold voltages Vthl, V
By rewriting the expressions (1 ′), (2 ′) and (3) using thh, the following expressions (4) to (6) are obtained.

[0039]

Vwh−Vthl ≧ V _DD (4) Vwh−Vthh ≦ 0 (5) Vthm ≧ 0.7 (6)

From the above equations (4) and (5), the following equation is established.

[0041]

Vthh−Vthl ≧ V _DD (7)

FIG. 3 shows a setting range of the transistor threshold voltage satisfying the equations (4) to (7). This figure 3
An example of setting the threshold voltage within the range shown in FIG.

The initial threshold voltage V during the transistor manufacturing process
thm is set to 0.7 V, the power supply voltage V _DD during operation is set to 1.5 V, and the word line boost voltage Vwh is set to 1.8 V. In this case, from the above equations (4) and (5), the high threshold voltage Vthh is 1.8 V or more and the low threshold voltage Vthh is low.
l must be less than 0.3V. From the above equation (7), the difference between the two threshold voltages is required to be 1.5 V or more. The setting of each threshold voltage is arbitrary as long as these requirements are satisfied. However, for example, for example, the threshold voltage is shifted by 1.5 V in the positive direction and 0.5 V in the negative direction, and Vthh
= 0.7 + 1.5 = 2.2 (V), Vthl = 0.7-
0.5 can be set to 0.2. It is also possible to shift the threshold voltage only in the negative direction. For example, the initial threshold voltage Vthm is previously set to a high value of 2.2 V, this is set to a high threshold voltage Vthh, the shift amount is set to -2.0 V, and the low threshold voltage Vthl is set to 0.
It can be 2V.

The threshold voltage condition has been described above mainly from the viewpoint of the conduction / non-conduction of the transistor. In addition, the threshold voltage may be limited by the impurity concentration of the channel. FIGS. 4 and 5 are graphs showing the dependence of the transistor threshold voltage Vth and its shift amount ΔVth on the gate bias voltage applied to the second control electrode, using the acceptor concentration Na of the active layer as a parameter. FIG.
The horizontal axis indicates the gate forward bias voltage Vgf, and the horizontal axis in FIG. 5 indicates the gate reverse bias voltage Vgb.

As shown in FIGS. 4 and 5, the transistor threshold voltage Vth greatly depends on the impurity concentration (in this embodiment, the acceptor concentration Na) of the active layer in which the channel is formed. There is also a certain optimum range for acceptor concentration Na that satisfies the operation performance of. For example, when the gate oxide film thickness Tox is 5 nm and the optimum impurity concentration Na of the active layer (p-well 6) is 1 × 10 ¹⁸ cm ^{−3 in} the device structure of FIG. 2, the initial threshold voltage Vthm is 0 from the graph. It is decided naturally to .8V. In this case, assuming that the gate forward bias voltage Vgf is 0.8 V, which is a limit at which the diode under the second control electrode G1 turns on and no forward current flows, the negative threshold voltage shift amount ΔVth from FIG. Approximately -0.45V, and thus the low threshold voltage Vthl is 0.35V. Assuming that the gate reverse bias voltage Vgb is −3.0 V, the threshold voltage shift amount ΔVth in the positive direction is about 0.8 V from FIG.
Becomes In this case, when the power supply voltage V _DD is 1.5 V, the above equation (7) is not satisfied. For example, the power supply voltage V _{DD is set} to 1.2 V and the word line boost voltage Vwh is set to 1.55 V.
Operate as V. Note that the gate bias voltage V
gf and Vgb are voltages based on the source or the drain. Therefore, the voltage to be actually applied to the second control electrode G2 is lower storage potential Vnl unselected cells may remain -3V taking into account the (0V), high storage potential Vnh (V _DD) for the selected cell Is considered, 1.2 + 0.8 = 2.0
(V).

In the DRAM according to the present embodiment, the initial threshold voltage Vthm is set in consideration of the process parameters in the range as shown in FIG. 3, and the threshold voltage is adjusted by the control circuit 2 described above. In the last write operation in a read cycle or a write cycle consisting of a series of operations described above, predetermined data may be written only to the selected cell. Therefore, the DRAM according to the present embodiment has an advantage that power consumption can be significantly reduced as compared with a DRAM having a conventional structure that requires writing to all cells connected to the same word line.

Second Embodiment In this embodiment, the "partial depletion type" D in which the active layer of the cell transistor is not a well but a semiconductor layer formed by epitaxial growth or the like and a part thereof is depleted.
Regarding RAM. The basic circuit configuration and operation are the same as those of the first embodiment, and FIGS. 1 and 3 to 5 are also applied to this embodiment.

FIG. 6 is a sectional view showing a transistor structure of the partially depleted DRAM. In the transistors T1 and T2 of the partially depleted DRAM shown in FIG.
(A material other than a semiconductor is also possible)
An SOI layer 14 as an active layer is laminated. This SOI structure is, for example, a bonding method or a SIMOX.
(Separation by Implanted Oxygen) method or the like. A gate insulating film 7 and a first control electrode (surface gate electrode) G1 are stacked on the SOI layer 14 in the same manner as in the first embodiment, and the SOI layer regions on both sides of the gate insulating film 7 and the buried insulating layer 12 The n-type impurity is introduced until it reaches the upper limit, and the source / drain impurity region 16 is formed. Although not particularly shown, the second control electrode G2 is, for example,
The first control electrode G1 is formed at a predetermined position in the length direction of the first control electrode G1 so as to be in contact with the active region of the SOI layer sandwiched between the source / drain impurity regions 16 and insulated from the surface gate electrode G1. I have.

The DRAM according to the present embodiment has the same advantages as the first embodiment, and also has a small parasitic capacitance with the substrate, and achieves high-speed operation with low voltage and low power consumption because the transistor has an SOI structure. There is an advantage that you can.

Third Embodiment This embodiment has an SOI structure similarly to the second embodiment, but forms a second control electrode in a buried insulating layer to directly control the electric field of the channel of the active layer. The present invention relates to a “fully depleted” DRAM that can be completely depleted.
The basic circuit configuration and operation are the same as those of the first embodiment, and FIGS. 1 and 3 are also applied to this embodiment.

FIG. 7 is a sectional view showing a transistor structure of the fully depleted DRAM. In the transistors T1 and T2 of the fully depleted DRAM shown in FIG. 7, as compared with the second embodiment, the second control electrode G2 is different from the buried insulating layer 12 in FIG.
The difference is that it is embedded inside. The buried-type second control electrode G2 is formed on the back surface of the SOI layer region sandwiched between the source / drain impurity regions 16 via the second gate insulating film 20 made of, for example, silicon oxide in the buried insulating layer 12. Facing. The SOI layer 14 in this example has an inter-transistor portion 14a that is insulated, thereby isolating elements.

In the transistors according to the first and second embodiments, the second control electrode G2 has an active layer (p well 6 or S well).
Since the gate forward bias voltage Vgf is in direct contact with the OI layer 14), it is desirable that the gate forward bias voltage Vgf be suppressed to, for example, about 0.8 V so that the diode forward current by the second control electrode G2 does not flow. This is because, if a diode forward current flows from the second control electrode G2 to the active layer depending on the operation state, this reactive current impedes a reduction in power consumption. Therefore, in order to prevent the reactive current from flowing in the first and second embodiments, it is necessary to add a current blocking diode or the like.

On the other hand, in the transistor according to the present embodiment, since the second control electrode G2 is formed of an insulated gate FET, no reactive current flows structurally, and the upper limit of the gate forward bias voltage Vgf is reduced. Is not limited to about 0.8V. Therefore, it is not necessary to add a diode or the like for blocking current.

The threshold voltage Vth of the first control electrode G1 of the fully depleted SOI transistor varies depending on the thickness of the buried side second gate insulating film 20 in addition to the channel impurity concentration. This is because if the gate insulating film thickness changes, the electric field dominating ability of the second control electrode G2 on the channel also changes.

FIGS. 8 and 9 show the dependence of the threshold voltage Vth and its shift amount ΔVth on the gate bias voltage applied to the second control electrode.
It is a graph which shows xb as a parameter. The horizontal axis in FIG. 8 shows the gate forward bias voltage Vgf, and the horizontal axis in FIG. 9 shows the gate reverse bias voltage Vgb.

An example of setting the threshold voltage obtained using FIGS. 8 and 9 is shown below. Gate oxide thickness To
xb is set to 5 nm, and the initial threshold voltage Vthm is set to 0.58V. In this case, since the initial threshold voltage Vthm is lower than 0.7 V, it is desirable to increase the initial threshold voltage value by applying the gate reverse bias voltage Vgb to the control line even when the word line is not selected. For example, if the gate reverse bias voltage Vgb is -0.5 V, the threshold voltage shift amount ΔVth is 0.19 V from FIG.
The initial threshold voltage Vthm is 0.77V, which can be higher than 0.7V. From the initial state of all the control lines, for example, 1.0 V is applied as the gate forward bias voltage Vgf to the embedded second control electrode G2 of the transistor T1 of the selected cell. From FIG. 8, the threshold voltage shift amount ΔV
th is -0.38 V, and the low threshold voltage Vthl is 0.2 V. On the other hand, the non-selected cell transistor T2
For example, -2.5 V is applied as the gate reverse bias voltage Vgb to the embedded second control electrode G2. From FIG. 9, the shift amount ΔVth of the threshold voltage is 0.97 V, and the high threshold voltage Vthh is 1.55 V.

In this threshold voltage setting example, the operation can be performed with the power supply voltage V _{DD set} to 1.2 V and the word line boost voltage Vwh set to 1.4 V, for example. Since the gate bias voltage Vgf is a voltage based on the source or the drain, the voltage applied to the second control electrode G2 is 1.2 + 1.0 in consideration of the high storage potential Vnh (V _DD ) in the selected cell. = 2.2 (V).

In the DRAM according to the present embodiment, the threshold voltage is controlled by the control circuit 2 of FIG. 1 similarly to the first embodiment, and unnecessary operation of cells that are not read / written is prevented, and power consumption is low. Further, as in the second embodiment, since the transistor has the SOI structure, the parasitic capacitance with the substrate is small, and high-speed operation can be achieved with low voltage and low power consumption. Further, since the second control electrode G2 of the transistor is an insulated gate type, there is no power loss due to a reactive current.

Fourth Embodiment In the present embodiment, a fully depleted DRAM will be described as an example in which the threshold voltage is controlled from the surface of the active layer.

FIG. 10 is a circuit diagram showing a cell configuration of the DRAM according to the present embodiment. In this DRAM cell, the connection relationship between the word line WL and the control line CL for the two control electrodes of the transistor T is reversed as compared with the third embodiment. That is, in the present embodiment, the word line WL
The first control electrode G1 connected to the control line CL is a buried type, and the second control electrode G2 connected to the control line CL is a surface type. Therefore, the gate insulating film on the word line side is S
Since it is formed in the buried insulating layer having the OI structure, the degree of freedom in setting the film thickness Toxb is high. That is, the thickness of the gate insulating film on the word line side is arbitrarily set within the range permitted by the process conditions without considering the consistency with the gate insulating film thickness of another MOS transistor formed on the surface side of the SOI layer. it can.

In such a transistor having two control electrodes, channel control is performed by the first control electrode to which a signal is input in response to a change in the amount of DC bias applied to the second control electrode G2 for threshold voltage control. It is desirable to increase the change amount of the threshold voltage because the change amount of the DC bias by the control circuit 2 can be reduced.

FIG. 11 is a graph showing the dependency of the threshold voltage shift amount on the other side of the two control electrodes when a certain amount is changed, on the gate insulating film thickness on the buried gate electrode side. The graph shown by the solid line in FIG. 11 shows the threshold voltage shift amount Δ by the surface gate electrode when the bias voltage of the buried gate electrode is changed by 1 V as in the third embodiment.
Vth / (ΔVgb = 1V). In this case, when the gate oxide film thickness Toxb on the side of the buried gate electrode is increased, the ability of the buried gate electrode to control the electric field with respect to the channel is reduced, so that the threshold voltage shift amount is reduced. In contrast,
In FIG. 11, a graph indicated by a dashed line indicates a threshold voltage shift amount Δ due to the buried gate electrode when the bias voltage of the surface gate electrode is changed by 1 V as in the present embodiment.
Vthb / (ΔVg = 1V). In this case, when the gate oxide film thickness Toxb on the side of the buried gate electrode is increased, the threshold voltage shift amount is increased.

For example, the gate oxide film thickness Tox on the front side
When both the gate oxide film thickness Toxb on the buried side and the buried side are 5 nm, the threshold voltage shift can be increased by connecting the word lines on the front side as in the third embodiment. It is about 37V. On the other hand, if the gate oxide film thickness Toxb on the buried side is made as thick as 60 nm, the threshold voltage shift can be increased by connecting the word lines on the buried side as in this embodiment, Can be as large as 4.2V. That is, from the graph of FIG. 11, the gate insulating film on the buried side is made thicker and the word line connection is reduced under the circumstances where the thickness of the gate insulating film on the surface side cannot be made too large due to the consistency with the surrounding transistors. It can be seen that the threshold voltage shift amount can be improved by performing on the buried side.

Now, the buried gate electrode (first gate electrode G)
1) It is assumed that the threshold voltage Vthb changes linearly with respect to the surface gate voltage Vg, and its slope is K. At this time, if there are two threshold voltages due to the buried gate electrode, the lower threshold voltage Vthlb is changed to the higher threshold voltage Vthhb.
The following equation is established using the effective surface gate bias voltage Vg (eff) required for the threshold voltage change of both.

[0065]

Vthlb = Vthhb−K × Vg (eff) = Vthhb− (ΔVthb / ΔVg) × (Vwh−V _DD ) (8)

In this case, as a threshold voltage setting example, for example, the power supply voltage V _DD is 1.5 V, the word line boost voltage Vwh is 2.0 V, and the initial threshold voltage Vthm and the high threshold voltage Vthhb are both 2.2 V. And Further, as read from the graph of FIG. 11, ΔVthb / ΔV
g = 4.2. When these are substituted into the above equation (8), Vthlb = 0.1 V is obtained. In this case, the above-mentioned expressions (4) to (7) also hold.

In the present embodiment, in addition to the same advantages as in the third embodiment, the control circuit 2 is formed by setting the gate insulating film thickness on the buried side to be large and connecting the word lines on the buried side. Can be made positive, and a negative voltage is unnecessary only by the word line boost voltage.

[0068]

According to the semiconductor memory device of the present invention,
For example, in a group of transistors connected to the same selection line (for example, a word line) such as a transistor in a DRAM cell, unnecessary transistors are prevented from conducting, so that a semiconductor device with low power consumption can be provided. Becomes

[Brief description of the drawings]

FIG. 1 is a diagram showing a main configuration of a DRAM according to first to third embodiments of the present invention.

FIG. 2 is a sectional view showing a schematic configuration of a transistor constituting a memory cell of the DRAM of FIG. 1;

FIG. 3 is a diagram showing a setting range of a transistor threshold voltage of FIG. 2;

FIG. 4 is a graph showing the dependence of a transistor threshold voltage Vth and its shift amount ΔVth on a gate forward bias voltage applied to a second control electrode, according to the first and second embodiments, using an acceptor concentration Na of an active layer as a parameter; It is a graph shown.

FIG. 5 is a graph showing the dependence of a transistor threshold voltage Vth and its shift amount ΔVth on a gate reverse bias voltage applied to a second control electrode, according to the first and second embodiments, using an acceptor concentration Na of an active layer as a parameter; It is a graph shown.

FIG. 6 shows a partially depleted DRA according to a second embodiment of the present invention.
FIG. 4 is a cross-sectional view showing a transistor structure of M.

FIG. 7 shows a fully depleted DRA according to a third embodiment of the present invention.
FIG. 4 is a cross-sectional view showing a transistor structure of M.

FIG. 8 shows the dependence of the threshold voltage Vth and its shift amount ΔVth on the gate forward bias voltage applied to the second control electrode according to the third embodiment.
It is a graph which shows xb as a parameter.

FIG. 9 is a graph showing the dependence of the threshold voltage Vth and its shift amount ΔVth on the gate forward bias voltage applied to the second control electrode according to the third embodiment.
It is a graph which shows xb as a parameter.

FIG. 10 is a circuit diagram showing a cell configuration of a DRAM according to a fourth embodiment of the present invention.

FIG. 11 is a graph showing the dependence of the threshold voltage shift amount on the other side of the two control electrodes on the buried gate electrode side when the constant amount is changed, according to the fourth embodiment. It is.

FIG. 12 is a circuit diagram showing a configuration of a conventional DRAM cell.

[Explanation of symbols]

1 ... DRAM (semiconductor storage device), 2 ... control circuit, 4 ...
Semiconductor substrate, 6 p-well (active layer), 7 gate insulating film (first gate insulating film), 8, 16 source / drain impurity region, 10 substrate, 12 embedded insulating layer (insulating layer), 14 SOI layer (active layer, semiconductor layer), 20 gate insulating film (second gate insulating film), T, T1, T2 ... transistor, CAP, CAP1, CAP2 ... memory capacitor, WL ... word line (select line) , BL, BL1, B
L2: bit line (data line), CL1, CL2: control line, G1: first control electrode, G2: second control electrode, ND
Storage node, V _DD ... power supply voltage, V _SS ... reference potential.

Claims (13)

[Claims] A first node connected between a data line and a predetermined node;
A semiconductor memory device, comprising: a transistor whose conduction or non-conduction is controlled in accordance with a voltage applied to a selection line connected to a control electrode, and which controls transfer of a charge corresponding to storage data between the data line and a predetermined node. A semiconductor comprising: a first control electrode connected to the selection line; and a second control electrode connected to the control line and controlling a threshold voltage of the transistor according to a voltage applied to the control line. Storage device. 2. The semiconductor memory device according to claim 1, wherein a plurality of said transistors are connected to the same selection line, and said plurality of transistors have a plurality of control lines individually connected to said second control electrodes. 3. The method according to claim 2, wherein a threshold voltage of a specific transistor among the plurality of transistors is lowered from an initial value when the second control electrode is not biased or is uniformly biased, and the threshold voltage is changed in response to application of a voltage to a selection line. 3. The semiconductor memory device according to claim 2, wherein a control circuit that turns on the specific transistor and turns off another transistor connected to the same selection line is connected to the plurality of control lines. 4. A method according to claim 1, wherein a threshold voltage of a specific transistor among the plurality of transistors is increased from an initial value when the second control electrode is not biased or is uniformly biased, and the voltage is applied to a selection line. 3. The semiconductor memory device according to claim 2, wherein a control circuit that turns off the specific transistor and turns on another transistor connected to the same selection line is connected to the plurality of control lines. 5. The method according to claim 1, wherein a threshold voltage of a specific transistor among the plurality of transistors is lower than an initial value when the second control electrode is not biased or uniformly biased, and is connected to the same control line. A control circuit that raises a threshold voltage of another transistor from the initial value, turns on the specific transistor in response to voltage application to a selection line, and turns off the other transistor, is connected to the plurality of control lines. 3. The semiconductor memory device according to claim 2, wherein: 6. The semiconductor memory according to claim 3, wherein said control circuit controls a threshold voltage difference between said specific transistor and said another transistor to be equal to or higher than a potential difference of said predetermined node which changes according to a storage state. apparatus. 7. The semiconductor memory according to claim 4, wherein said control circuit controls a threshold voltage difference between said specific transistor and said another transistor to be equal to or higher than a potential difference of said predetermined node which changes according to a storage state. apparatus. 8. The semiconductor memory device according to claim 1, wherein said second control electrode is formed on an active layer in which a channel of said transistor is formed in a semiconductor substrate. 9. The semiconductor memory device according to claim 8, wherein said active layer is a well formed in a semiconductor substrate. 10. The semiconductor memory device according to claim 8, wherein said active layer is a semiconductor layer formed on a substrate via an insulating layer. 11. A semiconductor layer formed on a substrate with an insulating layer interposed therebetween, wherein a channel of the transistor is formed, wherein the first control electrode is formed on the semiconductor layer with a first gate insulating film interposed therebetween. 2. The semiconductor memory device according to claim 1, wherein the second control electrode is stacked and embedded in the insulating layer so as to face the semiconductor layer via a second gate insulating film. 12. A semiconductor device comprising: a semiconductor layer formed on a substrate via an insulating layer; and a channel of the transistor is formed, wherein the first control electrode faces the semiconductor layer via a first gate insulating film. 2. The semiconductor memory device according to claim 1, wherein the second control electrode is buried in the insulating layer in a state in which the second control electrode is stacked on the semiconductor layer via a second gate insulating film. 13. The semiconductor according to claim 1, further comprising: a transistor; and a memory capacitor connected between the predetermined node and a reference potential line, for holding storage data at an electrode on a predetermined node side for each memory cell. Storage device.