KR20010008608A - low power SRAM device - Google Patents

Abstract

PURPOSE: An SRAM device for low power is provided to realize an SRAM device for performing a stable operation under a low power. CONSTITUTION: An SRAM device for low power comprises the following structure. A couple of transmission transistors(T1,T2) transmits information to a bit line according to a word line signal. A couple of load element(R1,R2) and a couple of drive transistor(T3,T4) are connected with a power terminal and a grounding terminal in order to perform a latch function. MOS transistors(M1,M2) are connected with the transmission transistors(T1,T2). Bipolar transistors(B1,B2) comprises a base connected with a gate electrode of the MOS transistors(M1,M2) and an emitter and a collector connected with a source and drain junction region.

Description

Low power SRAM device {low power SRAM device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a technique capable of implementing stable operation even under a low power supply voltage in a static random access memory (SRAM) device.

In general, SRAM, which is a semiconductor memory device, has a lower memory capacity than DRAM (Dynamic Random Access Memory), but is widely used in the medium and small memory fields because of its high speed and ease of use.

1 is a circuit diagram showing the basic cell structure of a conventional SRAM device, which has a pair of transfer (or pass) transistors T1 and T2, a pair of drive (or pull-down) transistors, and T3 and T4. And a pair of load elements R1 and R2. Here, the transistors constituting the cell are NMOS type.

The transfer transistors T1 and T2 have gates connected to word lines W / L, and source / drains of T1 to T2 to bit lines B / L and complementary bit lines / B / L. Are each connected.

The load elements R1 and R2 are connected in parallel to the power supply voltage Vdd terminal.

The driving transistors T3 and T4 have drains connected in common to the source and load elements R1 and R2 of the transfer transistors T1 and T2, and the gates thereof are alternately connected to the source of the transfer transistor. The ground voltage (Vss) terminal is connected.

Then, the stored information is preserved by the electric charge accumulated in the node of the cell, and the electric charge is always replenished from the constant power supply Vcc through the load elements R1 and R2, so that a refresh function is required as in DRAM. It doesn't work.

On the other hand, SRAM cells are also being scaled down due to the high integration of semiconductor devices. As a result, the power supply voltage Vdd is also lowered, so that the SRAM device is stably driven even under a low power supply voltage.

In other words, when the cell size and the power supply voltage are reduced in the highly integrated SRAM device, the voltage level of the cell node storing the "high level" is reduced. Therefore, as the integration and the low voltage become more important, it is important to secure cell operation stability.

However, in general, the transfer transistors T1 and T2 connecting between the SRAM cell and the bit line use a MOS transistor (Metal Oxide Silicon Transistor), which is a time for charging and discharging a large capacitive bit line. This takes a long time and slows cell access time. In addition, the MOS transistor has a smaller transconductance (g _m ) than the bipolar junction transistor (hereinafter referred to as BJT) and has a poor driving capability of current. In particular, the lower the power supply voltage, which is the driving voltage of the transistor, the more the driving current depends on the power supply voltage.

In addition, in an ultra-low voltage semiconductor device in which the power supply voltage Vdd is about 1 V, the transfer transceiver of such an SRAM cell usually has a threshold voltage (Vt) of about 0.7 V. Therefore, there is a problem in transferring the cell data of the SRAM. there was.

An object of the present invention is to solve the problems of the prior art, in the design of the structure of the transfer transistor, the gate of the MOS transistor and the base of the bipolar transistor is mutually connected and the impurity junction of the MOS transistor and the bipolar transistor is the same. The present invention provides a low power supply SRAM device that enables a cell to be accessed at a high speed even at a low power supply voltage.

1 is a circuit diagram showing a basic cell structure of a conventional SRAM device;

2A and 2B are circuit diagrams showing a cell structure of a low power SRAM device according to the present invention, respectively, and a vertical sectional view of a transfer transistor of the SRAM device;

3A and 3B are a three-dimensional view of an gated vertical bipolar transistor in a transfer transistor used in a low power supply SRAM device according to the present invention, and an equivalent circuit diagram of the transfer transistor;

4 is an operational waveform diagram showing a simulation of a transfer transistor of a low power supply SRAM device according to the present invention;

* Description of the symbols for the main parts of the drawings *

T1, T2: transfer transistor

T3, T4: drive transistor

R1, R2: load element

B / L, / B / L: Bitline

W / L: Wordline

M1, M2: MOS transistor

B1, B2: bipolar transistor

In order to achieve the above object, the present invention provides a pair of transfer transistors that apply information to or transmit information from a bit line in response to a word line signal, and a pair of loads connected in parallel to a power supply terminal and a ground terminal, respectively. In an SRAM cell having a device and driving transistors and outputting or pulling down a signal of a transfer transistor which is turned on in response to a signal transmitted from an intersecting transfer transistor and is not crossed, the gate electrode of each transfer transistor is a substrate. And a bipolar transistor having a MOS transistor commonly connected to the gate electrode, a base connected to the gate electrode of the MOS transistor, and an emitter and a collector connected to the source and drain junction regions, wherein each driving transistor is connected to the substrate and the gate in common. that It is characterized by.

The transfer transistor structure of the SRAM of the present invention includes a second conductive well formed in the first conductive substrate, a first conductive well formed in the second conductive well, and a gate electrode formed on the substrate of the first conductive well. And a junction region for the source / drain to emitter / collector in which the gate electrode is disposed in the well below the gate electrode with the gate electrode interposed therebetween and implanted with the second conductive impurity, and a predetermined distance from any one of the junction regions. And a base junction region into which the first conductive type impurity is implanted, and the gate electrode and the base junction region are connected to each other.

According to the principles of the present invention, a large amount of current flows through a transfer transistor by simultaneously activating a bipolar transistor and a MOS transistor having a large transfer conductance and a collector current constituting the transfer transistor. In addition, in the transfer transistor of the present invention, when a low voltage (word line voltage) of positive potential is applied to the gate electrode, the threshold voltage is lowered, so that the data access operation of the cell is stable even at a low voltage.

Best Mode for Carrying Out the Invention Preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, and the same reference numerals are used for the same parts as in the prior art.

2A and 2B are circuit diagrams showing a cell structure of a low power SRAM device according to the present invention, respectively, and a vertical cross sectional view of a transfer transistor of the SRAM device.

Referring to FIG. 2A, the present invention provides a pair of transfer transistors T1 and T2 for transmitting information applied to bit lines B / L and / B / L in response to a word line (W / L) signal; In a cell of an SRAM device having a pair of load elements R1 (R2) and driving transistors T3 (T4) connected in parallel to the power supply terminal Vdd and the ground terminal Vss, respectively, to perform a latch function, Bipolar having MOS transistors M1 and M2 having the gate electrodes of the transfer transistors T1 and T2 commonly connected to the substrate, a base commonly connected to the gate electrode of the MOS transistor, and an emitter and collector connected to the source and drain junction regions. Transistors B1 and B2.

In addition, each of the driving transistors T3 and T4 of the SRAM of the present invention are turned on by Vo ⁺ and Vo ⁻ , which are voltages applied to a common node (transmitting transistor, load and driving transistor are connected).

Vo ⁺ and Vo ^- voltages are low level if one is high level. In general, the values of the low level and the high level depend on the value of the power supply voltage Vdd and the value of the ground voltage Vss. For example, if Vo ⁺ is increased slightly by the external data write driver and exceeds the threshold voltage of the driving transistor T3, T3 is turned on and at the same time, Vo ^- of the other node is lowered to the ground voltage (Vss) so that the other connected driving transistors T4 are crossed. Is turned off. As a result, the potential of Vo ⁺ is almost close to the power supply voltage (Vdd) level.

In the transfer transistors T1 and T2 of the SRAM cell according to the present invention, the bipolar transistors B1 and B2 connected to the MOS transistors M1 and M2 are applied even if the driving voltage of the word line W / L is applied at a low voltage. Simultaneously activated, a large amount of current charges and discharges the bit line (B / L) (/ B / L), enabling high-speed operation even at low power.

In the driving transistors T3 and T4 of the present invention, when the transfer transistors T1 and T2 are turned on by the word line W / L, the pulse voltage of the gate electrode is simultaneously applied to the substrate. Is reduced to stabilize the cell operation even when the power supply voltage Vdd is lowered to a low power supply, for example, 1V or less. At this time, how much the power supply voltage is lowered depends on the doping concentration of the substrate.

Referring to FIG. 2B, the transfer transistor structure of the SRAM of the present invention is shown wherein the transfer transistor is an NMOS.

The vertical structure of the transfer transistor of the present invention is a n-well 12 in which a n-type impurity of a second conductivity type formed in a substrate 10 doped with a p-type impurity is implanted at a low concentration, and an n-well as a first conductivity type. The p-well 14 into which the first conductive type impurity formed in (12) is injected at low concentration, the gate electrode 16 formed on the substrate of the p-well 14, and the well below the gate electrode 16 ( 14, the junction region 18 for the source / drain to emitter / collector implanted with a gate electrode therebetween and implanted with a second conductivity type n-type impurity, and one of the junction regions 18 It is composed of a base junction region 20 in which a p-type impurity of a first conductivity type is spaced apart from a predetermined distance.

The voltage of the word line W / L is applied to a line where the gate electrode 16 and the base junction region 20 are connected to each other.

Unexplained reference numeral 15 denotes a gate oxide film.

Then, in the transfer transistor according to the present invention, the p-well 14 serves as a base of the bipolar transistor, and the n-well 12 is formed between the p-type substrate 10 and the p-well 14, so that the base It serves to separate. In the transfer transistor of the present invention, the drain and the source 18 used as the MOS transistor also serve as the collector and emitter of the bipolar transistor. Here, the collector and the emitter are completely symmetrical, unlike the conventional bipolar transistors, and either junction becomes an emitter or a collector.

On the other hand, there is no problem because the MOS transistor of the transfer transistor operates simultaneously even if the β (current transfer amplification factor) of the vertical bipolar transistor is small because a retrograde well is formed during p-well formation.

3A and 3B are a three-dimensional diagram of an gated vertical bipolar transistor in a transfer transistor used in a low power supply SRAM device according to the present invention, and an equivalent circuit diagram of the transfer transistor.

3A shows that the channel length (l _ch ) of the MOS transistor represents the base length of the bipolar transistor, and the channel width (w) represents the base width of the bipolar transistor. 3B shows a symmetric gated vertical bipolar transistor with the gate of the transfer transistor connected directly to the substrate and in parallel therewith.

4 is an operation waveform diagram showing a simulation of a transfer transistor of a low power supply SRAM device according to the present invention, in which the horizontal axis represents Vgs, which is a gate-source voltage, and the vertical axis, Ids, a drain-source current.

In the operation of the transfer transistor of the present invention, since the gate electrode is directly connected to the substrate, Ids is controlled by the operation of the transistor (1) until Vgs becomes 0.65V, but more voltage levels (0.65V or more). In this case, the bipolar transistor (2) is driven to generate the driving current Ids. Therefore, the overall averaged current versus voltage waveform (③) shows a high current value at low power supply voltage. For example, when Vgs is 0.35V, Ids flows 1 kHz. This driving current is mainly obtained by the MOS transistor whose threshold voltage Vt is 0.7V. On the other hand, when Vgs = 0.7V, Ids flows 1 kHz, which is mainly obtained by bipolar transistors.

Therefore, the transfer transistor of the SRAM cell of the present invention can operate normally even at a power supply voltage of 1V or less.

Accordingly, the present invention lowers the threshold voltage by activating the forward voltage of the gate electrode on the substrate during activation to lower the threshold voltage of the transfer transistor of the SRAM cell, and simultaneously activates the device acting as a parasitic bipolar transistor under the MOS transistor.

Therefore, when a low power supply voltage is supplied to the word line to transfer the stored cell data of the SRAM cell to the bit line, the transfer transistor is normally driven even at a low power supply to speed up the cell access time.

Claims (2)

A pair of transfer transistors that apply information to or transmit information from the bit line in response to the word line signal, and a pair of load elements and drive transistors connected in parallel to the power supply terminal and the ground terminal, respectively, A SRAM cell that outputs or pulls down a signal of a transfer transistor that is turned on and does not cross in response to a signal transmitted from the transfer transistor, A gate electrode of each transfer transistor includes a MOS transistor commonly connected to a substrate, a bipolar transistor having a base commonly connected to the gate electrode of the MOS transistor, and an emitter and a collector connected to the source and drain junction regions; Low power supply SRAM device, characterized in that each of the driving transistor is connected to the substrate and the gate in common. The transfer transistor structure of claim 1, wherein A second conductive well formed in the first conductive substrate; A first conductive well formed in the second conductive well; A gate electrode formed on the substrate of the first conductive well; A junction region for a source / drain to emitter / collector formed between the gate electrode and spaced apart from each other in the well below the gate electrode, and implanted with a second conductive impurity; And And a base junction region spaced a predetermined distance from any one of the junction regions and into which a first conductivity type impurity is implanted, wherein the gate electrode and the base junction region are connected to each other.