JPS594157A - Driving method for semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce the power consumption at the time of writing information in a memory device having dynamic random access memory cells composd of MIS transistors by limiting the threshold value current of the transistors to the range most preferable in operation. CONSTITUTION:The source 34 and the drain 33 of a buried channel MIS transistor Q having a junction gate 32 are respectively connected to word and bit lines, the gate is connected to the data line which specifies data to be written, and electrically floated. In driving, it is driven as VBB+DELTAV<=VTF, where VBB is a substrate bias voltage, VTF is threshold value of junction gate to buried channel, and DELTAV is the saturated voltage between the drain and the source when the transistor SW1 for coupling between the junction gate and the substrate is turned ON, thereby reducing the power consumption at the writing time. Since the current flowed to the word line is small, the circuit configuration of the word line driver can be simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention (1) The present invention relates to an improvement in a semiconductor memory device having a dynamic random access memory cell composed of a single 1-transistor.

Prior Art and Problems Currently, dynamic random access memory cells in semiconductor memory devices consist of a storage capacitor that stores charge and a transfer transistor that controls charging and discharging of charge to the storage capacitor. However, in this memory cell, the charge stored in the capacitor is directly read out.

By the way, in general, in order to form a large number of memory cells in a limited area, it is necessary to reduce the area occupied by the memory cells, and in such a case, the area of the capacitor may be sacrificed. There are many.

However, capacitors must be able to store the minimum amount of charge necessary, so in order to meet this requirement, we have to make it possible to form a thin, high-quality insulating film (the capacitor's dielectric film), and to make the shape ( 2) Although things are being done, there are limits to these.

Therefore, in recent years, in order to solve the drawbacks of the above-mentioned conventional technology, a random access cell called a taper isolated type dynamic gain cell has been developed.
A semiconductor storage device having memory cells has been developed and disclosed in Japanese Patent Laid-Open No. 101689/1989.

The memory cell disclosed herein has a buried channel region in the substrate and a junction gate region above the channel region, and the M-product capacitor in conventional memory cells is absent. The content of the stored information depends on the presence or absence of charge in the junction gate region, but the information is read out not by directly reading the stored charge, but because the conversion conductance of the transistor in the memory cell depends on the stored charge. Since the signal is modulated by the signal, we are trying to detect it. Therefore,
A large storage capacitor is not required, and
It has many features such as being able to read information non-destructively.

(3) Figure 1 shows a tapered isolated type dynamic
FIG. 3 is a sectional view of a main part of the gain cell taken in a direction perpendicular to the Gale direction.

In the figure, 1 is a p-type semiconductor substrate, 2 is a field insulating film, 3 is a gate insulating film, 4 is an n-type buried channel region, 5 is a p-type junction gate region, and 6 is a polycrystalline silicon gate electrode. It shows. It goes without saying that all the conductivity types illustrated here may be reversed.

As can be seen, the junction gate region 5 has a surface that is
~ insulation N'J3, and the lower surface is surrounded by an n-type buried channel region, and is in a completely electrically floating state.

The gate electrode 6 in this cell is wired parallel to the bit line and constitutes a data line. Charge is transferred into and out of the junction gate region 5 by using a hack gate and a hack gate in the channel region 4.
It is sufficient to operate the gate electrode 6, which is a data line, as a MOS gate, the semiconductor substrate 1 as a source region, and the junction gate region 5 as a drain region. That is, the punch-through current of the p-channel MOS transistor (4) is controlled by the back gate voltage, and therefore,
It may be considered that the voltage is controlled depending on the voltage of the channel region 4.

To write information to this cell, the potential of the word line containing the selected cell is lowered, thereby reducing the n+ type source region (located on the front or back side of the paper, not shown) in contact with the n type buried channel region 4. It has not been)
When the potential of the polycrystalline silicon gate electrode 6 is lowered to a high level, the holes in the p-type junction gate region 5 penetrate through the n-type buried channel region 4 and flow into the p-type semiconductor substrate 1. That is, the p-channel M
A punch-through current flows between the source and drain of the O3I transistor, and as a result, the junction gate region 5 enters an electron lynch state.

Similarly, when only the potential of the polycrystalline silicon gate electrode 6 is brought to a low level, hole injection does not occur. The (5) threshold value of the MOS transistor that forms the memory cell changes depending on the presence or absence of hole injection, so this is used as information "1" and "0".
This corresponds to

By the way, in the method for driving the tapered isolated type dynamic gain cell described above, no consideration is given to the reduction in power consumption required for large-capacity memories. Next, this point will be explained in detail.

Now, as mentioned above, when writing information to a cell,
Although the junction gate region 5 and the semiconductor substrate 1 should have the same potential, according to the inventor's experiments, they are never completely the same, and a slight potential difference ΔV always occurs.

The reason for this is that the current flowing through the p-channel MO3) transistor is not a current using the inversion layer as a channel like in a normal MOS-FET, but rather from the junction gate region 5, which is the source region of the p-channel MO3) transistor, to the channel region 4. A current generated by the movement of carriers (holes) injected into the drain, and the current is proportional to an exponential function of the drain voltage (in this case, the semiconductor substrate 1 is the drain region).
(6) This is because when the potential difference between the drain and source decreases, the current decreases extremely. It will be understood that the voltage dependence is steeper than that of a normal MOS-FET, where the current is proportional to the voltage multiplied by the drain-source voltage.

FIG. 2 shows the potential distribution for the ball between the semiconductor substrate 1 and the junction gate region 5, and shows the potential distribution for the ball between the semiconductor substrate 1 and the junction gate region 5.
When the word line voltage is lowered to lower the potential barrier 12 that stopped the ball 1!11, the semiconductor substrate 1
It is shown that the junction gate region 5 approaches the voltage of the semiconductor substrate 1. Even in this case, the potential barrier 12 that was blocking holes does not completely disappear, but remains slightly, so the voltage in the junction gate region 85 becomes slightly higher than that in the semiconductor substrate 1, as described above. be. This voltage can be set to a relatively small value when the substrate bias VBB is zero. The reason for this is that during a write operation, the word line voltage becomes equal to the substrate voltage, so the potential barrier for holes in the channel region 4 through which a current flows is the potential barrier for holes in the depleted channel region 4. :The potential barrier of the channel region 4 with respect to the substrate during writing is equal to that of the door when a substrate bias VBB (VBB in this case is negative) is applied. Depletion occurs in the n+ type source region (the part to which the word line is connected as described above, and is not related to the p-channel MO3 transistor) where a bias voltage equivalent to VB11 exists relative to the charge of the impurity atoms. This is because the effects of the electrostatic potential on the potential barrier minimum point for the ball in the channel region 4 that has become saturated overlap, and the barrier to hole injection becomes higher.

In response to this phenomenon, the present inventor proposed a method of lowering the injection barrier by using a depletion type transistor in the hole injection control section (refer to Japanese Patent Application No. 1983-42692). However, even in this case, there is no guarantee that the voltage on the substrate 1 and the voltage on the junction area 5 will be completely equal.

(8) Purpose of the Invention The present invention provides a semiconductor memory device as described above, in which the threshold current of the buried channel MIS transistor, which is a transfer transistor, is limited to a range that is preferable from an operational point of view. This reduces power consumption when writing information to cells.

Structure of the Invention In the present invention, in the semiconductor memory device, when a substrate bias voltage is applied, the junction gate region of the buried channel type MIS transistor has the same value as the substrate bias during data writing. The buried channel region is cut off in the write state.

Embodiment of the Invention When the substrate bias voltage IlB is applied to the semiconductor memory device described above, and the word line voltage is lowered to Vss (this may be set to the ground potential of zero (V)) in order to write as described above. , the voltage vpc of the junction gate region 5 is not equal to the word line voltage Vss (9), but becomes a slightly higher voltage vtte+ΔV. Then, with respect to the threshold value VTP of the embedded channel M I S +− transistor, at least VBIl+△V≦VTF
If so, no matter what information the embedded MIS) transistor holds, it will be turned off immediately upon entering the write operation, and no current will flow between the drain and source, so there will be no direct current consumption of the cell during write. Power can be reduced to zero.

When the threshold value VTF is outside the above conditions, current flows through the cell, but there is no problem with actual writing. The reason is,
This is because if the pull amplifier element is connected so that the bit line voltage is maintained at a high level during the write period, erroneous writing to unselected memory cells due to a drop in the bit line voltage will not occur. However, although it is good when the number of cells is small, when the number of cells is 64 or more, 256 or more cells are connected to one word line, and the power consumption when these cells are made conductive during writing cannot be ignored. Therefore, the threshold value V.

By setting P to the above-mentioned conditions, direct current power consumption during writing is eliminated, and a high-density memory can be realized.

(10) However, the problem is that 8V cannot be easily determined from the structural parameters. This is because the height of the potential barrier that controls hole injection into the junction gate region is determined by the three-dimensional potential distribution within the element and cannot be determined by -dimensional approximate calculation.

Therefore, in the present invention, the following method is adopted for practical discrimination.

FIG. 3 shows an equivalent circuit of a memory cell, where 31 is a MOS gate connected to a data line, 32 is a floating junction gate, 33 is a drain, 34 is a source, and Q is a junction FET having junction gate 32. , SWI is source 3
A transistor CI that is turned on and off depending on the voltage of 4 to control hole injection between the junction gate 32 and the semiconductor substrate.
indicate the MO8 capacity, respectively. Note that the drain 33 is connected to a bit line, and the drain 34 is connected to a word line.

Now, in the circuit shown in Figure 3, the data in the memory "
0'' write state, the data line connected to the MOS gate 31 is set to the ground potential, the source 34 is also set to the ground potential,
Drain currents are measured by connecting the drains 33 to the power supply potential.

At this time, if light is irradiated or a bias is applied and sufficient time has elapsed, the present invention does not depend on the present invention (even if the drain current becomes zero and the apparent It is easy to design words that require zero power.

The reason for this is that in the above state, the potential of the junction gate 32 is almost completely equal to the substrate bias voltage van, and the gate of the transistor Q is deeply biased. However, in this case, in an actual memory write operation, a read operation is performed before the potential of the junction gate 32 becomes completely equal to the substrate bias, resulting in power consumption. That is, in a short cycle transient state, the voltage V exists and the potential of the junction gate 32 is higher than the substrate potential.

According to the present invention, direct current power consumption can be reduced to zero even in memory operation, and the data line voltage of the memory cell biased in the write state is stepped from the ground potential to an appropriate potential. For example, when raised to the power supply voltage,
Step pulse standing distance is at most 2 (ms) from illusion.
This method is characterized by the drain current becoming almost completely zero after a certain period of time, and is distinguished from the prior art.

FIG. 4 is an explanatory diagram of the inside of the memory for demonstrating the above feature.

In the figure, 41 is a MOS gate connected to the data line, 42 is a floating junction gate, 43 is a drain, 44 is a source, 45 is a pulse, Q is a transistor having a junction gate 42, CI is MO3 capacitance, and R is a punch
The internal resistance of the through transistor, Δ■, is the saturation voltage that remains between the drain and source when the transistor is turned on. Note that the saturation voltage ΔV becomes zero after a sufficient amount of time has passed.

Now, when pulse 45 is applied to the data line, MO8 capacitance C
□ is charged, and the charging current flows depending on the punch-through current between the junction gate and the semiconductor substrate. When a step voltage is initially applied to the data line, the gate 42 of the transistor Q is biased by the voltage generated by the current flowing through the resistor R and 8V, and a drain current flows instantaneously. However, MO5 capacity C
The drain current of the transistor in the present invention when I is fully charged! , becomes approximately zero. Incidentally, in the memory cell described above, which has a good appearance but does not consume DC power during writing, the drain current IO continues to flow due to the effect of ΔV, and Δ■ becomes zero after a sufficient period of time has passed. The drain current ID becomes zero for the first time. This “sufficient time”
is determined depending on the memory refresh cycle.

The memory refresh time is currently set to 2 (ms) for convenience.
) to 4 (ms), but there is a tendency for it to become longer in the future. Therefore, after applying a pulse to the data line, 2(m
s) If the drain current Itl is flowing significantly after the lapse of time, it is not possible to effectively reduce the write power consumption, and this point is largely different from the present invention.

A memory cell suitable for the present invention is characterized by the impurity concentration of the buried channel region, the thickness of the buried channel region (14), the electrically floating junction data 1-
This can be achieved by optimizing the impurity concentration in the region.

FIG. 5 is an explanatory diagram for explaining such a memory cell, and the same parts as those explained with respect to FIG. 1 are indicated by the same symbols.

In the figure, dl represents the width of the depletion layer extending into the substrate at the junction between the channel and the substrate, d2 represents the width of the depletion layer extending into the channel, d3 represents the junction gate, and CH represents the thickness of the channel, respectively.

In this memory cell, when VBll is applied to the junction gate to V1 to the substrate, if do≦dl+d3, a memory cell that can be used in the present invention is realized. If 8V is unknown, if it is set to zero, then the necessary condition is do<d2'→-d3, assuming that the depletion layer width at this time is d2'.

(15) Effects of the Invention According to the present invention, a junction gate is provided in which the source and drain are connected to a word line and a bit line, respectively, and the gate is connected to a data line specifying write data and is electrically floating. Embedded channel type MT with
When driving a dynamic gain random access memory cell having an S transistor, the substrate bias voltage is V9B, the threshold of the junction gate with respect to the buried channel is VTF, and the transistor connecting the junction gate and the substrate is turned on. When the saturation voltage between the drain and source is △V, the power consumption during write operation can be reduced by driving as VIIB+△V≦VTP, which makes it possible to use highly integrated d-RAM. In addition, since the current flowing through the word line is small, the circuit configuration of the word line driver is simplified.

[Brief explanation of drawings]

Fig. 1 is a cross-sectional view (16) of a main part of a Taber isolated type dynamic gain cell to which the present invention is applied, Fig. 2 is a diagram showing the potential distribution for holes between the substrate and the junction gate, and Fig. 3 is a diagram showing the potential distribution for holes between the substrate and the junction gate. The figure is an equivalent circuit diagram of a memory cell, FIG. 4 is an explanatory diagram for explaining the state inside the memory cell, and FIG. 5 is an explanatory diagram of a memory cell suitable for applying the present invention. In the figure, 1 is a p-type silicon semiconductor substrate, 2 is a field insulating film, 3 is a gate insulating film, 4 is an n-type buried channel region, 5 is a p-type junction gate region, and 6 is a polycrystalline silicon gate electrode. be. Patent Applicant: Fujitsu Ltd. Representative Patent Attorney Tools: Kugobe (3 others) (17) Figure 1 Figure 2 Figure 3 -w~°.

Claims (1)

[Claims] Buried channel type Mis) having a junction gate whose source and drain are connected to a word line and a bit line, respectively, and whose gate is connected to a data line specifying write data and is electrically floating. When driving a dynamic gain type random access memory cell equipped with a transistor, the substrate bias voltage is set to VII+! , when the threshold value of the junction gate with respect to the buried channel is VTp-, and the drain-source saturation voltage when the transistor connecting the junction gate and the substrate is turned on is △V, then vlIB+△■≦VTF. A method for driving a semiconductor memory device, characterized in that: