JP3363038B2 - Semiconductor storage device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device characterized by a memory signal storage unit for storing memory signals.

[0002]

2. Description of the Related Art An SRAM for statically storing a storage signal is widely used as one of semiconductor memory devices. As the SRAM cell, there are known ones composed of six MOS transistors and one composed of four MOS transistors and two high resistance elements. All SRAM cells need to use 6 elements.

On the other hand, there is proposed an SRAM cell which is effective for high integration and which is composed of three elements (two Esaki diodes, one MOS transistor). 58-153295). Figure 2
9 shows an equivalent circuit diagram of this SRAM cell.

This SRAM cell has two Esaki diodes ED1 and ED2 connected in a forward direction between a high level voltage power source Vdd and a low level voltage power source Vss, and one source / drain of the Esaki diode ED1. ED1, ED2
Connection point N, the other source / drain is the bit line BL,
It is composed of a MOS transistor Tr whose gate is connected to the word line WL.

FIG. 30 shows an SRAM configured as described above.
The current-voltage characteristics of the Esaki diodes ED1 and ED2 in the cell are shown.

Intersection points A ₀ , A ₁ of the characteristic curve of the Esaki diode ED1 and the characteristic curve of the Esaki diode ED2
The state stabilizes at and shows latch characteristics. This SRAM cell utilizes these two stable states for storage signals.

Writing and reading of a memory signal and holding (standby) of signal charges are performed by the MOS transistor Tr.

That is, in the case of writing, the MOS transistor Tr is turned on to select the selected bit line B.
The L and the connection point N are electrically connected. As a result, at the connection point N, charges as a storage signal corresponding to the product of the parasitic capacitance and the voltage of the bit line BL are accumulated. Bit line BL
The voltage is selected so that the system is in a stable state corresponding to the intersection A ₀ or the intersection A ₁ .

In the case of reading, the MOS transistor Tr is turned on and the connection point N as a storage signal is set.
The charges stored in the bit line BL are read from the selected bit line BL. Then, in the case of standby, it is performed by turning off the MOS transistor. However, this SRA
The M cell has the following problems.

That is, in this SRAM cell, since a constant level drive current (tunnel current) I ₀ always flows, it is difficult to simultaneously improve the power consumption during standby and the read speed of the storage signal. This is because it is necessary to reduce the drive current I ₀ in order to suppress the power consumption during standby, whereas it is necessary to increase the drive current I ₀ in order to increase the reading speed.

[0011]

As described above, the conventional SRAM cell using the Esaki diode is an excellent memory cell in terms of high integration, but it has low power consumption and high speed operation at the same time. There was a problem that it was difficult to achieve.

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a semiconductor memory device including a memory signal storage section effective for high integration, low power consumption and high speed operation. To provide.

[0013]

[Means for Solving the Problems]

[Outline] To achieve the above object, a semiconductor memory device according to the present invention (claim 1) is connected to a semiconductor substrate and a first voltage power supply, and is selectively formed on the surface of the semiconductor substrate. It is sandwiched between the first conductivity type source diffusion layer, the second conductivity type drain diffusion layer selectively formed on the surface of the semiconductor substrate in a region different from the source diffusion layer, and these two diffusion layers. A first three-terminal Esaki consisting of a gate electrode provided on the substrate surface in the region through a gate insulating film.
It is characterized in that it has a memory signal accumulating section constituted by a tunnel element and a load having one end connected to the drain diffusion layer and the other end connected to a second voltage power supply.

Another semiconductor memory device according to the present invention (claim 2) is the semiconductor memory device (claim 1), wherein the load is a second three-terminal Esaki tunnel element, a MOS transistor, an Esaki -Characterized by being a diode or a resistance element. Another semiconductor memory device according to the present invention (claim 3) is the semiconductor memory device (claim 1), wherein the gate electrode of the second 3-terminal Esaki tunnel element or the MOS transistor is a refresh circuit. It is characterized by being connected.

[Operation] When a predetermined voltage is applied to the gate electrode of the three-terminal Esaki tunnel element to form the inversion layer,
An Esaki diode (tunnel diode) is formed by the inversion layer and the source / drain diffusion layer having a conductivity type opposite to that of the inversion layer. As a result, the system composed of the three-terminal Esaki tunnel device and the load can take a plurality of stable states. These plural stable states are utilized for the storage signal, as in the case of the conventional two-Esaki diode system.

The tunnel current of the Esaki diode can be controlled by the gate voltage. That is, the tunnel current increases as the carrier density of the inversion layer is increased by adjusting the level of the gate voltage.

As a result, according to the present invention, the tunnel current (driving current) can be increased and the storage signal can be read at high speed. Further, according to the present invention, the tunnel current (driving current) can be reduced, and the power consumption during standby can be reduced.

Further, according to the present invention, the constituent elements of the memory signal accumulating section are the two-terminal Esaki tunnel element and the load.
Therefore, high integration is easy.

Therefore, according to the present invention, high integration,
It becomes possible to realize a memory signal storage unit effective for low power consumption and high speed operation.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention (hereinafter referred to as embodiments) will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
FIG. 6 is an equivalent circuit diagram showing a storage signal storage unit of the SRAM cell according to the embodiment.

This memory signal storage unit includes a low level voltage power supply Vss (first voltage power supply) and a high level voltage power supply Vdd.
A three-terminal Esaki tunnel element ET connected in the forward direction with the (second voltage power supply), and a three-terminal Esaki tunnel element provided between the three-terminal Esaki tunnel element ET and the voltage power supply Vdd. Load L connected in series with ET
It is composed of and. The load L is, for example, 3
Examples include terminal Esaki tunnel elements, MOS transistors, Esaki diodes, and resistance elements.

FIG. 2 shows a sectional perspective view and symbols of a three-terminal Esaki tunnel device. To describe the structure of this element in a word, in the MOS transistor, the conductivity types of the source diffusion layer and the drain diffusion layer are opposite to each other.

In the figure, reference numeral 1 denotes a p-type silicon substrate, and an n ⁺ type source diffusion layer 2 and a p ⁺ type drain diffusion layer 3 having a high impurity concentration are selectively formed on the surface of the p type silicon substrate 1. Has been formed.

The n ⁺ type source diffusion layer 2 is a voltage source Vss, p
^{The +} type drain diffusion layer 3 is connected to the voltage power supply Vdd. Further, for example, the impurity concentration of the n ⁺ type source diffusion layer 2 and the p ⁺ type drain diffusion layer 3 is set to 1 × 10 ¹⁹ pieces / cm ³ or more so that the current / voltage characteristics of the element show negative differential resistance. .

A gate electrode 5 is provided on the substrate surface in a region sandwiched by the n ⁺ type source diffusion layer 2 and the p ⁺ type drain diffusion layer 3 with a gate insulating film 4 interposed therebetween.

FIG. 3 shows the current-voltage characteristics of the 3-terminal Esaki tunnel element.

When the gate voltage Vg is 0V, the drain current, more specifically, the diffusion current does not flow unless the drain voltage exceeds a certain value. When the drain voltage exceeds a certain value, the current increases in proportion to the drain voltage.

On the other hand, when the gate voltage Vg is a positive voltage, the n ⁺ type inversion layer 6 is formed on the substrate surface below the gate electrode 3,
An Esaki diode ED is generated near the interface between the n ⁺ type inversion layer 6 and the p ⁺ type drain diffusion layer 3. As a result,
The current / voltage characteristics of the 3-terminal Esaki / tunnel element ET exhibit a negative differential resistance.

As a result, the system composed of the three-terminal Esaki tunnel element ET and the load L can take a plurality of stable states. These plural stable states are utilized for the storage signal, as in the case of the conventional two-Esaki diode system.

Further, as the gate voltage Vg increases, n
^Since the electron density in the ⁺ type inversion layer 6 increases, if the gate voltage Vg is a positive voltage, the tunnel current increases as the gate voltage Vg increases.

Therefore, a large drive current can be obtained by increasing the gate voltage Vg at the time of reading the memory signal (accumulated charge). On the other hand, during standby, the gate voltage V
Power consumption can be reduced by lowering g and reducing the drive current.

Further, the storage signal accumulating unit of this embodiment has three units.
It is composed of two elements, a terminal Esaki tunnel element ET and a load L. On the other hand, the memory signal storage portion of the conventional SRAM cell of FIG. 29, which is advantageous for high integration, is composed of two elements (Esaki diodes ED1 and ED2). Therefore, the storage signal storage unit of the present embodiment is advantageous for high integration, like the conventional SRAM cell of FIG.

As described above, the memory signal storage unit of this embodiment is effective in terms of high integration, low power consumption and high speed operation. Therefore, by configuring the SRAM cell using the memory signal storage unit of the present embodiment, it becomes possible to realize a highly integrated SRAM with low power consumption and high speed operation.

(Second Embodiment) FIG. 4 shows a second embodiment of the present invention.
FIG. 6 is an equivalent circuit diagram showing a storage signal storage unit of the SRAM cell according to the embodiment. In the following drawings, the same reference numerals as those used in the previous drawings indicate the same or corresponding parts, and detailed description thereof will be omitted.

The SRAM cell of the present embodiment is a specific version of the SRAM cell of the first embodiment, and is an example in which a 3-terminal Esaki tunnel element ET _L is used as the load L. A common gate voltage Vg is applied to the gates of the three-terminal Esaki tunnel elements ET and ET _L. FIG. 5 shows the current-voltage characteristics of the three-terminal Esaki tunnel element ET _L in the memory signal storage section configured as described above. This is when a positive voltage is applied to the gate electrode.

(Third Embodiment) FIG. 6 shows a third embodiment of the present invention.
FIG. 6 is an equivalent circuit diagram showing a storage signal storage unit of the SRAM cell according to the embodiment.

The SRAM cell of the present embodiment is a modification of the SRAM cell of the first embodiment, and is an example in which a MOS transistor Tr _L is used as the load L. A common gate voltage Vg is applied to the gates of the three-terminal Esaki tunnel element ET and the MOS transistor Tr _L.

FIG. 7 shows the three-terminal Esaki tunnel elements ET and M in the memory signal accumulating section thus constructed.
The current / voltage characteristics of the OS transistor Tr _L are shown. This is when a positive voltage is applied to the gate electrode.

(Fourth Embodiment) FIG. 8 shows a fourth embodiment of the present invention.
FIG. 6 is an equivalent circuit diagram showing a storage signal storage unit of the SRAM cell according to the embodiment.

The SRAM cell of this embodiment is a modification of the SRAM cell of the first embodiment.
This is an example using a diode ED. The Esaki diode ED is connected in the forward direction.

FIG. 9 shows the current / voltage characteristics of the three-terminal Esaki tunnel element ET and the Esaki diode ED in the memory signal accumulating unit thus configured. This is when a positive voltage is applied to the gate electrode.

(Fifth Embodiment) FIG. 10 is an equivalent circuit diagram showing a storage signal storage portion of an SRAM cell according to a fifth embodiment of the present invention.

The SRAM cell of the present embodiment is a concrete example of the SRAM cell of the first embodiment, and is an example in which a resistance element R is used as a load L.

FIG. 11 shows the current-voltage characteristics of the three-terminal Esaki tunnel element ET and the resistance element R in the memory signal storage section thus configured. This is when a positive voltage is applied to the gate electrode. 2 as shown
The state becomes stable at the intersections A ₀ and A ₁ of the two characteristic curves.

(Sixth Embodiment) FIG. 12 is an equivalent circuit diagram showing an SRAM cell according to a sixth embodiment of the present invention.

This SRAM cell is composed of the storage signal storage section of FIG. 1 and the MOS transistor Tr.
One source / drain of the MOS transistor Tr is 3
Connection point N between terminal Esaki tunnel element ET and load R,
The other source / drain is connected to the bit line BL, and the gate is connected to the word line WL.

Writing, reading and holding of the accumulated charges are performed by the MOS transistor Tr.

That is, to write the accumulated charge, MO
The S transistor Tr is turned on to electrically connect the selected bit line BL and the connection point N. As a result,
At the connection point N, charges as a storage signal corresponding to the product of the parasitic capacitance and the voltage of the bit line BL are accumulated at high speed, and the storage signal is written. The voltage of the bit line BL is selected so that the system including the 3-terminal Esaki tunnel element ET and the load L is in a stable state.

Further, in order to read the accumulated charge, a high level positive voltage is applied to the gate of the 3-terminal Esaki tunnel element ET to maximize the tunnel current, and then M
The OS transistor Tr is turned on. As a result, the charge as the storage signal accumulated at the connection point N is transferred to the bit line B.
The data is read from L at high speed.

In order to retain the accumulated charge, a low level voltage is applied to the gate of the 3-terminal Esaki tunnel element ET to turn off the MOS transistor Tr with the tunnel current kept to a minimum. . As a result, the connection point N
The electric charge as the storage signal accumulated in the memory is retained with low power consumption.

(Seventh Embodiment) FIG. 13 is an equivalent circuit diagram showing an SRAM cell according to a seventh embodiment of the present invention. Further, FIG. 14 is a cross-sectional view of the storage signal storage portion of the SRAM cell.

The SRAM cell of the present embodiment is a modification of the SRAM cell of the sixth embodiment, and is an example in which the memory signal storage unit having the configuration of FIG. 4 is used. The storage signal storage portion is formed on the SOI substrate, and the buried oxide film 7 is thin. This is because the capacitance at the storage node (connection point N) is increased to increase the amount of stored charge as a storage signal. As a result, even if some leakage current is generated, the stored signal is not lost.

Further, in order to increase the capacitance at the storage node, the p ^-- type impurity diffusion layer 8 is provided in the formation region of the inversion layer. This p ⁻ type impurity diffusion layer 8 narrows the width of the depletion layer of the pn junction and increases the capacitance at the storage node. Depending on the situation, the amount of accumulated charge may be increased by forming a capacitor as in the case of the DRAM cell. In the figure, 9 is a wiring (electrode) for short-circuiting the n ⁺ type source diffusion layer 2 and the p ⁺ type drain diffusion layer 3.

FIG. 15 shows current / voltage characteristics of the SRAM cell of this embodiment during standby and during reading.
During standby, the gate voltage Vg can be lowered sufficiently,
As shown in FIG. 15, the tunnel current is minimized. As a result, the power consumption is extremely small.

Further, at the time of reading, the gate voltage Vg can be raised sufficiently, so that the tunnel current (driving current) is maximized as shown in FIG. as a result,
τ _pd becomes sufficiently small, and the reading speed becomes extremely fast.

The SRAM cell of this embodiment is composed of three elements, namely, a three-terminal Esaki tunnel element ET, ET _L and a MOS transistor Tr. As a result, according to the present embodiment, the conventional SRAM of FIG.
High integration of the same level as the cell is possible.

Therefore, by using the SRAM cell of this embodiment, it becomes possible to realize a highly integrated, low-power-consumption and high-speed operation SRAM.

(Eighth Embodiment) FIG. 16 is an equivalent circuit diagram showing an SRAM cell according to an eighth embodiment of the present invention.

This SRAM cell is a modification of the SRAM cell of the sixth embodiment, and is an example in which the memory signal storage unit having the structure of FIG. 6 is used.

In this embodiment as well, by controlling the gate voltage Vg, as shown in FIG. 17, the current and voltage characteristics similar to those of the sixth embodiment can be obtained during standby and during reading, so that low power consumption and High-speed operation can be realized.

In addition, the SRAM cell of this embodiment is MO
S-transistor Tr _L , 3-terminal Esaki tunnel element E
It is composed of three elements of T and MOS transistor Tr. As a result, according to the present embodiment, it is possible to achieve the same level of high integration as the conventional one.

Therefore, by using the SRAM cell of this embodiment, it is possible to realize a highly integrated, low-power-consumption and high-speed operation SRAM.

In the present embodiment, in order to simplify the circuit operation, the gate of the MOS transistor Tr _{L and} the gate of the 3-terminal Esaki tunnel element ET are made common, but this is, for example, a MOS transistor. It can be easily realized by optimizing the threshold voltage of Tr _L.

(Ninth Embodiment) FIG. 18 is an equivalent circuit diagram showing an SRAM cell according to a ninth embodiment of the present invention.

The SRAM cell of the present embodiment is characterized in that forward-connected three-terminal Esaki tunnel elements ET _L , ET
The gate is independent. That is, the gate voltage Vg1 of the three-terminal Esaki tunnel element ET _L , ET,
Vg2 can be controlled independently by a gate voltage control circuit.

In the case of the present embodiment, the reading of the stored signal,
The holding (waiting) is the same as the previous embodiments, but the memory signal writing method is different from the previous embodiments.

That is, when writing a low-level memory signal, first, with the gate voltage Vg2 of the 3-terminal Esaki tunnel element ET fixed, the gate voltage Vg1 of the 3-terminal Esaki tunnel element ET _L is changed. As shown in FIG. 19, the elements ET and ET are made sufficiently lower than Vg2.
_It is ensured that the number of intersection points A _L of the characteristic curve of _L is one, that is, only one stable state is formed on the low voltage side.

Next, the gate voltage Vg1 is gradually changed to the gate voltage Vg.
Ascending to g2, as shown in FIG. 19, the elements ET, ET
_{When the number} of intersections A ₀ and A ₁ of the characteristic curve of _L is set to two, the system automatically becomes stable on the low voltage side, and a low level memory signal is written.

When writing a high level memory signal,
First, the gate voltage V of the 3-terminal Esaki tunnel element ET
3 terminal Esaki tunnel device ET with g2 fixed
The gate voltage Vg1 of _L is made sufficiently higher than the gate voltage Vg2 so that the number of intersections A _H of the characteristic curves of the elements ET and ET _L is exactly one, that is, the high voltage, as shown in FIG. Only one stable state is formed on the side.

Next, the gate voltage Vg1 is gradually increased to the gate voltage Vg.
20. As shown in FIG. 20, the elements ET and ET are lowered to g2.
_{When the number} of intersections A ₀ and A ₁ of the characteristic curve of _L is set to two, the system automatically becomes stable on the high voltage side, and a high level memory signal is written.

It is possible to set the two stable states of the intersections A _L and A _H as low-level and high-level storage signals, respectively. In this case, the two stable states corresponding to the low-level and high-level storage signals are used. It is necessary to generate two voltages using a voltage generation circuit.

As in the case of the SRAM cell of FIG. 13, it is possible to write the storage signal by using the MOS transistor Tr. In this case as well, two voltages are generated by using the voltage generating circuit. There is a need to.

In this embodiment, the memory signal is written when the gate voltage Vg2 is fixed, but the memory signal can be similarly written even when the gate voltage Vg1 is fixed. FIGS. 21 and 22 show current / voltage characteristic diagrams corresponding to FIGS. 19 and 20 when the gate voltage Vg1 is fixed.

In the conventional SRAM using the Esaki diode, there is no gate electrode, and therefore the current / voltage characteristics cannot be changed by the gate voltage, so the writing method of this embodiment is not possible. .

(Tenth Embodiment) FIG. 23 is an equivalent circuit diagram showing an SRAM cell according to a tenth embodiment of the present invention.

The SRAM cell of this embodiment has a structure in which the refresh circuit 11 is provided in addition to the structure of the seventh embodiment shown in FIG. During standby, refresh circuit 1
1, the pulse voltage is applied to the gate at a constant cycle to restore the memory signal, so-called refresh operation is performed. As a result, it is possible to effectively prevent the destruction of the storage signal due to the loss of the charge as the storage signal accumulated at the connection point N in the form of a leak current. This mode can also be applied to the eighth embodiment shown in FIG.

FIG. 24 shows an example of the SRAM cell array. The SRAM cells (cells) are arranged in a matrix, and the SRAM cells (cells) in the same row are connected to the same word line WL and the SRAM cells (c) in the same column are connected.
(ell) are connected to the same bit line BL. This S
Since the RAM cell array is highly integrated, it is possible to achieve an integration degree of 1 giga or more.

FIG. 25 shows an example of the sensing method. This is a comparison of the magnitude relationship between the voltage (memory voltage) of the storage signal read from the SRAM cell (cell) and the voltage (reference voltage) of the reference signal read from the dummy cell (dummy) by comparing the differential amplifier ( Detection circuit) and, for example, "1" if the storage voltage is greater than the reference voltage.
Is detected and the stored voltage is lower than the reference voltage, it is "0".
Is detected.

When applied to the SRAM cell array of FIG. 24, for example, as shown in FIG.
A dummy cell is provided. The differential amplifier is common. Then, the SRAM cells are sequentially sensed using the column recorder and the row recorder.

(Eleventh Embodiment) FIG. 27 is an equivalent circuit diagram showing an SRAM cell according to the eleventh embodiment of the present invention.

Although the binary memory has been described in the above embodiments, for example, in the case of using the SRAM cell shown in FIG. 27, the gate voltages Vg1 and Vg2 are controlled as follows, As shown at 28, four different voltages are obtained as the voltage Vout at the connection point N.
Therefore, by using the cell configuration shown in FIG. 13 and the sensing method shown in FIG. 26, a four-valued memory becomes possible.

The gate voltages Vg1 and Vg2 are controlled as follows.

By controlling the gate voltages Vg1 and Vg2, the 3-terminal Esaki tunnel element ET _L is turned off and the 3-terminal Esaki tunnel element ET is turned on. In this case, the voltage Vout at the connection point N has a value equal to that of the second voltage power supply Vss.

Further, by controlling the gate voltages Vg1 and Vg2,
The 3-terminal Esaki tunnel element ET _L is turned on, and the 3-terminal Esaki tunnel element ET is turned off. In this case, the voltage Vout at the connection point N has a value equal to that of the first voltage power supply Vdd.

Further, by controlling the gate voltages Vg1 and Vg2,
The 3-terminal Esaki tunnel element ET _L is turned on, and the 3-terminal Esaki tunnel element ET is turned on. In this case, the two stable states (l
2), two different voltages are obtained as the voltage Vout at the connection point N. These voltages are voltages between the voltage power supply Vss and the voltage power supply Vdd.

By controlling the gate voltages Vg1 and Vg2 in this manner, a total of four different voltages can be obtained as the voltage Vout at the connection point N, and a four-valued memory becomes possible.

[0088]

As described above in detail, according to the present invention, 3
By using the memory signal storage unit composed of the terminal Esaki / tunnel element and the load, high integration of the storage signal storage unit,
Low power consumption and high speed operation can be realized at the same time.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram showing a storage signal storage unit of an SRAM cell according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional perspective view of a 3-terminal Esaki tunnel device and a diagram showing symbols.

FIG. 3 is a characteristic diagram showing current-voltage characteristics of a 3-terminal Esaki tunnel element.

FIG. 4 is an equivalent circuit diagram showing a storage signal storage unit of an SRAM cell according to a second embodiment of the present invention.

FIG. 5 is a three-terminal Esaki in the storage signal storage unit of FIG.
Characteristic diagram showing current / voltage characteristics of tunnel element

FIG. 6 is an equivalent circuit diagram showing a storage signal storage unit of an SRAM cell according to a third embodiment of the present invention.

7 is a characteristic diagram showing current-voltage characteristics of a 3-terminal Esaki tunnel element and a MOS transistor in the storage signal storage unit configured as shown in FIG. 6;

FIG. 8 is an equivalent circuit diagram showing a storage signal storage unit of an SRAM cell according to a fourth embodiment of the present invention.

FIG. 9 is a three-terminal Esaki in the storage signal storage unit of FIG.
Characteristic diagram showing current-voltage characteristics of tunnel element and Esaki diode

FIG. 10 is an equivalent circuit diagram showing a storage signal storage unit of an SRAM cell according to a fifth embodiment of the present invention.

11 is a diagram showing current-voltage characteristics of a three-terminal Esaki tunnel element and a resistance element in the memory signal storage section of FIG.

FIG. 12 is an equivalent circuit diagram showing an SRAM cell according to a sixth embodiment of the present invention.

FIG. 13 is an equivalent circuit diagram showing an SRAM cell according to a seventh embodiment of the present invention.

14 is a cross-sectional view of a storage signal storage unit of the SRAM cell of FIG.

15 is a characteristic diagram showing current / voltage characteristics of the SRAM cell of FIG. 13 during standby and during reading.

FIG. 16 is an equivalent circuit diagram showing an SRAM cell according to an eighth embodiment of the present invention.

FIG. 17 is a characteristic diagram showing current / voltage characteristics of the SRAM cell of FIG. 16 during standby and during reading.

FIG. 18 is an equivalent circuit diagram showing an SRAM cell according to a ninth embodiment of the present invention.

FIG. 19 is a characteristic diagram showing current-voltage characteristics when the low-level storage signal of the SRAM cell of FIG. 18 is written.

FIG. 20 is a characteristic diagram showing current / voltage characteristics when the high-level storage signal of the SRAM cell of FIG. 18 is written.

FIG. 21 is another characteristic diagram showing current / voltage characteristics when the low-level storage signal of the SRAM cell of FIG. 18 is written.

22 is another characteristic diagram showing current-voltage characteristics when the high-level storage signal of the SRAM cell of FIG. 18 is written.

FIG. 23 is an equivalent circuit diagram showing an SRAM cell according to a tenth embodiment of the present invention.

FIG. 24 is a diagram showing an example of an SRAM cell array.

FIG. 25 is a diagram showing an example of a sense system.

26 is a diagram for explaining an example in which the sensing method of FIG. 25 is applied to the SRAM cell array of FIG. 24.

FIG. 27 is an equivalent circuit diagram showing an SRAM cell according to an eleventh embodiment of the present invention.

28 is a diagram showing a method of writing a storage signal in the SRAM cell of FIG. 27. FIG.

FIG. 29 is a conventional SRAM using an Esaki diode.
Equivalent circuit diagram of cell

30 is a characteristic diagram showing current-voltage characteristics of the Esaki diodes ED1 and ED2 in the SRAM cell of FIG.

[Explanation of symbols]

Vss ... low level voltage power supply (first voltage power supply) Vdd ... high level voltage power supply (second voltage power supply) ED ... Esaki diode ET ... 3-terminal Esaki tunnel element ET _L ... 3-terminal Esaki tunnel element (Load) L ... Load R ... Resistor Tr ... MOS transistor TrL ... MOS transistor (load) 1 ... P-type silicon substrate 2 ... N ⁺ type source diffusion layer 3 ... P ⁺ type drain diffusion layer 4 ... Gate insulating film 5 ... Gate Electrode 6 ... N ⁺ type inversion layer 7 ... Buried oxide film 8 ... P ^-- type impurity diffusion layer 9 ... Wiring (electrode)

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-5-41520 (JP, A) JP-A-6-112438 (JP, A) JP-A-5-183128 (JP, A) JP-A-3- 278456 (JP, A) JP-A-6-61454 (JP, A) JP-A-9-186251 (JP, A) JP-A-9-186252 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/8244 H01L 27/11 H01L 27/10 JISC file (JOIS)

Claims (3)

(57) [Claims] 1. A semiconductor substrate, a first source diffusion layer of a first conductivity type, which is connected to a first power supply voltage and is selectively formed on a surface of the semiconductor substrate.
Wherein a first drain diffusion layer of the second conductivity type selectively formed on a semiconductor substrate surface, the region sandwiched between the first diffusion layer of the two first alternative region and a source diffusion layer A first three-terminal Esaki tunnel element composed of a first gate electrode provided on the surface of the substrate through a first gate insulating film, and connected to a second power supply voltage, 3 terminal Esaki
A second drain diffusion layer of the second conductivity type selectively formed on the surface of the semiconductor substrate in a region different from the tunnel element, the second drain diffusion layer and the first three-terminal Esaki tunnel A second source diffusion layer of a first conductivity type selectively formed on the surface of the semiconductor substrate in a region different from the element and connected to the first drain diffusion layer;
A second three-terminal Esaki tunnel element composed of a second gate electrode provided on the substrate surface in a region sandwiched by two second diffusion layers with a second gate insulating film interposed therebetween. A semiconductor memory device, wherein the first and second gate electrodes are connected to a refresh circuit. 2. The semiconductor substrate has a second-conductivity-type semiconductor region formed on the substrate with an insulating film interposed therebetween.
2. The semiconductor memory device according to claim 1, wherein the second drain diffusion layer and the first and second source diffusion layers are formed in the semiconductor region of the second conductivity type. 3. The memory circuit applies a pulse voltage to the first and second gate electrodes at a constant cycle, and stores a memory signal stored at a connection point of the first and second source diffusion layers. 3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device has a function of recovering.