JP2508441B2 - Memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention uses a semiconductor device to store predetermined information.
The present invention relates to a memory device such as DRAM (dynamic RAM), and more particularly to a so-called gain cell structure memory device which amplifies and reads information.

B. Summary of the Invention The present invention relates to a memory device for storing predetermined information by using a semiconductor element, the memory cell having a source and a drain connected to a word line and a bit line, respectively, and the MIS transistor. Of the diode connected between the gate and the bit line, and the switch means for applying a predetermined potential to the gate,
The present invention realizes high density of memory cells of a memory device.

C. Conventional Technology As an example of a memory device, a DRAM that stores information in a capacitor in a memory cell is widely known.

Here, the structure of a general DRAM memory cell will be described. First, a memory cell is configured to have one access transistor and one capacitor in one memory cell. For example, a word line serves as a gate of the access transistor. The bit line is connected to one impurity diffusion region of the access transistor, and the capacitor is connected to the other impurity diffusion region of the access transistor.

Then, at the time of reading or writing, a predetermined signal is supplied to the word line, the access transistor is turned on, the capacitor of the memory cell is electrically connected to the bit line, and a predetermined read operation or write operation is performed. . Further, when the memory holding operation is performed, the access transistor is turned off by the signal of the word line, and the information is stored in the form of electric charge in the capacitor which is disconnected from the bit line.

As an array of cells of a memory device having such a memory cell structure, in addition to a folded bit line configuration, an open bit line configuration having a pair of left and right bit lines distributed around a sense amplifier is used. Are known. Then, by adopting such an open bit line configuration, it becomes possible to arrange the memory cells at a high density.

D. Problems to be Solved by the Invention In general, memory devices such as DRAMs are required to have higher densities and miniaturization.

However, when a memory device having a cell configuration including one access transistor and one capacitor as described above is miniaturized, a minute current of the transistor increases due to the subthreshold characteristic. For this reason,
It will be necessary to make the capacitor larger,
This increases the area of the capacitor in the memory cell, which obviously violates the demand for miniaturization.

In addition, reading information from a cell requires a capacitance of, for example, several tens of fF due to the capability of the sense amplifier, and it is difficult to reduce the capacitor even if the memory cell is reduced.

Furthermore, when trying to arrange memory cells in high density,
Although the above-mentioned open bit line configuration has to be adopted, the open bit line configuration has a small noise margin, and it is technically difficult to adopt it in, for example, a 64 Mbit memory device.

On the other hand, as a structure of a memory cell for solving such a problem, a memory device having a gain cell structure for amplifying a signal of a capacitor is considered, but generally, the number of components of the gain cell is large, and the structure is also large. Because of the complexity
High density is not easy.

In view of the above-mentioned problems, it is an object of the present invention to provide a memory device that easily realizes high density of memory cells.

E. Means for Solving the Problems In the present invention, a MIS transistor in which a first impurity diffusion region is connected to a word line and a second impurity diffusion region is connected to a bit line, and one electrode of the bit line is provided. The above-mentioned problem is solved by a memory device having a memory cell including a diode connected to the gate of the MIS transistor and the other electrode connected to the gate of the MIS transistor, and a memory cell including a switch means for applying a predetermined potential to the gate of the MIS transistor.

F. Action In the above MIS transistor, the impurity diffusion regions are connected to the word line and the bit line, respectively. Therefore, the potential of the gate controls the connection / disconnection between the word line and the bit line. That is, at the time of reading, the gate potential can be amplified by the MIS transistor and transmitted to the bit line. Therefore, even if miniaturization is attempted, an open bit line configuration can be achieved without causing a problem with the area of the capacitor or the like. The potential of the gate is given from the bit line through the diode. The charges accumulated in the parasitic capacitance of the gate due to the rectifying action of the diode are retained as they are, and this becomes the storage operation. At the time of writing, it is necessary to reset the charges accumulated in the parasitic capacitance of the gate, but the switch means controls the potential of the gate to a predetermined potential and the charges are reset. With such a memory cell configuration in which only the diode and the switch means are combined with the MIS transistor, reliable storage operation and read / write operation are possible, and easy densification is realized.

G. Embodiment A preferred embodiment of the present invention will be described with reference to the drawings.

First Embodiment First, the structure of the memory device of this embodiment will be described with reference to FIG.

In the memory device of this embodiment, as shown in FIG. 1, the first impurity diffusion region 11 is connected to the word line WL and the second impurity diffusion region 11 is connected to the word line WL.
Of the PMOS transistor 1 as the MIS transistor whose impurity diffusion region 12 is connected to the bit line BL, and the bit line
It has a diode 2 having one electrode connected to BL and the other electrode connected to the gate 13 of the MIS transistor, and a memory cell comprising a switch means SW for applying a predetermined potential to the gate 13 of the MIS transistor. .

In the PMOS transistor 1, the first impurity diffusion region 11 is connected to the word line WL and the second impurity diffusion region 12 is
Are connected to the bit line BL. Therefore, when the PMOS transistor 1 is on, the word line WL and the bit line BL
When the PMOS transistor 1 is off, the word line WL and the bit line BL are non-conductive. Whether the PMOS transistor is turned on or turned off depends on the diode 2 of the PMOS transistor 1.
It is determined by the potential of the gate 13 connected to. Ie the gate
Charges are accumulated in the parasitic capacitance of 13 through the diode 2, and the accumulated charges are used to control the connection / disconnection of the word line WL to the bit line BL. As described above, the PMOS transistor 1 has an amplifying function according to the potential of the gate 13, and therefore a sufficient cell output can be obtained without increasing the area of the capacitor or the like. Also,
Due to the amplification function, a bit line can output an output signal sufficient for reading, and a sufficient noise margin can be secured even with an open bit line configuration. It is preferable that the capacitance of the gate is large, and for example, it is advantageous in operation to set the capacitance to about 10 times that of other capacitors.

In the diode 2, the P-type impurity diffusion region which is one electrode is connected to the bit line BL, and the N-type impurity diffusion region which is the other electrode is connected to the gate 13 of the PMOS transistor. Therefore, due to the rectification function of the diode, the current flows from the bit line BL to the gate of the PMOS transistor 1.
It flows to the 13 side, and this is the gate of the PMOS transistor 1
It will be stored in 13 capacities. Ie, the bit line
The potential of BL can be held in the gate 13 of the PMOS transistor 1 via the diode 2.

The switch means SW can supply the ground potential to the gate 13 of the PMOS transistor 1 in this embodiment. As described above, the gate 13 of the PMOS transistor 1 has
The charge corresponding to the information signal is accumulated through the diode 2, but when the stored contents are rewritten, the accumulated charge needs to be leaked, and therefore the switch means SW is provided. When the switching means SW is turned on, the potential of the gate 13 of the PMOS transistor 1 becomes the ground potential, and the information signal stored in the gate 13 is reset. Further, when the switching means SW is turned off, the gate of the PMOS transistor 1 is
The potential of 13 holds the potential according to the information signal as it is.
A MOS transistor or a bipolar transistor can be used as the switch means, and another element having an intermittent function may be used.

Next, the operation of the memory device according to the present embodiment will be described with reference to FIGS. Note that the signal ΦSW
Is a signal supplied to the switch means SW, the signal ΦWL is the signal (potential) of the word line WL, and the signal ΦBL is the signal (potential) of the bit line. In addition, F is the point F (PM
It shows the potential of the gate 13) of the OS transistor.

First, an example of the write operation of the memory device of this embodiment will be described with reference to FIG.
ΦSW is the potential to be turned off, and the signal ΦBL on the bit line BL
Is the “L” level (low level: ground voltage), and the signal ΦWL on the word line WL is the “H” level (high level: power supply voltage)
Is. At this time, the potential at the point F is "H" level (shown by a solid line in the figure) or "2H" level (a potential about twice the "H" level, a broken line in the figure) according to the previous information signal. Show.)
It becomes either.

Next, at time t ₁ , the signal ΦSW changes from the off potential to the on potential, and the switch means SW is turned on.
Then, the potential at the point F, which is the gate potential of the PMOS transistor 1, is set to the ground voltage, that is, the "L" level. As described above, when the potential at the point F becomes the “L” level, the potential of the bit line BL (signal ΦBL) can be accumulated via the diode 2 at any time. And the word line
The signal ΦWL, which is the potential of WL, changes from the “H” level to the “L” level, and at time t ₂ , the entire area of the memory cell is set to the “L” level potential and is in the reset state.

Next, the switch signal ΦSW is set to the off potential, and the point F is not electrically connected to the ground. Then, at time t ₃ , the write signal (signal ΦBL) is supplied to the bit line BL. When the signal ΦBL is at the “L” level (indicated by the solid line in the figure), the potential at the point F is kept at the “L” level. At this time
The PMOS transistor does not conduct because the source, drain, and gate are all at the "L" level. Conversely, the signal ΦBL
F becomes "H" level (indicated by a broken line in the figure), F
The potential at the point fluctuates from "L" level to "H" level (shown by the broken line in the figure). This is because the charge on the bit line BL is diode 2
This is because it flows into the point F via. At this time, in the PMOS transistor 1, the second impurity diffusion region connected to the bit line BL is at the “H” level and the first impurity connection region connected to the word line WL.
The impurity diffusion region is at "L" level, but the gate is at "H"
It is set to level and turned off. Thus, at time t ₃ , the potential at point F fluctuates according to the information signal, and this is accumulated as the gate capacitance. Also, PMOS transistor 1
Is always turned off regardless of the potential of the gate.

Next, at time t ₄ , the signal ΦWL on the word line WL changes from the “L” level to the “H” level. By thus setting the potential of the word line WL to the “H” level, the information signal accumulated in the gate capacitance is held. That is, by changing the potential of the word line WL to the “H” level, the gate potential (potential at the F point) follows the signal ΦWL of the word line WL, and the potential at the F point is at the “H” level. In case of, the potential rises to the “2H” level (shown by the broken line in the figure), and the potential at point F becomes “L”.
If it is at the level, the potential rises to the “H” level (shown by the solid line in the figure).

By holding the potential at the point F at the “H” level or the “2H” level in this manner, the diode 2 is irrespective of the potential of the bit line BL (swing between the “L” level and the “H” level). Does not conduct, and information is reliably retained. Also,
The PMOS transistor 1 also remains in the off state, and therefore, when the memory cell on the same bit line is selected, the word lines do not become conductive via the bit line.

In the write operation described above, the bit line BL
The timing at which the information signal can appear is not limited to the above time t ₃ ,
The time can be earlier than that. It is also possible to delay the timing of setting the word line WL to the “L” level by inserting a resistor in series with the diode 2. Further, since the PMOS transistor 1 and the diode 2 are turned off during the holding operation, bit line equalization or the like is also possible.

Next, an example of the operation at the time of reading will be described with reference to FIG.

First, at the time of reading, the switch means SW is always in the off state, and the signal ΦS is always at the off potential. Further, the signal ΦWL as the potential of the word line WL is initially set to the “H” level, and the signal ΦBL which is the potential of the bit line BL is reset to the “H” level. The potential at the point F, which is the potential of the gate of the PMOS transistor 1, is set to the “H” level (shown by the solid line in the figure) or the “2H” level (shown by the broken line in the figure) as described above, and at this time the diode 2 and the PMOS transistor 1 are always off.

Next, at time t ₅ , the signal ΦWL on the word line WL is changed from the “H” level to the “L” level. Then, the potential at the point F follows the fluctuation of the signal ΦWL and is brought to the “H” level when it is at the “2H” level (shown by the broken line in the figure), and when it is at the “H” level. It is set to the “L” level (shown by the solid line in the figure).

Due to the potential at the F point, when the potential at the F point becomes the “H” level, the source, drain and gate of the PMOS transistor 1 are all at the “H” level potential.
Therefore, the PMOS transistor 1 is turned off, the potential of the bit line BL does not change, and the signal Φ
BL remains at “H” level. Conversely, the potential at point F is "L"
When the level is set, the PMOS transistor 1 is turned on and the diode 2 is also turned on. That is, the PMOS transistor 1 amplifies the potential at the point F. Then, the signal ΦBL on the bit line BL is pulled to the “L” level via the PMOS transistor 1, and a potential difference is generated on the bit line L to perform a predetermined read.

After that, at time t ₇ , the potential of the word line WL is set to the “H” level again, and the information signal holding operation is resumed.

In the memory device of the present embodiment as described above, the PMOS transistor 1 can amplify and read the electric charge accumulated in the gate capacitance, and therefore, the area of the capacitor is not increased and the sufficient cell output is obtained. Therefore, it is possible to easily realize miniaturization of the memory device. Further, due to the amplification function as described above, an output signal sufficient for reading can be made to appear on the bit line, and a sufficient noise margin can be ensured even with an open bit line configuration, and high density can be achieved. it can.

Further, particularly in the memory device of the present embodiment, by operating the potential of the word line, the charge of the gate capacitance such as the "2H" level can be surely held and the diode and the PMOS transistor can be always turned off. it can. Therefore, the information signal is surely stored, and an accurate memory operation is realized in combination with the above-mentioned amplification function.

Second Embodiment The memory device of this embodiment has the configuration shown in FIG. 4, and in the first embodiment, the MIS transistor used as the PMOS transistor 1 is replaced with an NMOS transistor 21,
Further, the diode 2 is replaced with a diode 22 having an opposite polarity. That is, the NMOS transistor 21 having the first impurity diffusion region connected to the word line WL and the second impurity diffusion region connected to the bit line BL, and one electrode connected to the bit line BL and the NMOS transistor described above. To the gate of the NMOS transistor and the gate of the NMOS transistor, and the gate of the NMOS transistor to a predetermined potential (power supply voltage Vd
It has a memory cell consisting of a switch means SW for giving d).

Like the first embodiment, the memory device of the present embodiment having such a configuration can accumulate charges as an information signal in the gate capacitance of the NMOS transistor 21, and has an amplifying function of the NMOS transistor 21. Therefore, miniaturization can be promoted without requiring an area such as a capacitor, and further, high density can be realized with an open bit line configuration.

Here, the operation of the memory device of the second embodiment will be briefly described. At the time of writing, the switch SW is turned on, the gate potential is set to "H" level (high level), and the diode 22 is turned on. Is written via. At this time, the word line WL is set to "H" level,
When the holding operation is performed, the potential changes from "H" level to "L" level, and the potential of the gate follows this and is at "L" level or "2L" level (twice as low as "L" level. potential)
To be. Then, at the time of reading, the potential of the word line WL is set to the “H” level, and the potential of the bit line BL is given by the amplification of the NMOS transistor 21. That is, the operation of the memory device of the second embodiment is controlled by the potential symmetrical to the operation of the memory device of the first embodiment.

Third Embodiment This embodiment is a specific structural example of the structure of a memory cell, and this embodiment will be described with reference to FIGS. 5 and 6.

That is, FIG. 5 is a cross-sectional view of the memory cell portion of the memory device of the present embodiment, in which the P ⁺ -type first impurity diffusion region 52 and the P ⁺ -type first impurity diffusion region 52 are formed on the surface of the N-type semiconductor substrate 51. The second impurity diffusion region 53 is formed and serves as the source / drain region of the PMOS transistor. This first impurity diffusion region 52
Is connected to a word line, and the second impurity diffusion region 53 is connected to an aluminum wiring layer 57 as a bit line via a P-type impurity region 56 surrounded by an insulating layer 59. Part of the P-type impurity region 56 is a semiconductor region 55 of the N ⁺ -type which is a gate of the PMOS transistor is extended over the insulating layer 54, the N ⁺
The PN junction between the p-type semiconductor region 55 and the p-type impurity region 56 functions as a diode. A gate 58, which constitutes a switch means for resetting to a predetermined voltage, is formed on the upper part of the N ⁺ type semiconductor region 55 functioning as the gate, and when a predetermined voltage is applied to the gate, The potential of the N ⁺ type semiconductor region 55 becomes the ground potential.

This N ⁺ type semiconductor region 55 is a region in which electric charges are particularly accumulated in this embodiment, and its potential follows the potential of the word line to surely retain the information signal as in the first embodiment. Therefore, the N ⁺ type semiconductor region 55 is formed so as to increase the area facing the first impurity diffusion region 52.
Has been formed.

FIG. 6 is a plan view showing a row of memory cells taken out in parallel with the word lines in such a memory device, and a plurality of (n) memory cells are provided on a substrate 61 in the vertical direction in the figure. Each wiring is a bit line BL _{1 to} BL _n . Wirings formed in the horizontal direction in the drawing are word lines WL _m-1 and WL _m . The semiconductor regions 62, which are connected to the bit lines BL _{1 to} Bl _n through the contact holes 64 and to which the ground potential is applied at their ends, are of N-type under the bit lines BL _{1 to} Bl _n and in the vicinity thereof, respectively. The memory cells of the adjacent bits are separated from each other by P-type regions. Then, the semiconductor region 62 having such N-type regions and P-type regions alternately provided.
A semiconductor layer 63 (that is, the gate 58 in FIG. 5) is formed above the semiconductor region 62 with an insulating film interposed therebetween.

In the memory device of this embodiment having such a structure, charges are accumulated in the semiconductor region 55 (that is, the N-type region of the semiconductor region 62 of FIG. 6), and the PMOS transistor is operated by the charges to read data. Done. In particular, in the memory device of this embodiment, when a predetermined voltage is applied to the semiconductor region 63, the region from the N-type region under the bit line BL _n to the N-type region under the bit line BL ₁ is changed. As a result, the ground potential of the end portion is spread over the entire area of the semiconductor region 62 and the reset state is established. With such a configuration, the reset operation is performed over each bit, and a high speed write operation or the like is realized.

In the memory device of the third embodiment, the P type and the N type can be exchanged, respectively.

H. Effect of the Invention As described above, the memory device of the present invention can amplify and read the charge accumulated in the gate capacitance by using the MIS transistor, and therefore, without increasing the area of the capacitor, Sufficient cell output can be obtained, and miniaturization of the memory device can be easily realized. Further, due to the amplification function as described above, an output signal sufficient for reading can be made to appear on the bit line, and a sufficient noise margin can be ensured even with an open bit line configuration, and high density can be achieved. it can.

Further, particularly in the memory device of this embodiment, the information signal is surely stored by the potential control of the word line, and an accurate memory operation is realized in combination with the above-mentioned amplification function.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an example of a memory cell structure of the memory device of the present invention, FIG. 2 is a time chart for explaining the operation at the time of writing, and FIG. 3 is an operation at the time of reading of the memory device. It is a time chart for explaining.
FIG. 4 is a circuit diagram showing another example of the memory cell structure of the memory device of the present invention, FIG. 5 is a sectional view showing a specific structure of still another example of the memory device of the present invention, and FIG. FIG. 6 is a plan view of the above specific structure of still another example of the memory device of the present invention. 1 …… PMOS transistor 21 …… NMOS transistor 2,22 …… Diode BL …… Bit line WL …… Word line SW …… Switch means

Claims (1)

(57) [Claims] 1. A MIS in which a first impurity diffusion region is connected to a word line and a second impurity diffusion region is connected to a bit line.
A memory device including a transistor, a diode having one electrode connected to the bit line and the other electrode connected to the gate of the MIS transistor, and a memory cell including a switch means for applying a predetermined potential to the gate of the MIS transistor. .