JPS63299266A - Memory device - Google Patents

Abstract

PURPOSE:To realize a high density of a memory cell or the like by a method wherein the memory cell is constituted by the following: an MIS transistor whose source and drain are connected to a word line and a bit line, respectively; a diode which is connected between its gate and the bit line; a switching means which impresses a prescribed potential on the gate. CONSTITUTION:A first impurity diffusion region 11 is connected to a word line ML; a second impurity diffusion region 12 is connected to a bit line BL. As a result, if a PMOS transistor 1 as an MIS transistor is in an ON state, the word line WL and the bit line BL are conductive; if it is in an OFF state, the word line WL and the bit line BL are not conductive. An electric charge is stored in the parasitic capacitance of a gate 13 via a diode 2; a connection or a disconnection between the word line WL and the bit line BL is controlled by using this stored electric charge. The PMOS transistor 1 has an amplification function corresponding to a potential of the gate 13. Accordingly, it is possible to obtain a sufficient output of a cell without expanding an area of a capacitor or the like.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a method of storing predetermined information using a semiconductor element.
The present invention relates to memory devices such as RAM (dynamic RAM), and particularly to memory devices having a so-called gain cell structure that amplifies and reads information.

B6 Summary of the Invention The present invention relates to a memory device that stores predetermined information using a semiconductor element, in which the memory cell is connected to an MIS (MIS) whose source and drain are connected to a word line and a bit line, respectively.
By constructing a transistor, a diode connected between the gate of the MIS transistor and the bit line, and a switch means for applying a predetermined potential to the gate, it is possible to increase the density of memory cells, etc. of a memory device. It is something.

C1 Prior Art As an example of a memory device, a DRAM that stores information in a capacitor within a memory cell is widely known.

Here, to explain the structure of a general RAM memory cell, first, each memory cell has one access transistor and one capacitor, and for example, the word line is the gate of the access transistor. The focus line is connected to one impurity diffusion region of the access transistor, and the capacitor is connected to the other impurity diffusion region of the access transistor.

When reading or writing, a predetermined signal is supplied to the word line, the access transistor is turned on, the capacitor of the memory cell is electrically connected to the bit line, and a predetermined read or write operation is performed. .

Furthermore, when performing a memory retention operation, the access transistor is turned off by a signal from the word line, and information is stored in the form of charge in a capacitor that is disconnected from the bit line.

In addition to the folded bit line configuration, the cell arrangement of a memory device having such a memory cell structure includes an open bit line configuration in which a pair of bit lines are distributed to the left and right around a sense amplifier. Are known. By adopting such an open bit line configuration, it becomes possible to arrange memory cells at high density.

D8 Problems to be Solved by the Invention In general, memory devices such as DRAM are required to have higher density and miniaturization.

However, when miniaturizing a memory device having a cell configuration consisting of one access transistor and one capacitor as described above, the small current of the transistor increases due to subthreshold characteristics. Therefore, it becomes necessary to make the capacitor larger, which increases the area of the capacitor in the memory cell, which clearly goes against the demand for miniaturization.

Further, reading information from a cell requires a capacitance of, for example, several + fF due to the capacity of the sense amplifier, and it is difficult to reduce the size of the capacitor even if the memory cell is made smaller.

Furthermore, if you try to arrange memory cells at high density, you will have to adopt the above-mentioned oven bit line configuration.
The oven bit line configuration has a small noise margin and is technically difficult to employ in a 64 Mbit memory device, for example.

On the other hand, a memory device with a gain cell configuration that amplifies the capacitor signal has been considered as a memory cell structure to solve this problem, but the gain cell generally has a large number of components and its structure is also small. Due to its complexity, it is not easy to increase the density.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, it is an object of the present invention to provide a memory device that easily realizes higher density memory cells.

Means for Solving Problem E9 The present invention provides a method for solving problems (Mis) in which the first impurity diffusion region is connected to the word line and the second impurity diffusion region is connected to the bit line.
A memory device having a memory cell comprising a transistor, a diode having one electrode connected to the bit line and the other electrode connected to the gate of the MIS transistor, and a switch means for applying a predetermined potential to the gate of the MIS transistor. This solves the above problems.

F0 action (MIS) In the transistor (MIS), impurity diffusion regions are connected to the word line and the bit line, respectively, and therefore, the disconnection between the word line and the bit line is controlled by the potential of the gate. That is, during reading, the potential of the gate can be amplified by the MISI transistor and transmitted to the bit line. Therefore, even if miniaturization is attempted, the area of capacitors, etc. does not become an issue, and open circuit y
) can be configured in line. The potential of the gate is applied from the bit line via the diode. The charge accumulated in the parasitic capacitance of the gate due to the rectification effect of the diode is held as is, and this becomes a memory operation.

At the time of writing, it is necessary to reset the charges accumulated in the parasitic capacitance of the gate, but the potential of the gate is controlled to a predetermined potential by the above-mentioned switching means, and the charges are reset. With a memory cell configuration in which only such a diode and switch means are combined with an MIS transistor, reliable storage operations, read/write operations can be performed, and high density can be easily achieved.

G. Example Preferred embodiments of the present invention will be described with reference to the drawings.

First Embodiment First, the structure of the memory device of this embodiment will be explained with reference to FIG.

As shown in FIG. 1, the memory device of this embodiment has a first
The second impurity diffusion region 11 is connected to the word line WL, and the second impurity diffusion region 12 is connected to the bit line BL.
PMOS) transistor l as a TS transistor,
One electrode is connected to the bit line BL and the MI
S) the diode 2 whose other electrode is connected to the gate 13 of the transistor; and Mis) the gate 13 of the transistor
The memory cell includes a switch means SW that applies a predetermined potential to the memory cell.

The PMOS transistor 1 has its first impurity diffusion region 11 connected to the word line WL, and its second impurity diffusion region 12 connected to the bit line BL. Therefore, when PMO3) transistor 1 is on, word line WL and bit line BL are electrically connected, and PMOS
) When the transistor 1 is in the off state, the word line WL and the bit line BL are in a non-conducting state. This PMO3I-
Whether the transistor is turned on or off is determined by P
MOS) is determined by the potential of the gate 13 of the transistor 1 connected to the diode 2. That is, charges are accumulated in the parasitic capacitance of the gate 13 via the diode 2, and the accumulated charges are used to control connection and disconnection of the word line WL to the bit line BL. In this way PMOS)
The transistor 1 has an amplification function according to the potential of the gate 13, and therefore a sufficient cell output can be obtained without increasing the area of a capacitor or the like. Further, due to its amplification function, an output signal sufficient for reading can be generated on the bit line, and a sufficient noise margin can be ensured even in an oven bit line configuration. Note that it is preferable that the gate capacitance is large, for example, 10% of the other capacitance.
It is operationally advantageous to approximately double the amount.

The diode 2 has a P-type impurity diffusion region, which is one electrode, connected to the bit line BL, and the PMO 3).
The other electrode, an N-type impurity diffusion region, is connected to the gate 13 of the transistor. Therefore, due to the rectifying function of the diode, current flows from the bit line BL to the gate 13 side of the PMOS transistor 1, which is then transferred to the PMOS transistor 1.
) will be accumulated in the capacitance of the gate 13 of the transistor 1.

That is, the potential of the bit line BL can be held at the gate 13 of the PMOS transistor 1 via the diode 2.

In this embodiment, the switch means SW can apply a ground potential to the gate 13 of the PMOS transistor 1. PMOS) The gate 13 of transistor 1 is
As described above, charges corresponding to the information signal are accumulated through the diode 2, but when rewriting the memory contents, it is necessary to leak the accumulated charges, and for this purpose, the switch means SW is provided. ing. When the switch means SW is turned on, the potential of the gate 13 of the PMO transistor 1 becomes the ground potential, and the potential of the gate 13 of the transistor 1 becomes the ground potential.
The information signal stored in 3 is in a reset state.

Further, when the switch means SW is turned off, the potential of the gate 13 of the PMOS transistor 1 remains at the potential corresponding to the information signal. Note that as the switch means, a MoS transistor or a bipolar transistor can be used, and other elements having an on/off function may also be used.

Next, the operation of the memory device of this embodiment will be explained with reference to FIGS. 2 and 3. In addition, the signal ΦSW
is a signal supplied to the switch means SW, and the signal ΦW
L is a signal (potential) of the word line WL, and signal ΦBL is a signal (Ti level) of the bit line. Further, F indicates the potential at point F (gate 13 of the PMOS transistor) in FIG.

First, an example of the write operation of the memory device of this embodiment will be explained with reference to FIG.
SW is a potential that is turned off, and the signal Φ of the bit line BL
BL is “L” level (low level: ground voltage),
The signal ΦWL on the word line WL is at "H" level (high level; electric fi voltage), and at this time, the potential at point F is at "H" level (indicated by a solid line in the figure) in accordance with the previous information signal. )
Alternatively, it becomes either the "'2 H" level (a potential approximately twice the H level, indicated by the broken line in Figure 1).

Next, at time t1, the signal ΦSW changes from an off potential to an on potential, and the switch means sw is turned on. Then, the potential at point F, which is the gate potential of PMOS transistor 1, is set to the ground voltage, that is, uL" level. When the potential at point F reaches °L" level in this way, it is necessary to It becomes possible to accumulate the potential of the bit line BL (signal ΦBL). Then, the signal ΦWL, which is the potential of the word line WL, is “H”.
The voltage level changes from the level to the "°L" level, and at time tπ, the entire area of the memory cell is brought to the "L'° level potential, resulting in a reset state.

Next, the switch signal ΦSW is set to an off potential, and the point F is not electrically connected to the ground. And the time is also 3 and bit line B
A write signal (signal ΦBL) is supplied to L. signal Φ
When BL is at the "L" level (indicated by a solid line in the figure), the potential at point F remains at the "L" level.

At this time, the PMOS transistor has a source, a drain,
Since all of the gates are at "L" level, they are not conductive.

Conversely, when the signal ΦBL goes to the "H" level (indicated by the broken line in the figure), the potential at point F changes to the °゛L°゛L°゛level H level (indicated by the broken line in the figure). show).

This is because the charge on the bit line BL flows into point F via the diode 2. At this time, in the PMOS transistor 1, the second impurity diffusion region connected to the bit line BL is at the "H" level, the first impurity diffusion region connected to the word line WL is at the "L" level, but the gate is “H”
” level and turns off. In this way, at time t
, the potential at point F fluctuates in accordance with the information signal, and this is accumulated as gate capacitance. Further, the PMO3 transistor 1 is always turned off regardless of the gate potential.

Next, at time t4, the signal ΦWL of the word line WL becomes “°L”.
The level changes from "level" to "°'H" level.

By changing the potential of the word line WL to the "H" level in this way, the information signal stored in the capacitance of the gate is held. That is, by changing the potential of the word line WL to the "H" level, the information signal stored in the capacitance of the gate is held. , the gate potential (potential at point F) follows the signal ΦWL of word line WL, and the potential at point F becomes ゛°H°
If the potential at point F is at the "L" level, the potential rises to the "H" level (as shown by the broken line in the diagram). (indicated by a solid line).

By keeping the potential at point F at the "H" level or "2H" level in this way, regardless of the potential of the bit line BL (which swings between the "L" level and the "°H" level) Diode 2 does not conduct, ensuring that information is retained. PMOS transistor 1 also remains off, so when a memory cell on the same bit line is selected, the word There is no conduction between the wires.

Note that in the write operation described above, the focus line BL
The timing at which the information signal can appear is not limited to the above-mentioned time Lgo, but may also be at a time earlier than that. Also, by inserting a resistor in series with diode 2, the word line WL can be
It is also possible to delay the timing of setting the L" level. Also, during the holding operation, the PMO3) transistor 1
Since the diode 2 is turned off, focus line equalization and the like are also possible.

Next, an example of the operation at the time of reading will be described with reference to FIG.

First, during reading, the switch means SW is always in an off state, and the signal ΦSW is always at an off potential.

Additionally, the signal ΦWL as the potential of the word line WL is “
The signal ΦBL which is at the high level and has the potential of bit 41L
is reset to 'H' level. As mentioned above, the potential at point F, which is the potential of the gate of PMOS transistor l, is at the "H" level (indicated by the solid line in the figure) or the "2H" level (indicated by the broken line in the figure), and at this time, the diode 2
and PuO2) The transistor 1 is always in an off state.

Next, at the time, the signal ΦWL of the word line WL is set to “H”.
level to “°L” level.

Then, the potential at the above point F follows the fluctuation of the signal ΦWL, and when it was at the "2H" level, it becomes the "H" level (
(indicated by the broken line in the figure), and when it is at the "H" level, it is set to the "L" level (indicated by the solid line in the figure).

Due to this potential at point F, the potential at point F first becomes “
When the voltage reaches the H'' level, the source, drain, and gate of the PMOS transistor 1 are all at the H level potential, so the PMOS transistor l is turned off, and the potential of the bit line BL does not fluctuate ( , as shown by the broken line in the figure, the signal ΦBL remains at the "H" level. Conversely, when the potential at point F is set to the "L" level, the PMOS transistor 1 is turned on, and the diode 2 is also turned on. In other words, the potential at point F is amplified by PuO2) transistor 1. Then, bit line B
The L signal ΦBL is pulled to the "L" level via the PMO3I-transistor 1, and a potential difference is generated on the bit line, so that a predetermined readout is performed.

Thereafter, at a certain time, the potential of the word line WL is again set to the "H" level, and the information signal holding operation is resumed.

The memory device of this embodiment as described above can amplify and read out the charge accumulated in the gate capacitance by the PMOS transistor 1, and therefore can achieve sufficient cell output without increasing the area of the capacitor. This makes it possible to easily realize miniaturization of memory devices.

In addition, the amplification function described above allows output signals sufficient for reading to appear on the bit line, and even with an open bit line configuration, a sufficient noise margin is ensured, making it possible to achieve higher density. can.

In particular, in the memory device of this embodiment, the electric potential of the word line is manipulated to ensure that the charge of the gate capacitance, such as 2H'' level, is held, and the diode and PMOS transistor are always kept in the off state. Therefore, the information signal is reliably stored, and in combination with the amplification function described above, accurate memory operation is achieved.

Second Embodiment The memory device of this embodiment has the configuration shown in FIG. 2 was replaced with a diode 22 with the opposite polarity. That is, the first impurity diffusion region is connected to the word line WL, and the second impurity diffusion region is connected to the word line WL! An NMOS transistor 21 connected to the bit line BL, and the other tF connected to the gate of the NMOS transistor 21 whose one electrode is connected to the bit line BL
The memory cell includes a diode 22 connected to NMO3), and a switch means SW for applying a predetermined potential (ta voltage Vdd) to the gate of the transistor NMO3).

The memory device of this embodiment having such a configuration has the first
Similar to the embodiment, the charge as an information signal can be accumulated in the gate capacitance of the NMO3) transistor 21, and the amplification function of the NMO3) transistor 21 allows miniaturization without requiring the area of a capacitor or the like. Furthermore, it is possible to achieve high density by using an open bit line configuration.

Here, to briefly explain the operation of the memory device of the second embodiment, during writing, the switch means SW is turned on, the potential is set to "H" level (high level), and the diode is turned on. Writing is done via 22. At this time, the word line WL is set to the H level, but when performing the holding operation, the word line WL is changed from the H level to the L level.
level, and the gate potential follows this and is set to the "°L" level or "2L" level (a potential twice as low as the "L" level), and at the time of reading, the word line WL The potential of NMO3 is set to “H” level, and NMO3
) The potential of the bit line BL is given by the amplification of the transistor 21. That is, the operation of the memory device of the second embodiment is different from the operation of the memory device of the first embodiment.
It will be controlled by symmetrical potentials.

Third Embodiment This embodiment is a specific example of the structure of a memory cell, and will be described with reference to FIGS. 5 and 6.

That is, FIG. 5 is a cross-sectional view of the memory cell portion of the memory device of this embodiment, in which a P-type first impurity diffusion region 52 and a P-type first impurity diffusion region 52 are formed on the surface of an N-type semiconductor substrate 51. 2 impurity diffusion regions 53 are formed and serve as source/drain regions of the PMO3) transistor. This first impurity diffusion region 52 is connected to a word line, and the second impurity diffusion region 53 is a P-type impurity region 5 surrounded by an insulating layer 59.
6 to an aluminum wiring layer 57 as a bit line. A part of the P-type impurity region 56 extends on the insulating layer 54 and becomes the gate of the PMO3) transistor.
A 9-type semiconductor region 55 is formed, and a PN junction between the N''-type semiconductor region 55 and the P-type impurity region 56 functions as a diode. A gate 58 constituting a switch means for resetting to a predetermined voltage is formed above the N-type semiconductor region 55 functioning as the gate, and when a predetermined voltage is applied to this gate, The potential of the N′ type semiconductor region 55 becomes the ground potential.

This N9 type semiconductor region 55 is a region where charges are particularly accumulated in this embodiment, and as in the first embodiment,
Since the potential follows the potential of the word line and the information signal is reliably held, the N-type semiconductor region 55 is formed so as to increase the area facing the first impurity diffusion region 52. has been done.

FIG. 6 is a plan view of one row of memory cells parallel to the word line in such a memory device, in which a plurality (n) of memory cells are provided on a substrate 61 in the vertical direction in the figure. Each wiring is a bit line BL, -BL. In addition, the wiring formed in the horizontal direction in the figure is the word line WL,...
It is WL.

The semiconductor regions 62 which are connected to each of the pinto lines BL+ to Bl, l via each contact hole 64 and to which a ground potential is applied at their ends are connected to bit lines BL1 to B+, respectively.
The lower part of the bit and the vicinity thereof are N-type regions, and the memory cells of adjacent bits are separated from each other by P-type regions. Then, on the semiconductor region 62 in which N-type regions and P-type regions are provided alternately, a semiconductor layer 63 (that is, a fifth
A gate 58) shown in the figure is formed.

In the memory device of this embodiment having such a structure, charges are accumulated in the semiconductor region 55 (that is, the N-type region of the semiconductor region 62 in FIG. 6), and the charges cause the PMO3
) Reading is performed by operating the transistor. In particular, in the memory device of this embodiment, the semiconductor region 6
When a predetermined voltage is applied to bit line BL, conduction occurs from the N-type region at the bottom of bit line BL to the N-type region at the bottom of bit line BL, and therefore the ground potential at the end becomes The entire area of the semiconductor region 62 is in a reset state. With such a configuration, the reset operation is performed over each bit, and high-speed write operations and the like are realized.

Note that in the memory device of the third embodiment, the P type and the N type can be exchanged.

H4 Effects of the Invention As described above, the memory device of the present invention can amplify and read out the charge accumulated in the gate capacitance using the MIS transistor, and therefore the memory device of the present invention can be used without increasing the area of the capacitor. Accordingly, it is possible to obtain a cell output with a high level of cell output, and it becomes possible to easily realize miniaturization of a memory device. In addition, the amplification function described above allows output signals sufficient for reading to appear on the bit line, and even with an open bit line configuration, a sufficient noise margin is ensured, making it possible to achieve higher density. can.

Further, particularly in the memory device of this embodiment, the information signal is reliably stored by controlling the potential of the word line, and in combination with the amplification function described above, accurate memory operation is realized.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of the memory cell structure of the memory device of the present invention, FIG. 2 is a time chart for explaining the write operation, and FIG. 3 is the read operation of the memory device. It is a time chart for explanation. Further, FIG. 4 is a circuit diagram showing another example of the memory cell structure of the memory device of the present invention, FIG. 5 is a sectional view showing a specific structure of still another example of the memory device of the present invention, and FIG. is a plan view of the above-mentioned specific structure of still another example of the memory device of the present invention. i −−−１・−１−−−−−−−−−−−−・・−
...--PMO3) transistor 21--1----
・・・・・・・・・−・−・−NMO3) Transistor 2.
22-1・−・・・−・・−・・−・−Diode B
L ・・・・−・−１−−−−−・・・−１−−・
−・−Bit line W L , −−−−−−・・・・−・
−・−・−−−−1・・ Word line SW−・・・・−・
−・−・・−・・・・・・・・・・Sinch means patent applicant Akira Koba (and 2 others) Patent attorney representing Sony Corporation Shun no i? 4th
Figure 5

Claims (1)

[Scope of Claims] A MIS transistor in which a first impurity diffusion region is connected to a word line and a second impurity diffusion region is connected to a bit line, and one electrode is connected to the bit line, and the MIS transistor A memory device comprising a memory cell comprising: a diode whose other electrode is connected to the gate of the MIS transistor; and a switch means for applying a predetermined potential to the gate of the MIS transistor.