JP3045594B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, the present invention relates to a semiconductor memory device such as a dynamic ram (DRAM) having a dummy cell array formed around an actual cell array.

In recent years, DRAMs have been required to have a so-called refresh time increased during a period in which cell information is updated with an increase in the degree of integration.

For example, a DRAM of 256 KB has 4 ms.
The refresh time was 8 ms for 1 MBit, 4
In the case of MBit, the ability is doubled for each generation of 16 ms.

Further, in recent years, a battery backup mode having a long refresh time has been required to reduce power consumption.

Therefore, it is necessary to secure a sufficient refresh time for the device.

[0006]

2. Description of the Related Art FIG. 4 shows a block diagram of a general DRAM. The DRAM has a memory cell section 1 for holding data, an address buffer 2a, a predecoder 2b for selecting a cell corresponding to an input address signal, a row decoder 3, a column decoder 4a, a sense amplifier 4b, a data input buffer 5, and a data output. Buffer 6, a refresh address counter 7 for specifying cells to be refreshed,
It comprises a mode controller 8, generators 9a, 9b, 9c for generating various timing signals, a substrate bias generator 10 for applying a bias voltage to the substrate, and the like.

FIG. 5 shows a configuration diagram of a memory cell section. FIG.
The memory cell section 11 shown in FIG. 1 stores 4 MBit of data.

The entire memory cell section 11 has a configuration in which blocks 11a each composed of 512 Kbit cells are collected for eight blocks.

Also, a block 11 composed of 512 KB
Reference numeral a denotes a 16-KB cell array 12a for 32 KB, a column decoder 4a, and a sense amplifier / column decoder section 12b in which a sense amplifier 4b is formed.

The cell array 12a for 32 Kbits further includes a real cell array section 12a- ₁ and a dummy pattern section 12a.
_-2 . The actual cell array part 12a- ₁ is 32
Real cells of KBit are arranged according to a predetermined rule.

The actual cell comprises a selection transistor Tr ₁ and a storage capacitor C _S as shown in FIG. The drain of the selection transistor Tr ₁ is connected to the bit line BL, and the source of the selection transistor Tr ₁ is connected to the storage capacitor C _S.
The word line WL of the gate of the selection transistor Tr ₁
And the selection transistor Tr ₁ is switching-controlled in accordance with the signal level of the word line WL, and the storage capacitor C 1
Information is stored depending on whether or not to accumulate charges in _S.

The dummy pattern section 12a- ₂ has the same pattern as the real cell array section 12a- _1.
It is formed to maintain the regularity of the end of a- ₁ .

The main purpose of the conventional dummy pattern is to maintain the regularity of the pattern, and it has been considered that the dummy pattern hardly affects the electrical characteristics. However, in the request for increasing the refresh time, the actual cell array unit 12a _-1
It was found that the refresh time of the cell at the end of was bad. This is because electrons generated under the field oxide film outside the end of the actual cell array portion enter cells at the end of the actual cell array portion. Therefore, as a countermeasure, it is conceivable that a conventional dummy pattern is provided with a positive potential and electrons generated therein are taken in.

FIG. 7 is a sectional view showing an example of a conventional dummy pattern. FIG. 7 is a cross-sectional view of the stacked capacitor cell, in which 13 denotes a semiconductor substrate.

A storage node 14, a word line 15, and a bit line 16 are formed on a semiconductor and a substrate 13. Storage node 1
4 contacts the diffusion layer 17a formed on the semiconductor substrate 13, and the bit line 16 contacts the diffusion layer 17b.

At this time, the word line 15 is formed so as to intersect with the diffusion layers 17a and 17b via the insulating layer 18.

Further, a positive voltage Vcc has been applied to the bit line 16 in order to capture electrons generated outside the real cell array portion into the diffusion layer 17b in a dummy pattern.

[0018]

[SUMMARY OF THE INVENTION] However, the dummy pattern of this type of conventional semiconductor memory device, the voltage V _CC is applied to the bit line 16, charges are supplied to the diffusion layer 17b which is connected to the bit line 16 Therefore, electrons generated outside the cell are absorbed, but the diffusion layer 1
7 a crosses the word line 15 via the insulating layer 18 and is not connected, so that electrons generated outside the cell pass under the diffusion layer 17 a below the storage node 14 and pass through the cell at the end of the actual cell array portion. And the refresh time cannot be increased.

The present invention has been made in view of the above points, and has as its object to provide a semiconductor memory device capable of improving refresh characteristics while maintaining regularity of a pattern at an end of an actual cell array.

[0020]

According to the present invention, a dummy cell having substantially the same pattern as the real cells is arranged around a real cell array in which a plurality of real cells for storing information by a storage capacitor and a selection transistor section are arranged. In a semiconductor memory device formed by forming a cell array comprising: a conductive layer connected to either one of a diffusion layer forming a source and a drain of the select transistor unit over the entire dummy cell array; A gate electrode of the select transistor section is formed directly on the diffusion layer so that a diffusion layer forming a source of the select transistor section is connected to a diffusion layer forming a drain of the select transistor section, and a charge is supplied to the conductive layer. Thereby, electric charges are supplied to the diffusion layer.

[0021]

The storage capacitor portion of the dummy cell array is formed so as to be connected integrally and continuously, and the diffusion layer forming the drain of the selection transistor portion is the same as the one forming another conductive layer or the storage capacitor portion. Is connected to the conductive layer.

For this reason, electric charges are supplied to the conductive layer of the storage capacitor portion and other conductive layers, and this is supplied to all the diffusion layers of the dummy cell array.

Alternatively, in the case where the connection to the diffusion layer is made only by the conductive layer of the storage capacitor portion, if the charge is supplied to the conductive layer of the storage capacitor portion, the charge is supplied to all the diffusion layers of the dummy cell array as described above. Is done.

Therefore, electric charges can always be supplied to all the diffusion layers of the dummy cell array, and electrons generated outside the real cell array can be taken into the diffusion layer to prevent the electrons from entering the real cell array.

Further, since the dummy cell array can be formed in substantially the same pattern as the actual cell array, regularity of the pattern can be maintained even at the end of the actual cell pattern, and the occurrence of defects in the actual cell pattern can be prevented.

[0026]

FIG. 1 is a sectional view of an essential part of an embodiment of the present invention, and FIG. 2 is a plan view of an essential part of an embodiment of the present invention. The figure shows a view of a dummy pattern portion formed around the real cell array. In the figure, A shows a real cell pattern, B shows a dummy cell pattern, and 19 shows a semiconductor substrate. Semiconductor substrate 1
Reference numeral 9 denotes a P-type semiconductor, and on the semiconductor substrate 19, dummy cell storage nodes 20 _{-1 to} 20 _{-4 serving} as storage capacitor units, select transistor units Q _{1 to} Q ₄ , and word lines 22 and 22 _{-1 serving as} gate electrodes. 22 _-4 , and the bit line 21 are formed.

The dummy cell storage node 20 is connected to the storage capacitor 2
N-type diffusion layer 2 formed on semiconductor substrate 19 at 0 _{-1 to} 20 _-4
Contact with 3 _-1 to 23 _-4 . All the dummy storage nodes 20 are integrally connected.

The bit line 21 has N-type diffusion layers 24 _-1 and 24 _-2.
It is wired so that it contacts. At this time, the dummy pattern is substantially the same as the pattern of the real cell array as shown in FIG.

The storage nodes 20 _-1 and 20 _-2 have a drive potential Vcc.
Alternatively, a potential similar thereto, for example, 1/2 Vcc is supplied.

The driving potential Vcc is applied to the storage nodes 20 _-1 and 20 _-2.
Is supplied, the drive potential Vcc is also supplied to the diffusion layers 23 _-1 and 23 _-2 which are in contact with the storage nodes 20 _-1 and 20 _-2 .

The diffusion layers 24 _-1 and 24 _-2 are connected to the bit line 2.
1, the driving potential Vcc is supplied to the diffusion layers _24-1 and _24-2 in the same manner.

The dummy pattern having such a structure is formed over the entire periphery of the actual cell array. For this reason, all the diffusion layers 23 ₋₁ , 2 in the outer peripheral portion of the actual cell array
A driving potential Vcc or a similar potential 1/2 Vcc is supplied to 3 _-2 , 24 _-1 and 24 _-2 .

Therefore, the electrons generated under the field oxide film outside the actual cell array are diffused in the dummy pattern diffusion layer _23-1.
23 _-4 , 24 _-1 , and 24 _-2 , and do not enter the actual cell array.

As a result, the electric charge accumulated in the actual cell can be held longer, so that the refresh time can be set longer.

As described above, the dummy pattern can be constituted by the same pattern as that of the actual cell array, and all the diffusion layers 23 _-1 to 23 _-4 , 2 of the dummy pattern can be formed.
A potential can be applied to 4 _-1 and _24-2 .

Therefore, it is possible to prevent electrons from entering the actual cell while maintaining the regularity of the pattern in the cell array.

Therefore, the occurrence of actual pattern defects can be prevented, the yield can be improved, and the refresh characteristics can be improved by preventing the intrusion of electrons into the actual cells.

[0038] The electrode 20 _-1 of the storage node C _S in the present embodiment has been integrally formed 20 _-2 across the dummy cell array B, not limited to this, the electrode 2
_{Instead of} 0 ₋₁ and 20 ₋₂ , the bit line 21 may be formed integrally over the entire dummy cell array B.

FIG. 3 is a sectional view of a main part of another embodiment of the present invention. In the figure, reference numeral 25 denotes a semiconductor P-type substrate.

On the semiconductor substrate 25, the storage nodes 26 _{-1 to} 26 _-4 constituting the storage capacitor section and the selection transistors Q ₅ to
Q ₈ is formed.

In the select transistors Q _{5 to} Q ₈ , the sources are formed by the N-type diffusion layers 27 _-1 , 27 _-2 , 27 _-3 and 27 _-4 , and the drains are formed by the N-type diffusion layers 28 _-1 and 28 _-2. It is formed. Diffusion layers 27 _{-1 to} 27 _-4 , 28 _-1 , and 28 _-2 are in contact with conductive layer 29 in which storage nodes and bit lines are integrally and continuously formed.

By supplying a drive potential Vcc or a similar potential, for example, 1/2 Vcc to the conductive layer 29, a potential can be supplied to all the diffusion layers 26.

As a result, electrons generated outside the actual cell array are absorbed by the diffusion layer 26.

Since the conductive layer 29 integrally and continuously forms the storage nodes and the bit lines, the pattern can be made substantially the same as the pattern of the actual cell array. Therefore, defects in the actual cell array can be prevented. In addition, since it is possible to prevent electrons generated outside the real cell array from entering the real cell array, it is possible to reduce a decrease in accumulated charges in the real cell array and to lengthen the refresh time.

[0045]

As described above, according to the present invention, the charge can be supplied to the diffusion layer forming the selection transistor of the dummy cell array while maintaining the regularity of the pattern, and the electrons generated outside the actual cell array can be diffused. Since it can be taken into the layer, it is possible to prevent the intrusion of electrons into the real cell array without generating a pattern defect of the real cell array, and therefore, it is possible to improve the yield and the refresh characteristics. It has the features of

[Brief description of the drawings]

FIG. 1 is a sectional view of a main part of an embodiment of the present invention.

FIG. 2 is a plan view of a main part of one embodiment of the present invention.

FIG. 3 is a sectional view of another embodiment of the present invention.

FIG. 4 is a block diagram of a DRAM.

FIG. 5 is a configuration diagram of a memory cell unit of the DRAM.

FIG. 6 is a circuit configuration diagram of a real cell.

FIG. 7 is a cross-sectional view of an example of the related art.

[Explanation of symbols]

 13, 19, 25 Semiconductor substrate 14, 20, 26 Storage node 16, 21 Word line 15, 22 Bit line 17, 23, 24, 27, 28 N-type diffusion layer A Real cell array B Dummy cell array

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/108 H01L 21/8242

Claims (2)

(57) [Claims] 1. A real cell array (A) in which a plurality of real cells (a) for storing information by a storage capacitor (C _S ) and a selection transistor section (Q ₁ , Q ₂ ) are arranged around a real cell array (A). In a semiconductor memory device having a cell array (B) formed by arranging dummy cells (b) having substantially the same pattern as that of (a), the select transistor sections (Q _{1 to} Q ₄ ) are formed over the entire dummy cell array (B). Diffusion layer (23 _-1) forming the source of
To 23 _-4 ) are added to the conductive layer (2) forming the storage capacitor portion (C _S ).
0), and a diffusion layer (24 _-1 , 24 _-2 ) forming a drain of the selection transistor section (Q ₁ -Q ₄ ) is connected to a conductive layer (21) forming a bit line (BL). By supplying electric charges to the conductive layers (20) and (21), electric charges are supplied to the diffusion layers (23 _-1 to 23 _-4 , 24 _-1 and 24 _-2 ). A semiconductor memory device. 2. A real cell array (A) comprising a plurality of real cells in which information is stored by a storage capacitor section (C _S ) and a selection transistor section (Q ₃ , Q ₄ ). Dummy cell array (B) with the same pattern as
The diffusion layer (27 _-1 ) forming the source of the select transistor section (Q _{5 to} Q ₈ ) over the entire dummy cell array (B).
~ 27 _-4) and the selection transistor (Q ₅ diffusion layer forming the drain of _{~Q 8) (28 -1, 28} -2) connecting the conductive layer (29) the storage capacitor of (C _S) By using a conductive layer for forming an electrode or a bit line (BL) and supplying a charge to the conductive layer (29),
Diffusion layers (27 _{-1 to} 27 _-4 , 28 _-1 , 28) forming sources and drains of the selection transistors (Q _{5 to} Q ₈ )
_-2 ) A semiconductor memory device characterized by supplying a charge to the semiconductor memory device.