JP2555870B2 - Semiconductor memory device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a high density and low power consumption MOS static memory.

[0002]

2. Description of the Related Art Among conventional MOS static memory cell construction methods, Japanese Patent Publication No. 53-148989 is known as a method of using a resistance as a load. It is shown in FIG. In the figure, 1 to 4 are n-channel MOSTs, 1 and 2 are transfer MOSTs, and 3 and 4 are drive MOSTs.
Reference numerals 5 and 6 are data lines, 7 is a word line, 8 and 9 are load resistors, and the information stored in the information storage nodes 12 and 13 is held by supplying a current from a power supply line 10 (potential V _CC ). ing. Reference numeral 11 is a ground line (potential V _SS ). The load resistances 8 and 9 are formed of a polycrystalline silicon layer (polysilicon layer) of the same layer as that forming the gates of the MOSTs 1 to 4 or a laminated polysilicon layer different from the gate material. It is formed by leaving a part of the polysilicon layer as an intrinsic semiconductor or forming a region having a low impurity concentration. Information is written in or read from the memory cell through the data lines 5 and 6 by changing the word line 7 from a low level voltage to a high level voltage.

[0003]

In recent years, static RAMs have tended to have a large capacity due to advances in fine processing technology, and accordingly, it is necessary to reduce the occupied area of memory cells. Based on the above-mentioned conventional memory cell,
As a result of examining the feasibility of realizing a larger-capacity static RAM, the following drawbacks became clear.

Α generated from impurities in the package material
Line particles irradiate the surface of the semiconductor memory chip and invert the information stored in the storage node of the memory cell to generate a random error. Regarding the so-called soft error, in the present memory cell, as the memory cell area becomes smaller, the storage capacity C of the memory cell (the gate parasitic to 12 and 13 of 14, 15 in FIG. 1 is a capacitance, the diffusion layer capacitance, etc.)
Becomes smaller and the accumulated charge amount Q (= C · V, V accumulated voltage)
Becomes smaller. As a result, the frequency of soft errors generated by the same α-ray particle emission is higher than before. Therefore, in order to increase the resistance to soft error to the same level as in the conventional case, some means for making the accumulated charge amount approximately the same as in the conventional case is required.

An object of the present invention is to overcome the above-mentioned drawbacks of the prior art and to provide a static memory cell having a small occupied area which can realize a large capacity static RAM. Further, according to the present invention, the occupied area is small and the reliability is the same as the conventional one. A semiconductor memory device suitable for a large capacity memory can be provided.

[0006]

The basic concept of the present invention will be described with reference to FIG. FIG. 2 shows a circuit configuration diagram of the present invention. In the figure, 14 to 15 are capacitances parasitic on the memory cells (for example, gate capacitances and diffusion layer capacitances parasitic on the storage nodes 12 and 13), and 16 to 17 storages newly added to the storage nodes 12 and 13. Capacity.
A feature of the present invention is that the storage capacity of the memory cell is realized by a newly formed capacity different from the conventional parasitic capacity.

Among the inventions disclosed in the present application, typical ones are summarized as follows.

That is, the semiconductor memory device according to the present application is
The memory cell includes a plurality of word lines, a plurality of data lines, and a plurality of memory cells arranged at intersections of the word lines and the data lines, the memory cells including two drive MOS transistors and two transfer MOS transistors. And two load elements, the gate of the transfer MOS transistor is connected to the word line, the drain of the drive MOS transistor is connected to the data line via the source / drain path of the transfer MOS transistor, and the drive The drain of the MOS transistor is connected to one end of the load element, the other end of the load element is connected to a first operating potential point, and the source of the drive MOS transistor is connected to a second operating potential point. The gate of the MOS transistor is connected to the one end of the load element, and the gate of the drive MOS transistor is connected. The gate is formed of a first polycrystalline silicon layer on a semiconductor substrate via an insulating film, and the load element is formed of a second polycrystalline silicon layer above the first polycrystalline silicon layer, One end of the second polycrystalline silicon layer is connected to the source / drain of the transfer MOS transistor, and the other end of the second polycrystalline silicon layer is connected to the first operating potential point. Is formed so as to have a high impurity concentration, and is further formed so as to oppose the one end of the second polycrystalline silicon layer via an insulating film. It is characterized in that it has three polycrystalline silicon layers.

[0009]

Since the storage capacitance of the memory cell is realized by a newly formed capacitance different from the conventional parasitic capacitance, in the semiconductor memory device according to the present invention, as a result of an increase in the accumulated charge amount due to the storage capacitors 16 to 17, -A semiconductor memory device that is resistant to errors can be obtained. Further, capacitance can be added to the storage node of the memory cell by making the end portions of the third polycrystalline silicon layer and the second polycrystalline silicon layer face each other through the insulating film.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 3 is a sectional structural view of the first embodiment of the present invention. 18 to 19 in a p-type substrate
An n-channel MOST having an insulating isolation layer 1 and n-type impurity layers 22 and 23 as drains, sources and 26 as gates.
T35 (source and drain are not shown in this cross-sectional view because they exist across the gate in the direction perpendicular to the paper surface). After that, the capacitors 16 and 17 in FIG.
2 and 13, and 23 and 27 in FIG. 3) and an insulator (SiO ₂
It is configured by sandwiching a film or a composite film of SiO ₂ and SiN ₃ N ₄ ). After forming the insulator layer 32 on this, a load resistance is formed by the third polysilicon layer 33. A power supply voltage or a ground potential is applied to the electrode 30.

The structure in which the load resistance is formed after the new capacitance is formed, like the structure of the present invention, can shorten the heat treatment time of the polysilicon layer forming the load resistance.
This is very effective because it can reduce the fluctuation of the load resistance value due to the heat treatment time.

FIG. 4 is a sectional view showing a second embodiment of the present invention. The feature of the present invention is that the electrode 30 is fixed to the power supply voltage (V _CC ). In this structure, the electrode on the V _CC side of the load resistance of 33 and the electrode of 30 can be shared, and wiring of the electrode of 30 can be performed without increasing the occupied area of the memory cell, which is very effective. is there.

FIG. 5 shows a sectional structural view of the third embodiment of the present invention. The feature of the present invention is that the electrode 30 is fixed to the ground potential (V _SS ). In this structure, the electrode of 30 can be shared with the terminal of V _SS example of 36 memory cells, and the wiring of 30 electrodes can be performed without increasing the occupied area of the memory cell, which is very effective. is there.

FIG. 6 shows a pattern layout diagram of the fourth embodiment of the present invention. MOSTs 109, 110, 111 and 112 are formed by the n-type impurity diffusion layers 101 and 102 and the first polysilicon layer 103, 104 and 105, and the capacitors 16 and 17 of FIG. Two
12 or 13) and a second polysilicon layer 106. The capacity of 16 (17) in FIG. 2 is 1
The upper part of the n-type impurity diffusion layer 13 (115) and 114
It can be formed on the first polysilicon layer (116). Not only may the electrode 106 be common to all memory cells, but also the load resistor (107, 108) in the area occupied by the storage node in the pattern layout drawing.
Which is formed of a third polysilicon layer) and a storage region for connecting a storage node, and is extremely effective because it can be used to form a capacitance for newly adding all areas. . Also, the electrode V _{CC which is} 106,
Since it may be fixed to either _Vss , flexibility can be given to the design of the memory cell, which is more effective.

As described above, according to the present invention, it is possible to provide a static memory cell which occupies a small area and has high resistance to α rays, and has a large capacity static R.
The effect is remarkably large for the realization of AM.

Although the present invention has been described with reference to a memory cell formed on a p-type substrate, it goes without saying that the present invention can be applied to a memory cell formed in a p-type well in an n-type substrate.

Even if the impurity type names and the well type names used in the description of the present invention are reversed, the effect of the present invention is the same. In addition, the transfer MOST is a p-channel type M
It goes without saying that the same effect can be obtained by applying the OST and the drive MOST to the memory cell in which the n-channel type MOST is applied.

[0018]

Since the storage capacity of the memory cell is realized by a newly formed capacity different from the conventional parasitic capacity,
In the semiconductor memory device according to the present invention, the storage capacitors 16 to 1
As a result of the increase in the accumulated charge amount by 7, a semiconductor memory device resistant to soft error can be obtained. Further, capacitance can be added to the storage node of the memory cell by making the end portions of the third polycrystalline silicon layer and the second polycrystalline silicon layer face each other through the insulating film.

[Brief description of drawings]

FIG. 1 is a circuit diagram illustrating a semiconductor memory device according to a conventional technique.

FIG. 2 is a circuit diagram showing a semiconductor memory device according to an embodiment of the present invention.

FIG. 3 is a structural cross-sectional view showing a configuration of first, second and third embodiments of the present invention.

FIG. 4 is a structural cross-sectional view showing a configuration of first, second and third embodiments of the present invention.

FIG. 5 is a structural cross-sectional view showing a configuration of first, second and third embodiments of the present invention.

FIG. 6 is a pattern layout diagram showing a fourth embodiment of the present invention.

[Explanation of Codes] 16, 17 ... Capacities newly added to storage nodes, 29,
Electrodes for forming storage capacitors 106, 16 and 17.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshiaki Yamanaka 1-280 Higashi Koikeku, Kokubunji City, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (72) Katsuhiro Shimoto 1-280 Higashi Koikeku, Kokubunji, Tokyo Hitachi Ltd. Central Research Laboratory, Ltd. (72) Toshiaki Masuhara, Toshiaki Masuhara 1-280, Higashi Koigokubo, Kokubunji, Tokyo (56) Reference, Japanese Patent Laboratory JP-A-56-107574 (JP, A) JP-A-58-165376 (JP) JP, A) JP 59-167051 (JP, A)

Claims (4)

(57) [Claims] 1. A plurality of word lines, a plurality of data lines, and a plurality of memory cells arranged at intersections of the word lines and the data lines, wherein the memory cells include two drive MOS transistors. It includes two transfer MOS transistors and two load elements, the gate of the transfer MOS transistor is connected to a word line, and the drain of the drive MOS transistor is the transfer MO.
Connected to a data line via a source / drain path of an S transistor, the drain of the drive MOS transistor is connected to one end of the load element, and the other end of the load element is connected to a first operating potential point, The source of the drive MOS transistor is connected to the second operating potential point, the gate of the drive MOS transistor is connected to the one end of the load element, and the gate of the drive MOS transistor is provided on the semiconductor substrate via an insulating film. Is formed of a first polycrystalline silicon layer, the load element is formed of a second polycrystalline silicon layer above the first polycrystalline silicon layer, and one of the second polycrystalline silicon layers is formed. The end is the above transfer M
The second polycrystalline silicon layer is connected to the source / drain of the OS transistor, and the second end of the second polycrystalline silicon layer is connected to the first operating potential point. The first end of the second polycrystalline silicon layer has a high impurity concentration. And a third polycrystalline silicon layer formed so as to oppose the one end of the second polycrystalline silicon layer via an insulating film. Semiconductor memory device. 2. The second polycrystalline silicon layer has one end portion and the other end portion, and a region sandwiched between the one end portion and the other end portion, and the one end portion. 2. The semiconductor memory device according to claim 1, wherein the portion and the other end portion have a higher impurity concentration than the sandwiched region. 3. The capacitance of the storage node of the memory cell is formed by a capacitive element having at least the third polycrystalline silicon layer and the one end of the second polycrystalline silicon layer as electrodes. 3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a semiconductor memory device. 4. The semiconductor memory device according to claim 1, wherein the third polycrystalline silicon layer is connected to a fixed potential point.