JP3004921B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having static memory cells.

[0002]

2. Description of the Related Art FIG. 31 shows a static random access memory (hereinafter referred to as "static RAM").
FIG. 3 is a block diagram showing an example of the configuration of FIG.

In FIG. 1, a memory cell array 50 is arranged such that a plurality of word lines and a plurality of bit line pairs cross each other, and a memory cell is provided at each intersection of the word line and the bit line pair. ing. The word lines of the memory cell array 50 are connected to an X decoder 51, to which an X address signal is applied via an X address buffer 52. The bit line pair of the memory cell array 50 is connected to the Y decoder 54 via the transfer gate 53,
4 is supplied with a Y address signal via a Y address buffer 55.

One word line of the memory cell array 50 is selected by the X address decoder 51 in response to the X address signal, and one bit line pair of the memory cell array 50 is selected by the Y address decoder 54 in response to the Y address signal. A selected memory cell is provided at the intersection of the selected word line and the selected bit line pair. Data is written to the selected memory cell, or data stored in the memory cell is read.
Whether to write or read data is selected by a read / write control signal R / W applied to read / write control circuit 56.
When writing data, input data Din is input to a selected memory cell via data input buffer 57. At the time of reading data, data stored in the selected memory cell is taken out as output data Dout via sense amplifier 58 and data output buffer 59.

FIG. 32 shows, for example, Japanese Patent Publication No. 62-18997.
FIG. 1 is a circuit diagram of a memory cell portion of a conventional static RAM having a storage capacity of 1M (mega) disclosed in Japanese Unexamined Patent Application Publication No. H10-115,026.

In FIG. 1, a plurality of memory cells 101a to 101n are connected between a pair of bit lines 8a and 8b. Each of the memory cells 101a to 101n includes two enhancement-type inverter MOS field effect transistors (hereinafter, referred to as “MOSFETs”) 4a and 4
b, two high load resistors 104 and 105, and 2
It consists of two access MOSFETs 6a and 6b.

The drains D of the MOSFETs 4a and 4b
Are load resistors 104 and 10 having a high resistance value formed of polysilicon or the like at nodes 14a and 14b, respectively.
5, and the other ends of the resistors 104 and 105 are connected to power terminals 110 and 111, respectively. The sources S of these MOSFETs 4a and 4b
Are connected to the ground potential GND.

Further, the gate G of the MOSFET 4a is connected to the node 14b, and the gate G of the MOSFET 4b is connected to the node 14a. Stored information is node 14
a and the ground potential GND and the parasitic capacitance 113 existing between the node 14b and the ground potential GND as potentials. The node 14a is connected to the bit line 8a via the access MOSFET 6a, and the gate of the MOSFET 6a is connected to the corresponding word lines 7a to 7n. The node 14b is connected to the bit line 8b via the access MOSFET 6b,
The gate of MOSFET 6b is connected to corresponding word line 7a-7
n.

The bit lines 8a and 8b are MOS
Input / output line I / O 11 via FETs 117 and 118
9 and 120, and the gates of MOSFETs 117 and 118 are connected to an input terminal 121 to which a column selection signal is applied by a Y decoder. The bit lines 8a and 8b are connected to connection terminals 124 and 125 to which a power supply potential Vcc is applied, via diode-connected bit line load MOSFETs 122 and 123, respectively. MOSFET 122 and 123
Is for precharging the bit lines 8a and 8b. Power supply terminals 110 and 111 are supplied with power supply potential Vcc.

Next, the operation of the memory cell will be described. When the node 14a of the memory cell 101a is at "L" level and the node 14b is at "H" level,
It is assumed that data stored in memory cell 101a is read. At this time, the potential of the word line 7a changes from 0 V at the time of selection to a potential close to 0 V to the power supply potential Vcc at the time of selection or a potential close to Vcc. As a result, the bit line load MOSFET 1
22, access MOSFET 6a, inverter MO
A current flows toward the ground terminal via the SFET 4a. However, since the inverter MOSFET 4b is off, the bit line load MOSFE is connected from the connection line 125.
No current flows through the path of T123, access MOSFET 6b, inverter MOSFET 4b, and ground terminal. Therefore, the potential of the bit line 8a is
22, the potential is determined by the on-resistance ratio of the MOSFET 6a and the MOSFET 4a, and the potential of the bit line 8b is higher than the power supply potential Vcc.
3 is set to a potential lower by the threshold voltage. As described above, the sense amplifier 58 reads the stored information based on the difference in potential between the bit lines 8a and 8b of the bit line pair.

However, in a 1M (mega) SRAM, the terminal 110 or 111 and the node 14a are connected as described above.
Alternatively, since the memory cell 101a is constituted by the high load resistance 104 or 105 formed of polysilicon or the like formed between the memory cell 101a and the memory cell 14b, the speed and stability of the read operation are insufficient. For example, suppose that held node 14b is at the "H" level and word line 7a is selected. At that time, transistor 6
b is turned on, and a current flows from the power supply terminal 111 to the bit line 8b via the resistor 105. However, a voltage drop occurs due to the high load resistance 105, and the potential of the node 14b does not immediately rise as expected. Therefore, the read operation is not accelerated because the potential of bit line 8b does not rise significantly, and the potential of node 14a and the potential of node 14b holding the "L" level are not significantly different from each other. It also lacks reliability.

[0012] From such a background, 4M (mega) SRA
In M, the high load resistances 104 and 105 are p
It is replaced by a channel type transistor, and the reliability and stability of the read operation are achieved.

FIG. 33 is an equivalent circuit diagram of such a memory cell. In the figure, a memory cell as one logic element unit is composed of six elements, that is, driver transistors 4a and 4b, load transistors 5a and 5b, and access transistors 6a and 6b. Access transistors 6a and 6b are connected to driver transistors 4a and 4b and bit lines 8a and 8b, respectively, and their gates are connected to word line 7. Access transistors 6a and 6b serve to transmit data between bit lines and flip-flops. That is, two inverters each including the driver transistor 4a and the load transistor 5a and the driver transistor 4b and the load transistor 5b are cross-coupled to form a flip-flop and store data. In a 4M SRAM, four transistors 4a, 4b, 6a and 6b are formed on a substrate as a first layer, and a polysilicon thin film transistor (TF) is formed as a second layer thereon.
The cell area is reduced by forming two transistors 5a and 5b using T). That is, a driver transistor and an access transistor are formed on the first layer 1 as NMOS transistors, and a load transistor is formed on the second layer 2 as a PMOS transistor.

FIG. 34 is a perspective view three-dimensionally depicting the transistor arrangement of the conventional SRAM memory cell shown in FIG.

Driver transistors 4a and 4b and access transistors 6a and 6b are formed on the first layer 1, and load transistors 5a and 5b are formed on the second layer 2 by polysilicon TFTs. That is, while there are four transistors on the substrate of the first layer 1, only two transistors are formed in the second polysilicon TFT layer. Therefore, it is calculated that a region corresponding to two transistors is left in the second layer where the polysilicon TFT is formed.

However, actually, a bulk transistor (a transistor having a source and a drain formed on a semiconductor substrate) on a substrate and a polysilicon transistor (TF)
T transistors) have different performances as transistors, and the gate lengths and gate widths of the transistors are changed in order to function sufficiently as a logic element forming a memory cell. As a result, the bulk transistor 4
The area occupied by the individual TFTs and the area occupied by the two polysilicon TFTs are balanced.

[0017]

However, if the grain size of polysilicon is increased by a solid phase growth method, a single crystal is formed by a method such as laser recrystallization, or a bonding technique is used, S comparable to bulk transistors
An OI (silicon on insulator) transistor can be formed in the second layer. When a CMOS type SRAM memory cell is formed by using this technology, the performance of the first-layer bulk transistor and the performance of the second-layer SOI transistor hardly change.
The area occupied by each of the first-layer access transistor of the PMOS type and the second-layer load transistor of the PMOS type can be made almost the same.

FIG. 35 is a perspective view showing an element arrangement corresponding to the equivalent circuit shown in FIG. 33, and FIG. 36 is a cross-sectional view of the configuration of FIG. 35 viewed from the side.

Referring to FIG. 35, driver transistors 4a and 4b and access transistors 6a and 6b are formed on the first layer, and load transistors 5a and 5b are formed on the second layer. As described above, when the second-layer transistor is formed to be comparable to a bulk transistor, each transistor occupies the same area. Therefore, as shown in FIG. 35, the area occupied by the transistors in the first layer 1 is significantly different from the area occupied by the transistors in the second layer 2. FIG. 36 shows a state in which two memory cells of FIG. 35 are arranged in parallel. As is clear from FIG. 36, it is found that a space is wasted in the area of the second layer.

After all, as the technology for forming the second-layer transistor has been further developed, the current memory cell structure has a layout inefficient in terms of the degree of integration.

The present invention does not require a complicated manufacturing process.
And aims at data retention is obtained a semiconductor memory device having high memory cell.

[0022]

SUMMARY OF THE INVENTION A semiconductor memory device according to the present invention is a semiconductor memory device having a flip-flop type memory cell, wherein each of the flip-flop type memory cells has a pair of memory nodes. A pair of driver transistors connected to a ground potential node, a pair of load transistors each connected between each of the memory nodes and a power supply potential node, and each connected to each of the memory nodes 1 pair and access transistors of, saw including a capacitance formed between each and the ground or power supply potential node of the memory node, the capacitor insulating film driver also
Is formed in the same layer as the gate insulating film of the load transistor.
ing. In this semiconductor storage device, a capacitance insulating film is
It can be formed in the same process as the gate insulating film of the transistor.
Requires another process to form a capacitive insulating film.
Absent.

[0023]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts.

[First Embodiment] FIG. 1 is an equivalent circuit diagram showing a structure of a memory cell according to a first embodiment of the present invention.

In the figure, an equivalent circuit of a memory cell 24 formed between a pair of bit lines 8a and 8b and a memory cell 42 formed between a pair of bit lines 8c and 8d adjacent to the bit line pair is shown. It is shown. Since the structure of memory cell 24 is equivalent to the equivalent circuit of the memory cell structure shown in FIG. 33 shown in the conventional example, description thereof will not be repeated. The structure of the memory cell 42 is basically the same as the structure of the memory cell 24, except that the type of the access transistor is a p-channel transistor. That is, access transistors 6a and 6b of memory cell 24 are n-channel transistors, whereas access transistors 6c and 6d of memory cell 42 are p-channel transistors. In this embodiment, the adjacent memory cells 24 and 42 are considered as one set, and an n-channel MOS transistor is formed in the first layer 1 formed on the semiconductor substrate. In the layer 2, a p-channel SOI transistor is formed. FIG.
6 is a perspective view showing an element arrangement corresponding to the equivalent circuit of FIG. 1, and FIG. 6 is a cross-sectional view of the configuration of the element of FIG.

In FIG. 6, a memory cell 24 as one logic element unit surrounded by a broken line is a memory cell having two transistors in the second layer 2 and four transistors in the first layer 1 (the left one in the figure). The memory cell 42 as one logic element unit includes four transistors and a first transistor in a second layer.
This is a memory cell having two transistors in a layer (the right memory cell in the figure, hereinafter referred to as “4/2 type memory cell”).

The first layer 1 is formed using a single crystal substrate or SOI or polysilicon, and the second layer 2 is formed using SOI or polysilicon.

In the 2/4 type memory cell 24, driver transistors 4a and 4b and access transistors 6a and 6b are formed in the first layer 1, and load transistors 5a and 5b are formed in the second layer 2. In the 4/2 type memory cell 42, driver transistors 4c and 4d are formed in the first layer 1, and the access transistor 6c is formed in the second layer 2.
c and 6d and load transistors 5c and 5d are formed.

As shown in FIG. 5, four access transistors 6a and 6b of 2/4 type memory cell 24
Two memory cells are arranged such that access transistors 6c and 6d of / 2 type memory cell 42 are mounted correspondingly. Eventually, in two adjacent memory cells, the number of transistors in the first layer is six, and the number of transistors in the second layer is also six, resulting in an efficient arrangement without wasteful areas. As a result, the total area of the semiconductor device can be reduced.

Further, the present invention is not limited to the above-described SRAM memory cells, and may be applied to a case where the number of transistors included in a plurality of one circuit units arranged in one row or in an array is unbalanced over at least two layers. The present invention is applicable. For example, if the number of transistors in one circuit unit is a in the first layer, b in the second layer, and a and b are not equal, a / b in the first layer and b / b in the second layer As described above, the total area of the circuit can be reduced by alternately combining the a-type circuit units and the a / b-type circuit units in the first layer and b in the second layer.

FIGS. 3 and 4 are circuit diagrams for driving word lines in the memory cell structure of FIG.

When memory cells are two-dimensionally arranged, each of the memory cells is selected using an X address and a Y address. The X address corresponds to each word line. The SRAM memory cell shown in the circuit diagram of FIG. 1 includes a memory cell 24 in which access transistors 6a and 6b are n-channel MOS transistors, and an access transistor 6c.
And 6d are arranged alternately with memory cells 42 formed of p-channel SOI transistors, so that different potentials must be applied to drive the word lines. Therefore, a simple example of the X decoder in the case of the SRAM memory cell array arranged in 256 rows in the X direction is shown in FIGS.

The addresses of the memory cell row having the NMOS type access transistors are (X0, X1, X2, X3,
X4, X5, X6, X7): The binary numbers X0 to X6 = 0 or 1, X7 = 0, and the address of the row of the memory cell having the PMOS access transistor is (X0, X1, X2,
X3, X4, X5, X6, X7): binary numbers X0 to X6 =
Assuming that 1 or 0, X7 = 1, the decoder for selecting the word line in each row may be configured as shown in FIGS. The circuit of FIG. 3 has X0 (/ X0) to X7
The circuit of FIG. 4 includes a NAND circuit of (/ X7) and an inverter, and the NAND circuit of X0 (/ X0) to X7 (/ X7)
It consists only of circuits.

For example, the X address (1100101
0), and consider an n-channel row of access transistors. X0, X1,
By connecting / X2, / X3, X4, / X5, X6, and / X7, the potential of the word line can be set to the “H” level only when (X0 to X7) = (11001010), Turn on access transistors 6a and 6b
can do.

Next, consider an X address (10010011) and a row in which the access transistors are p-channel type. X0, / X1, / X are input to the input of the X decoder of FIG.
2, X3, / X4, / X5, X6, X7,
Only when (X0 to X7) = (10010011), the potential of the word line becomes "L" level, and access transistors 6c and 6d can be turned on.

FIG. 7 is a diagram showing a specific wiring pattern of the equivalent circuit of FIG. Here, the wiring pattern of the memory cell as shown in FIG. 1 is shown, but the total occupied area of the semiconductor memory device can be reduced by combining 2/4 type memory cells and 4/2 type memory cells. Any such memory cell may be used.

In the figure, the left side shows the wiring pattern of the first layer 1 and the right side shows the wiring pattern of the second layer 2. The reference numerals correspond to the numbers in FIG. Storage node 14
Reference numerals a to 14d correspond to the contacts of the first layer 1 and the second layer 2, and the contacts 15a and 15b are the contacts of the first layer 1 and the second layer 2 and the contacts connected to the bit lines.

The shaded regions constitute the gates of the transistors and the word lines 7a and 7b. Capacitors 17a and 17b, each gate of load transistors 5a to 5d, and power supply potential (Vcc) between each gate of driver transistors 4a to 4d and GND line 13.
Capacitors 17c and 17d are formed between the line 17 and the line 12.

In the memory cell of FIG. 7, a transistor having performance comparable to that of a bulk is formed in the second layer, the shape of the driver transistor and that of the load transistor are exactly the same, and the layout is completely different between the first layer and the second layer. This is an example of the same. As is apparent from FIG. 1, the gate 9a of the driver transistor 4b and the load transistor 5
It is possible to share the gate 9c of the driver transistor 4a with the gate 9c of the load transistor 5a and the gate 9d of the load transistor 5a.

FIG. 8 is a sectional view of a structure sharing a gate. In the figure, the channel 21c of the second layer 2 transistor is above the common gate 9, and the common gate 9 is also the gate of the first layer 1 transistor. By sharing the gate 9, the manufacturing process can be simplified accordingly. In this case, the same layout is used for the first layer and the second layer, but the manufacturing process can be simplified even if a layout that shares only a part of the gate is used.

In the memory cell of FIG. 7, in the first layer 1, storage nodes 14a and 14b and GND line 13
Between the storage nodes 14a and 14b and the Vcc line 12 in the second layer 2, the data holding capacity of the memory cell increases, and the soft error Has the effect of becoming stronger. FIG. 9 is an equivalent circuit diagram showing this effect.

FIG. 10 is a perspective view showing a specific structure near the capacitor 17a in FIG. 7, and FIG. 11 is a sectional view taken along the line XI-XI of FIG.

In the figure, an L-type wiring layer 9a is formed so as to cross over the GND line 13. Wiring layer 9
a has one end functioning as a gate electrode of the driver transistor 4a and the other end being contacted as a node 14a. Then, the wiring layer 9a
When crossing the ND line 13, it is found that the capacitance 17a is formed. Thus, the storage node 14a,
Capacitance exists with respect to the GND line 13 via the insulating film 18. Since the charge of the storage node is stored in the capacitor, the data holding ability of the memory cell is improved.

In FIG. 10, as in forming the source 10a and the drain 11a of the transistor 4a,
When impurities are implanted using the gate as a mask, the capacitance 17a
No impurity will be implanted into the portion 13a below. In this memory cell, the portion 13a is connected to the GND line 1
3, the impurity is implanted in advance so that the resistance of this portion is not increased, or only the gate 9a of the driver transistor 4a is first patterned to form the source / drain. At this time, the impurity is simultaneously implanted also into the GND line, and then the gate 13a is connected to the storage node 14a to form the portion 13
It is necessary to reduce the resistance of a. The same can be said for the formation of the capacitance between the gate of the load transistor and the power supply potential line.

12 to 17 are cross-sectional structural views of a manufacturing method corresponding to the memory cell structure of FIG. 7, in which A: a transistor portion, B: a contact portion between the first and second layers,
C: The cross-sectional structure is shown in the order of steps for the contact portion with the aluminum wiring.

First, a field oxide film 71 is formed by LOCOS or the like in order to form an active region on the main surface of the semiconductor substrate 20. Next, the main surface of the semiconductor substrate 20 is thermally oxidized to form a gate oxide film 73 over the entire surface.
5 is formed (see FIG. 12).

Next, polysilicon is formed on the entire surface of the gate oxide film 73 and is patterned into a predetermined shape.
A gate electrode 77 and a wiring layer 79 connected to the gate electrode are formed. At the contact portion C with the aluminum wiring, the polysilicon is entirely removed by etching. (See FIG. 13).

Next, an interlayer insulating film 81 is formed on the entire surface of the gate electrode layer 79 and the exposed gate oxide film 73. This interlayer insulating film 81 is for separating the first layer and the second layer. After the interlayer insulating film is planarized, a contact hole 83 for connecting the first layer and the second layer is formed, while the main surface of the semiconductor substrate 20 is exposed in the aluminum contact portion C. A contact hole 85 is formed (see FIG. 14).

Next, polysilicon is formed on the entire surface of interlayer insulating film 81 and contact holes 83 and 85,
The active region layers 87a and 8 are patterned into a predetermined shape.
7b and 87c are formed. The active region layer is single-crystallized by a solid phase growth method or a laser recrystallization method. Note that information on the crystal orientation of the crystal plane of the substrate can be extracted from the contact portion B and the aluminum contact portion C (see FIG. 15).

Next, a gate insulating film 89 is entirely formed on the active regions 87a to 87c, and an opening 88 is formed only on the active region 87b. Further, the gate insulating film 89
Polysilicon forming a gate electrode is formed on the entire surface, and is patterned into a predetermined shape. As is clear from the figure, the layout of the first layer and the second layer in the region of the transistor portion A and the region of the contact portion B are exactly the same, and the patterns of the active region and the gate polysilicon layer match. (See FIG. 16).

Next, an interlayer insulating film 93 is formed on the entire surface so as to cover the gate electrode layer 91, and an opening 94 is formed in the aluminum contact portion C to make a contact. Next, an aluminum layer is formed on interlayer insulating film 93 including opening 94 and patterned into a predetermined shape to form aluminum wiring 95. That is, the interlayer insulating film 93 functions as an interlayer insulating film for insulating the wiring structure of the second layer from the aluminum wiring layer and the like (see FIG. 17).

The polysilicon gate electrode layer can reduce wiring resistance by using a two-layer structure of a metal work and polysilicon such as tungsten silicide or titanium silicide.

FIG. 2 is an equivalent circuit diagram in which the structure of the adjacent memory cell itself is the same as that of FIG. 1, but the bit lines 8b and 8c are shared in FIG. In this case, the drive circuits for the word lines 7a and 7b may have the structure shown in FIGS. 3 and 4, but in this case, since the bit lines 8b are shared, the word lines must be driven separately. . Such an adjacent memory cell structure also produces the same effect as the memory cell shown in FIG. 1 in terms of occupied area.

[Second Embodiment] FIG. 18 is an equivalent circuit diagram of a memory cell structure according to a second embodiment of the present invention.

In this example, one access transistor 6a included in one memory cell is formed in the first layer 1,
Another access transistor 6 b is formed in the second layer 2. That is, one memory cell has three transistors in the first layer and three transistors in the second layer.
/ 3 type memory cell structure.

FIG. 19 is a diagram showing an element arrangement corresponding to the equivalent circuit of FIG. 18. As is apparent from FIG. 19, a portion of access transistor 6b included in one memory cell and an access between an adjacent memory cell are shown. By arranging the transistor 6c and the transistor 6c so as to overlap with each other, the occupied area can be effectively utilized as a whole. The drive circuits for driving the bit lines 7a and 7b may have the structures shown in FIGS. 3 and 4 described in the first embodiment. In this example, the access transistors included in one memory cell have the same conductivity type. Since they are different, it is necessary to control the word line drive circuit so that the word lines 7a and 7b are simultaneously selected.

FIG. 20 is a diagram showing a specific wiring pattern of the equivalent circuit of FIG. With such an arrangement, the access transistor 6b of the adjacent memory cell can be arranged so as to overlap the access transistor 6c of the other memory cell. The configuration of the other parts is basically the same as that of FIG.

[Third Embodiment] FIG. 21 is an equivalent circuit diagram showing a structure of a memory cell according to a third embodiment of the present invention.

In this example, one of the adjacent memory cells 23 is a 2/3 type memory cell, and the other memory cell 32 is a 3/2 type memory cell. In this embodiment, one access transistor is connected to the bit line 8 for one memory cell. The reason is as follows.

When a transistor having performance comparable to that of a bulk is formed in the second layer, the potential of the storage node is more stable than that of a conventional SRAM using a polysilicon TFT. Therefore, it is possible to directly extract the potential of one storage node to the bit line and read the potential change without extracting the potential difference between the storage nodes on both sides to the bit line pair and reading the potential difference as in the related art. This is because the information stored in the memory cell can also be known.

FIG. 23 is a perspective view showing an element arrangement corresponding to the equivalent circuit of FIG. As is apparent from the drawing, adjacent memory cells are alternately arranged such that access transistor 6a of one adjacent memory cell is arranged to overlap above access transistor 6c of the other adjacent memory cell. Thus, the area occupied by the memory cells can be reduced.

FIG. 22 is a diagram showing a specific configuration of the sense amplifier circuit connected to bit line 8 in FIG.

This circuit is a so-called NMOS cross-coupled circuit, and has a structure often used for a sense amplifier of a dynamic random access memory (DRAM). In the DRAM, since one bit line is connected to one memory cell, the bit line is connected to the terminal Vin in FIG. 22, and the terminal / Vin is connected to the bit line of another memory cell. This is a memory cell that is not accessed at the same time.

Similarly, in the case of the SRAM memory cell of FIG. 21, the bit line 8 is connected to the terminal Vin, and the terminal / Vin
May be directly connected to the bit lines or the power supply potential Vcc of the memory cells which are not simultaneously accessed. As a result, FIG.
1 can read the information of each of the memory cells shown in FIG.

[Fourth Embodiment] FIG. 24 is an equivalent circuit diagram showing a memory cell structure according to a fourth embodiment of the present invention.

In the third embodiment, one memory cell has one access transistor. In this embodiment, one memory cell has one transfer gate. Things.
That is, the transfer gate 16 is formed by combining an NMOS access transistor 16a and a PMOS access transistor 16b. By means of transfer gate 16, a flip-flop formed of driver transistors 4 a and 4 b and load transistors 5 a and 5 b and bit line 8
Is connected to In this embodiment, the first layer 1
Are formed with driver transistors 4a and 4b and an access transistor 16a of the transfer gate 16, and in the second layer 2, load transistors 5a and 5b and an access transistor 16b of the transfer gate 16 are formed.

FIG. 25 is a perspective view showing an element arrangement corresponding to the equivalent circuit of FIG. As is apparent from the figure, in the memory cell of this embodiment, three, two,
Since three transistors are formed in the layer, there is no useless area for forming a memory cell, and the area occupied by the memory cell can be reduced.

This memory cell structure has features and advantages not found in the memory cell of the third embodiment. In the memory cell of FIG. 21, since the access transistor is formed only of the NMOS type or the PMOS type, when accessing the storage node from the bit line and inverting the data at the time of writing data, the access transistor is not connected. There is a difference between the bit line potential and the storage node potential by the threshold value. Therefore, there is a problem that the writing operation of the memory cell becomes unstable by the potential difference.

In order to explain this problem, in FIG. 21, for example, when storage node 14b already holds "H" level information, word line 7a and bit line 8 are set to "L" level and stored. It is assumed that "L" level information is to be written to node 14b. First, access transistor 6a is turned on, so that a current flows from storage node 14b at the “H” level to bit line 8 and the potential of storage node 14b drops, but the potential of storage node 14b reaches the threshold value of access transistor 6a. When the potential drops, the access transistor turns off. As a result, since the potential of the storage node 14b does not become sufficiently low, the information holding operation of the memory cell becomes unstable.

On the other hand, in the structure of the memory cell shown in FIG. 24, the transfer gate 16 is used instead of the access transistor.
Either the transistor 16a of the PMOS type or the transistor 16b of the PMOS type is ON, so that the read operation of the memory cell becomes unstable due to the threshold value of the transistor as in the third embodiment. It will not be.
Further, since the threshold voltage of the access transistor is not affected, "H" level information or "L" level information can be written without lowering the potential in accordance with the potential of the bit line. In addition, the reliability of the writing operation is improved.

[Fifth Embodiment] FIG. 26 is an equivalent circuit diagram showing a memory cell structure according to a fifth embodiment of the present invention.

Each of the logic elements constituting the memory cell is
The number and type thereof are the same as the logic elements of the memory cell of FIG. 33 shown in the conventional example. However, in this embodiment, the memory cell structure is formed as a three-layer structure. That is, driver transistors 4 a and 4 b are formed on the first layer 1, and load transistors 5 a are formed on the second layer 2.
a and 5b are formed, and access transistors 6a and 6b are formed in the third layer 3.

FIG. 28 is a perspective view showing the arrangement of elements corresponding to the equivalent circuit of FIG. 26. FIG. 29 shows the configuration of FIG.
It is sectional drawing seen from the side.

As is clear from these figures, the memory cell of this embodiment has a three-layer SRAM memory cell (hereinafter, 2/2) having two transistors for each layer.
/ 2 type memory cell).

FIG. 27 is a diagram showing a specific example of a wiring pattern of the SRAM having the three-layer structure. In this example, the access transistors 6a and 6b are formed in the third layer because the bit lines 8a and 8b and the word line 7 need to be connected to these transistors. This is because the contact from above becomes shallower and the margin in the manufacturing process becomes larger. However, access transistors 6a and 6b
Even if a layout in which the first and second layers are used is adopted, the number of transistors formed in each layer does not change, so that the effect of reducing the occupied area of the memory cell as a whole can be obtained.

In each of the above embodiments, an example is shown in which the driver transistor is the first layer and the load transistor is the second layer. However, the functions of the driver transistor and the load transistor function only when they complement each other. Therefore, either of them may be called a driver transistor or a load transistor. Therefore, the same effect as in the above embodiment can be obtained even in a memory cell in which a load transistor is formed in the first layer and a driver transistor is formed in the second layer.

In the above example, an SRAM memory cell has been described as an example. However, the idea of the present invention can be applied to a memory cell of another storage device or a semiconductor device forming a logic element.

[Sixth Embodiment] FIG. 30 is a perspective view showing an example in which the idea of the present invention is applied to an optical sensor according to a sixth embodiment of the present invention.

In the figure, the CCD 15 is provided in the first layer (lower layer).
1 and an access transistor 161 are formed. An element unit in which a photodetector 157 connected to the access transistor 161 via a contact 159 is formed in the second layer (upper layer), and only the CCD 153 is formed in the first layer. The light detector 163 and the access transistor 16
5 are formed, and an element unit in which the first layer and the second layer are connected by the contact 167 is formed. By alternately arranging each of such element units, the area occupied by the detector can be increased.

[0080]

According to the present invention, the insulating film of the capacitor is not
Formed of the same layer as the transistor gate insulating film.
Therefore, a complicated manufacturing process is not required. Moreover, the capacity is
The edge film can be formed as thin as the gate insulating film.
Therefore, the memory cell is resistant to soft errors.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram showing a structure of a memory cell according to a first embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram showing a modification of the memory cell structure of FIG.

FIG. 3 is a circuit diagram showing an example of a word line driving circuit for the memory cell structure of FIG. 1;

FIG. 4 is a circuit diagram showing another example of a word line driving circuit for the memory cell structure of FIG. 1;

FIG. 5 is a perspective view showing an element arrangement corresponding to the equivalent circuit diagram of the memory cell of FIG. 1;

6 is a cross-sectional view of the configuration of the memory cell of FIG. 5 as viewed from the side.

FIG. 7 is a diagram showing a specific wiring pattern of the memory cell structure of FIG. 1;

8 is a cross-sectional view showing a configuration of a gate electrode of a driver transistor and a load transistor of the memory cell structure of FIG.

FIG. 9 is a circuit diagram equivalently showing formed capacitance in the memory cell structure of FIG. 1;

FIG. 10 is a perspective view of a specific wiring structure showing a state of forming the capacitor of FIG. 9;

11 is a diagram showing a cross-sectional structure taken along line XI-XI in FIG.

FIG. 12 is a cross-sectional view showing a first step in the manufacturing steps of the memory cell structure in FIG. 1;

13 is a cross-sectional view showing a second step in the process of manufacturing the memory cell structure in FIG.

FIG. 14 is a cross-sectional view showing a third step in the process of manufacturing the memory cell structure of FIG. 1;

15 is a cross-sectional view showing a fourth step in the process of manufacturing the memory cell structure in FIG.

16 is a cross-sectional view showing a fifth step in the process of manufacturing the memory cell structure in FIG.

17 is a cross-sectional view showing a sixth step in the process of manufacturing the memory cell structure in FIG. 1. FIG.

FIG. 18 is an equivalent circuit diagram showing a structure of a memory cell according to a second embodiment of the present invention.

FIG. 19 is a perspective view showing an element arrangement corresponding to the equivalent circuit of FIG. 18;

20 is a diagram showing a specific wiring pattern of the memory cell structure of FIG. 18;

FIG. 21 is an equivalent circuit diagram showing a structure of a memory cell according to a third embodiment of the present invention.

22 is a circuit diagram showing a specific structure of a sense amplifier connected to a bit line in the memory cell structure of FIG.

FIG. 23 is a perspective view showing an element arrangement corresponding to the equivalent circuit of FIG. 18;

FIG. 24 is an equivalent circuit diagram showing a structure of a memory cell according to a fourth embodiment of the present invention.

FIG. 25 is a perspective view showing an element arrangement corresponding to the equivalent circuit of FIG. 24;

FIG. 26 is an equivalent circuit diagram showing a structure of a memory cell according to a fifth embodiment of the present invention.

FIG. 27 is a diagram showing a specific wiring pattern of the memory cell structure of FIG. 26;

FIG. 28 is a perspective view showing an element arrangement corresponding to the equivalent circuit of FIG. 26;

29 is a cross-sectional view of the configuration of the memory cell of FIG. 28 as viewed from the side.

FIG. 30 is a perspective view showing a structure of an optical detector according to a sixth embodiment of the present invention.

FIG. 31 is a block diagram showing a system configuration of a conventional SRAM.

FIG. 32 is a circuit diagram showing a specific configuration of the memory cell array of FIG. 31.

FIG. 33 is an equivalent circuit diagram showing a specific memory cell structure obtained by improving the memory cell of FIG. 32;

FIG. 34 is a perspective view showing a structure in which the memory cell structure of FIG. 33 is specifically shown on a semiconductor substrate.

FIG. 35 is a perspective view showing an element arrangement corresponding to the equivalent circuit of FIG. 33;

36 is a cross-sectional view of the configuration of the memory cell of FIG. 35 as viewed from the side.

[Explanation of symbols]

1 1st layer, 2nd layer, 4a-4d driver transistor, 5a-5d load transistor, 6a-6d access transistor, 7a, 7b word line, 8a-8
d bit line, 12 power supply potential line, 13 ground potential line, 14a to 14d storage node, 242/4 type memory cell, 424/2 type memory cell, 9 gate electrode, 16 transfer gate.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/8244 H01L 27/11

Claims (1)

(57) [Claims] 1. A semiconductor memory device having a flip-flop type memory cell, wherein each of the flip-flop type memory cells is connected between a pair of memory nodes and a ground potential node. A pair of load transistors each connected between each of the memory nodes and a power supply potential node; a pair of access transistors each connected to each of the memory nodes; look including a capacitance formed between each said ground or power supply potential node of the node, the insulating film of the capacitor is the driver or load transistor
A semiconductor memory device formed of the same layer as the gate insulating film of the semiconductor device.