JPH07115141A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To enable an FRAM of 1-MOS multi-capacitor type to be lessened in cost and stabilized in operating characteristics. CONSTITUTION:In an FRAM of 1-MOS multi-capacitor type, part or all of a certain number of ferroelectric capacitors whose lower electrodes are connected together in common are so formed to overlap the upper layer of corresponding selection MOSFETs QN0 and QN1, the ferroelectric capacitors and sub-data lines d000 and d100 serving as the lower electrodes of the capacitors connected together in common are formed above a metal wiring layer of data line or the like after a wiring is formed an processed. By this setup, selection MOSFETs and a prescribed number of corresponding ferroelectric capacitors are three-dimensionally formed, a memory array can be enhanced in layout efficiency, and a thermal treatment carried out in a wiring forming process can be restrained from affecting a ferroelectric capacitor in holding characteristics.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, for example, a 1MOS / multicapacitor type Ferroelectric RA.
The present invention relates to a technology that is particularly effective when used for an M (Random Access Memory).

[0002]

2. Description of the Related Art Ferroelectric RAM using a ferroelectric capacitor as a non-volatile memory element
(Hereinafter, abbreviated as FRAM). In addition, one selection MOSFET (Metal Oxide Semiconductor)
onductor Field Effect Tran
Sistor: Metal oxide semiconductor type field effect transistor. In this specification, there is a so-called 1-MOS / multi-capacitor type FRAM in which a plurality of ferroelectric capacitors are provided corresponding to an insulated gate field effect transistor (MOSFET). . Furthermore, in such a 1MOS / multicapacitor type,
A method has been proposed in which the stress on the ferroelectric capacitor in the non-selected state is reduced by setting the non-selected level of the plate line and the data line to half the write voltage.

A 1-MOS / multi-capacitor type FRAM is described in, for example, Japanese Patent Laid-Open No. 4-90189. Further, Japanese Patent Application No. 4-252326 describes a 1MOS / multicapacitor type stress reduction measure.

[0004]

In the conventional 1MOS / multicapacitor type in which the above-mentioned stress reduction measures are taken, for example, the plate lines P00 to P03 are used as the upper electrodes.
The lower electrodes of the individual ferroelectric capacitors are integrally formed as a sub data line d000 and are commonly coupled, as illustrated in FIG. The sub-data line d000 is coupled to the N-type diffusion layer ND1 serving as the source S of the corresponding selection MOSFET QN0 on one side and to the P-type diffusion layer PD1 serving as the source S of the corresponding stress prevention MOSFET QP0 on the other side. . In other words, in the conventional 1MOS / multi-capacitor type with stress reduction measures, a predetermined number of ferroelectric capacitors whose lower electrodes are commonly coupled should overlap the corresponding selection MOSFET QN0 and stress prevention MOSFET QP0. In other words, the lower electrodes of a predetermined number of ferroelectric capacitors integrated as sub-data lines are formed on a flat surface instead of the corresponding selection MOS.
It is formed by bending so as to be coupled to the diffusion layers of the FET and the stress prevention MOSFET. As a result, the layout efficiency of the memory array portion is reduced, the chip area is increased, and F
While the cost reduction of the RAM is restricted, the ferroelectric capacitor is deformed especially in the portions near both ends of the sub data line and the holding characteristic thereof is changed, and the operation characteristic of the FRAM becomes unstable.

On the other hand, in the conventional FRAM, a metal wiring layer serving as a data line and a word line is formed in the upper layer of the ferroelectric capacitor, that is, after the ferroelectric capacitor and the corresponding sub data line are formed. Therefore, the ferroelectric capacitor formed previously has a result that its holding characteristic is affected by the heat treatment in the wiring forming process, which makes the operating characteristic of the FRAM more unstable.

An object of the present invention is to promote cost reduction of a 1-MOS / multi-capacitor type FRAM, and to stabilize its operating characteristics.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, 1MO in which a predetermined number of ferroelectric capacitors are provided corresponding to one selection MOSFET
In an S / multi-capacitor type FRAM or the like, a part or all of a predetermined number of ferroelectric capacitors, the lower electrodes of which are commonly coupled, are formed so as to overlap the upper layer of the corresponding selection MOSFET, and a predetermined number of ferroelectric capacitors are formed. After the wiring forming process, the ferroelectric capacitor and the sub-data line, which will be the commonly coupled lower electrode thereof, are formed in the upper layer of the metal wiring layer.

[0009]

According to the above means, a predetermined number of ferroelectric capacitors corresponding to the selection MOSFETs are three-dimensionally formed to improve the layout efficiency of the memory array section and reduce the chip area of the FRAM or the like. In addition, the upper surface of the sub-data line, which serves as the commonly coupled lower electrode of a predetermined number of ferroelectric capacitors, can be flattened to prevent deformation of the ferroelectric capacitors at both ends thereof, and heat treatment in the wiring formation process can be performed. It is possible to eliminate the influence on the holding characteristics of the ferroelectric capacitor. As a result, especially 1
It is possible to promote cost reduction of a MOS / multi-capacitor type FRAM or the like and stabilize its operation characteristics.

[0010]

1 is a block diagram showing an embodiment of an FRAM to which the present invention is applied. Further, FIG. 2 shows a partial circuit diagram of a first embodiment of the memory array MARY included in the FRAM of FIG. Based on these figures, first, an outline of the configuration and operation of the FRAM and its memory array of this embodiment will be described. Although not particularly limited, the FRAM of this embodiment is built in a single-chip microcomputer and used as a read-only memory for storing a control program, fixed data, and the like. The circuit elements of FIG. 2 and the circuit elements of each block of FIG. 1 are formed on a single semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique. In the circuit diagram below, MOSF with an arrow on its channel (back gate) part
The ET is a P-channel type and is shown separately from an N-channel MOSFET without an arrow.

In FIG. 1, the FRAM of this embodiment is
Memory array M occupying most of the semiconductor substrate surface
Let ARY be its basic component. This memory array has 8 × (p + 1) memory blocks MB00 to MB.
07 to MBp0 to MBp7, each of these memory blocks being the memory block MB00 of FIG.
And MB10, representatively, 4 × (n + 1) storage elements arranged in a grid, that is, ferroelectric capacitors C00 to C03 and C10 to C13, and n.
+1 selection MOSFETs QN0 and QN1 and the like are included. One of the electrodes of the four ferroelectric capacitors arranged in the same column of each memory block has corresponding sub data lines d000 to d00n to d070 to d07n to d.
Via p00 to dp0n to dp70 to dp7n, they are commonly coupled to the sources of the corresponding selection MOSFETs QN0 and QN1. The other electrodes of the n + 1 ferroelectric capacitors arranged in the same row of each memory block are commonly coupled to the corresponding plate lines P00 to P03 to Pp0 to Pp3. Further, the drains of the selection MOSFETs QN0 and QN1 of each memory block are commonly coupled to the corresponding data lines D00 to D0n to D70 to D7n, respectively, and the gates thereof are commonly coupled to the corresponding word lines W0 to Wp, respectively.

The word lines W0 to Wp forming the memory array MARY have an X address decoder X on the left side thereof.
It is connected to D and is selectively put in the selected state. Further, the plate lines P00 to P03 to Pp0 to Pp3 are coupled to the plate driver PD on the right side thereof and selectively set to a predetermined selection or non-selection level. To the X address decoder XD, the internal address signals x0 to xi of i + 1 bits are supplied from the X address buffer XB, and the internal voltage VW is supplied from the internal voltage generation circuit VG. Further, the plate driver PD is supplied with the internal address signals x0 to xi from the X address buffer XB and the internal voltages VP, VO and HVO from the internal voltage generating circuit VG. The X address buffer XB has an address input terminal A
X address signals AX0 to AXi are supplied via X0 to AXi, and power supply voltage VCC is supplied to internal voltage generating circuit VG via power supply voltage input terminal VCC.

The internal voltage generating circuit VG has a power supply voltage VCC.
Is boosted to form predetermined internal voltages VP, VW and VO, and at the same time, an internal voltage HVO which is an intermediate potential between the internal voltage VO and the ground potential VSS is formed. Of these, the internal voltage VO is supplied to the plate driver PD and the read / write circuit RW as a so-called write voltage for the ferroelectric capacitor, and the internal voltage HVO is also supplied to the plate driver PD and the read / write circuit RW. Further, the internal voltage VW is set to a potential higher than the internal voltage VO by at least the threshold voltage of the selected MOSFET, and is supplied to the X address decoder XD as the selection level of the word lines W0 to Wp. Then, the internal voltage VP is set to a potential higher than the internal voltage VW and is supplied to the plate driver PD as a refresh voltage of the ferroelectric capacitor.

The X address buffer XB fetches and holds the X address signals AX0 to AXi input via the address input terminals AX0 to AXi, and holds the internal address signals x0 to xi based on these X address signals.
Are formed and supplied to the X address decoder XD and the plate driver PD.

On the other hand, the X address decoder XD is the FRA.
According to the operation mode of M, the internal address signals x0 to xi supplied from the X address buffer XB are selectively decoded, and the word lines W0 to Wp are selectively set to the selection level like the internal voltage VW. Also, the plate driver PD
Is an internal address signal x depending on the operation mode of the FRAM.
0 to xi are selectively decoded, and plate lines P00 to P00
P03 to Pp0 to Pp3 are selectively set to a predetermined selection level or non-selection level.

Next, the data lines D00 to D0n to D70 to D7n forming the memory array MARY are coupled to the Y switch YS under the data lines, and eight common data lines B0 to B7 are provided via the Y switch YS. Connected selectively.

The Y switch YS is provided with data lines D00 to D0.
8 × (n provided corresponding to n to D70 to D7n
+1) switch MOSFETs are included. The drains of these switch MOSFETs have corresponding data lines D0
0 to D0n to D70 to D7n, respectively,
The sources are n + 1 corresponding common data lines B0.
To B7 are sequentially connected in common. Also, switch MOSF
The gates of ET are sequentially connected in common every eight (n + 1) gates, and the corresponding data line selection signals Y0 to Yn are commonly supplied from the Y address decoder YD.

A switch MOS forming the Y switch YS
The FETs are selectively turned on by eight each in response to the high level of the corresponding data line selection signals Y0 to Yn, and the corresponding eight of the data lines D00 to D0n to D70 to D7n and the common data lines B0 to B7. And are selectively connected.

The Y address decoder YD has a j + 1-bit internal address signal y0 from the Y address buffer YB.
~ Yj are provided. The Y address buffer YB is supplied with Y address signals AY0 to AYj via address input terminals AY0 to AYj.

The Y address buffer YB fetches and holds the Y address signals AY0 to AYj supplied through the address input terminals AY0 to AYj, and at the same time, based on these Y address signals, the internal address signals y0 to yj.
Are formed and supplied to the Y address decoder YD. The Y address decoder YD is a Y address buffer Y.
The internal address signals y0 to yj supplied from B are decoded and the corresponding data line selection signals Y0 to Yn are alternatively set to the high level.

Data lines D00 to D0 of the memory array MARY
Common data lines B0 to B7 to which eight designated D0n to D70 to D7n are selectively connected are coupled to the read / write circuit RW below the common data lines B0 to B7.

The read / write circuit RW has a common data line B.
Eight unit read / write circuits provided corresponding to 0 to B7 are provided, and each of these unit read / write circuits includes a sense amplifier, a write amplifier, an input latch and an output latch. Of these, the input terminal of the sense amplifier is
It is coupled to the corresponding common data lines B0-B7, and its output terminal is coupled to the input terminal of the corresponding output latch.
The output terminal of the output latch is the corresponding read data line RD.
Via 0 to RD7, they are coupled to the input terminals of the corresponding unit circuits of data output buffer OB, and the output terminals of these unit circuits are coupled to the corresponding data input / output terminals IO0 to IO7. On the other hand, the input terminal of each unit circuit of the data input buffer IB has corresponding data input / output terminals IO0-I0.
It is coupled to O7 and its output terminal is the write data line WD
It is coupled via 0 to WD7 to the input terminal of the corresponding input latch of the read / write circuit RW. The output terminals of these input latches are coupled to the input terminals of the corresponding write amplifiers, and the output terminals of each write amplifier are coupled to the corresponding common data lines B0 to B7.

The sense amplifier constituting each unit read / write circuit of the read / write circuit RW has the corresponding data line and common data line B0 from the selected ferroelectric capacitors of the memory array MARY when the FRAM is in the read mode. The read signal output as a current signal through B7 is changed to a voltage signal and amplified. These read signals are transmitted to the corresponding input latches, then transmitted to the corresponding unit circuits of the data output buffer OB via the read data lines RD0 to RD7, and further to the corresponding data input / output terminals IO0 to IO7. Sent to the outside.

On the other hand, the input latches constituting each unit read / write circuit of the read / write circuit RW have data input / output terminals IO0-I0 when the FRAM is in the write mode.
The write data input from O7 via the data input buffer IB and the write data lines WD0 to WD7 is fetched, held, and transmitted to the corresponding write amplifier. The write data is converted into a predetermined write signal by the corresponding write amplifier, and is written to the selected ferroelectric capacitor from the common data lines B0 to B7 via the corresponding data line of the memory array MARY.

In this embodiment, the read / write circuit R
Data feedback signal lines are respectively provided between the output latches and the corresponding input latches constituting each unit read / write circuit of W. As is well known, in the FRAM, the stored data is read by so-called destructive read. Therefore, in the FRAM of this embodiment, the storage data read from the selected ferroelectric capacitor to the output latch via the corresponding sense amplifier is transferred to the corresponding input latch via these data feedback signal lines. Transmitted,
Rewriting is performed on the selected ferroelectric capacitor.

The timing control circuit TC includes an FRAM enable signal FRE and a read / write signal R / which are supplied as start-up control signals from the preceding circuit of the microcomputer.
Based on W and the refresh start signal RF, various internal control signals for timing control are selectively formed, and FR
Supply to each part of AM.

FIG. 3 shows a partial plan layout view of an embodiment of the memory array MARY of FIG. 2, and FIG. 4 shows an AB sectional structure view of the embodiment. . Based on these drawings, the arrangement and element structure of the memory array of the FRAM of this embodiment and its features will be described.
Note that FIG. 3 exemplarily shows the data lines D00 to D03, the plate lines P00 to P03 and P10 to P11, and a total of 24 ferroelectric capacitors arranged at the intersections thereof and their related portions. Hereinafter, a specific description will be given by taking the parts shown in FIGS. 3 and 4 as examples.

In FIG. 3, plate lines P00 to P03 and P10 to P1 forming the memory array MARY.
1 are arranged in parallel with each other in the horizontal direction of the figure at a predetermined interval, and corresponding word lines W0 and W1 are arranged in parallel below the plate lines P03 and P10. Further, the data lines D00 to D03 are arranged in parallel with each other at a predetermined interval in the vertical direction of the drawing, and the corresponding sub data lines d000 to d0 are provided below the data lines.
03 and d100 to d103 are arranged in parallel. Plate lines P00-P03 and P10
P11 and sub data lines d000 to d003 and d1
At the intersection with 00 to d103, as indicated by the diagonal line,
Ferroelectric capacitor C00 having the corresponding plate line as its upper electrode and the corresponding sub-data line as its lower electrode
To C03 and C10 to C11 are formed. Further, in the lower layer of the data lines D00 to D03, as shown by the dotted line, the corresponding selection MOSFETs QN0 and QN1 are provided.
N-type diffusion layers ND that serve as sources and drains of the same are formed, respectively.

Here, as shown in FIG. 4, the N-type diffusion layer ND has the P-type low-concentration semiconductor region P on the P-type semiconductor substrate PSUB surface with the word lines W0 and W1 as part of its photomask. ^- is formed in substantially three diffusion layer ND
1 to ND3. Of these, select MOSFET
Diffusion layer ND2 serving as common drain D of QN0 and QN1
Is coupled to a data line D00 formed of a metal wiring layer such as aluminum via a buried conductive layer BC1. Further, the diffusion layer ND1 serving as the source S of the selection MOSFET QN0 is
Corresponding sub-data line d00 via the buried conductive layer BC2
The diffusion layer ND3 which is coupled to 0 and serves as the source S of the selection MOSFET QN1 is coupled to the corresponding sub data line d100 via the buried conductive layer BC3. A field insulating film FI is formed outside the diffusion layers ND1 and ND2,
A P-type high-concentration semiconductor region P ⁺ that serves as a channel stopper CHS is formed in the lower layer. The buried conductive layer B
C1 to BC3 are formed by selectively embedding a metal conductor such as tungsten using a so-called selective embedding technique.

Plate lines P00 to P03 and P10 and P11 also made of platinum Pt are formed orthogonally on the upper layers of the sub data lines d000 and d100 made of platinum Pt. A ferroelectric SE such as BaMgF ₄ is deposited at the intersection. As a result, the plate lines P00 to P03 and P10 to P11 are connected to the ferroelectric capacitors C00 to C11.
It becomes the upper electrodes of C03 and C10 to C11, and the sub data lines d000 and d100 become the lower electrodes of these ferroelectric capacitors. An insulating film IL made of silicon oxide (SiO ₂ ) is formed between the data lines D00 and the like and the sub data lines d000 and d100 and the lower layers of these sub data lines.

That is, in the FRAM of this embodiment, as shown in FIG.
As is clear from the above, the ferroelectric capacitors C00 to C03 and C10 to C constituting the memory array MARY
11 and the like are corresponding selection MOSFETs QN0 and QN1
And the like, and the layout efficiency of the memory array MARY is improved. As a result, the chip area of the 1-MOS / multi-capacitor type FRAM can be correspondingly reduced, and the cost reduction can be promoted.

On the other hand, in this embodiment, the sub data lines d000 and d100, etc., which are the lower electrodes of the ferroelectric capacitors C00 to C03 and C10 to C11, are formed so as to be entirely horizontal to the semiconductor substrate surface. . Further, the upper surface thereof, including the upper surfaces of the buried conductive layers BC1 to BC3, is a so-called CMP (Chemical Mechanic).
It is polished by a mechanical polishing method to increase its levelness. As a result, in the FRAM of this embodiment, all the ferroelectric capacitors arranged on each sub-data line are formed under the same condition, which is especially formed at both ends of the sub-data line. Prevents deformation of the ferroelectric capacitor,
The operating characteristics of M can be stabilized.

FIG. 5 is a partial circuit diagram of a second embodiment of the memory array MARY included in the FRAM of FIG. Further, FIG. 6 shows the memory array MA of FIG.
A partial plan view of one embodiment of RY is shown, and FIG. 7 shows a CD sectional structure view of that embodiment.
It should be noted that this embodiment basically follows the embodiments of FIGS. 2 to 4, and therefore only the portions different from this will be described. Further, in FIG. 5, sub-data lines d000, d070, d100 and d17 forming the memory blocks MB00, MB07, MB10 and MB17.
0 and its related parts are shown as an example. In FIG. 6, data lines D00 to D03, plate lines P00 to P03 and P1 are shown.
0 and a total of 20 ferroelectric capacitors arranged at the intersections and related parts thereof are shown by way of example.
In the following description, a specific description will be given by taking the parts shown in these figures as examples.

In FIG. 5, the memory array MARY of this embodiment has all the sub data lines d constituting the memory blocks MB00 to MB07 to MBp0 to MBp7.
000, d070, d100, d170, etc. and a predetermined potential supply point, that is, the ground potential of the circuit, respectively, P-channel type stress prevention MOSFET QP
0 and QP1 and the like. MOS for these stress prevention
The gates of the FETs are commonly coupled to the corresponding word lines W0 and W1, etc., respectively. As a result, the stress prevention MOSFETs QP0 and QP1 etc. are selectively turned on when the corresponding word lines W0, W1 etc. are set to a non-selection level such as the ground potential of the circuit, and the corresponding sub-data lines d000 and d100. And the ground potential of the circuit are selectively connected. As a result, the sub data line d
000, d100, etc. are not brought into a floating state when they are not selected, and plate lines P00-P
03 and P10 to P13 and the like have the same potential as the non-selected level, so that the stress on the non-selected ferroelectric capacitors can be prevented.

By the way, stress preventing MOSFET Q
As shown in FIG. 6, P0 and QP1 and the like are formed with the P-type diffusion layer PD formed under the data lines D00 to D03 and the like as their drains and sources. As illustrated in FIG. 7, these diffusion layers PD are formed by using one of the two branched word lines W0 and the like as a part of a photomask, and are divided into two diffusion layers PD1 and PD2. Of these, the diffusion layer P serving as the source S of the MOSFET QP1 and the like.
D1 is connected to the corresponding sub data line d000 or the like via the buried conductive layer BC4 and becomes the drain D, the diffusion layer PD.
2 is a ground potential supply wiring SV via the buried conductive layer BC5
It is connected to SS. On the upper layers of the diffusion layers PD1 and PD2, corresponding sub-data lines d000 and plate lines P00 and P01, that is, a part of a plurality of corresponding ferroelectric capacitors are overlapped and formed. As a result, in the FRAM of this embodiment, the stress prevention MOS is
Despite the addition of FETs QP0 and QP1,
It is possible to minimize the increase in the chip area accompanying this and to promote cost reduction.

FIG. 8 shows a partial circuit diagram of a third embodiment of the memory array MARY included in the FRAM of FIG. Further, FIG. 9 shows the memory array MA of FIG.
A partial plan view of one embodiment of RY is shown in FIG.
11 and 12, the EF of the embodiment is shown.
The cross-sectional structural diagram, the GH cross-sectional structural diagram, and the I-J cross-sectional structural diagram are shown, respectively. It should be noted that this embodiment basically follows the embodiments of FIGS. 2 to 4, and therefore only the portions different from this will be described. Further, in FIG. 8, memory blocks MB00, MB07, M
Sub data lines d000 and d001, d070 and d071, d100 and d1 forming B10 and MB17
01 and d170 and d171 and their related parts are shown by way of example, and in FIG. 9, a total of 24 ferroelectrics arranged at the data lines D00 to D03, the plate lines P00 to P03 and P10 to P11 and their intersections. Although a capacitor and its related portion are shown as examples, in the following description, a specific description will be given taking the portion shown in these figures as an example.

In FIG. 8, all the memory blocks MB00, which form the memory array MARY of this embodiment.
MB07, MB10, MB17, etc. are connected to the data line D00.
And 2 × (n +) provided in correspondence with D70 and the like.
1) One sub data line d000 and d001, d070
And d071, d100 and d101 and d170
And d171 and the like, respectively. Of these, one of the sub-data lines d000, d070, d100 and d forming a pair
170 or the like is coupled to the corresponding data line D00 or the like via the depletion type selection MOSFET QD1 or QD3 and the enhancement type selection MOSFET QN1 or QN3 which are formed in series, and the other sub data line d0.
01, d071, d101, d171 and the like are enhancement-type selection MOSFETs that are serially arranged in reverse order.
Depletion type selection MOSFET with QN2 or QN4
Corresponding data line D00 via TQD2 or QD4
And so on. The gates of the pair of selection MOSFETs QN1 and QD2 and QN3 and QD4 are commonly coupled to the corresponding word line W0U or W1U, respectively.
The gates of the selection MOSFETs QD1 and QN2 and QD3 and QN4 have corresponding word lines W0L or W1L.
Etc. are commonly connected to each other.

From these facts, one of the sub-data lines d000, d070, d100, d170, etc. forming a pair has the corresponding word line W0U or W1U at the high level and the word line W0L or W1L at the low level. Is selectively connected to the corresponding data lines D00 and D07, and the other sub-data lines d001 and d0 are connected.
71, d101, d171, etc. are corresponding word lines W
0U or W1U is set to low level and word line W0L
Alternatively, when W1L is set to the high level, the corresponding data lines D00 and D07 are selectively connected.

Here, the data lines D00 and D01, etc. are
As illustrated in FIG. 9, a corresponding pair of sub-data lines d000 and d001 and d100 and d101 or d002 and d003 and d102 and d1.
It is arranged in parallel with the middle of 03. In the lower layers of the sub-data lines d000 to d003, d100 to d103, etc., as shown by the dotted lines in the figure, an H-shaped N that serves as the drain and source of the corresponding two pairs of selection MOSFETs.
The type diffusion layer ND is formed, and the corresponding word lines W0L and W0U and W1U and W1 are formed below the orthogonal plate lines P02 and P03 and P10 and P11.
L and the like are formed respectively.

In this embodiment, as shown in FIGS. 10 to 12, the data lines D00, etc. are made of metal wiring layers such as aluminum, so that the selection MOSFETs QD1, QN are selected.
1, a word line W0 serving as a gate for QN3, QD3, etc.
L, W0U, W1U, W1L, etc. are formed immediately above, and the plate line P0 made of a metal wiring layer is formed on the upper layer.
Plate shunt wires P00S to P03S and P1 to be shunt wires such as 0 to P03 and P10 to P11
0S to P11S are formed. Then, sub-data lines d000 and d100, etc. are formed in the upper layer of these plate shunt lines so as to be horizontal to the semiconductor substrate surface,
Further, the plate line P is orthogonal to these sub-data lines.
00 to P03 and P10 to P11 are formed.

On the other hand, the N-type diffusion layer ND has word lines W0L, W0U, W1U and W1 as shown in FIG.
The diffusion layer ND is formed by using L and the like as a part of the photomask.
4 to ND8 and the like. Of these, select MOSFE
As shown in FIG. 11, the diffusion layer ND6 serving as the common drain D of TQN1 and QD2 and QN3 and QD4 is provided with the corresponding data line D0 via the contact CON1.
It is combined with 0 and so on. Further, the diffusion layer ND4 serving as the drain D of the selection MOSFET QD1 is coupled to the corresponding sub data line d000 or the like via the buried conductive layer BC6, and the diffusion layer ND8 (not shown) serving as the drain D of the selection MOSFET QD3 has the same buried layer. It is coupled to the corresponding sub data line d100 through the embedded conductive layer.

That is, in the FRAM of this embodiment, the sub data lines d000 to d003 and d100 to d10 are used.
Third grade and plate lines P00-P03 and P10-P1
And the like are formed in the upper layer of the metal wiring layer including the data line and the plate shunt line, and are formed after the wiring forming process for forming the metal wiring layer is completed. As is well known, in the wiring formation process, CVD
(Chemical Vapor Deposition
n) In the conventional FRAM in which a heat treatment of 400 to 500 ° C. is required for the processing and the like, and the wiring forming process is performed after the ferroelectric capacitor is formed, the information holding characteristic of the ferroelectric capacitor previously formed by this heat treatment is high. to be influenced. In the case of this embodiment, the ferroelectric capacitor is formed after the wiring forming process is completed, so that the information holding characteristic of the ferroelectric capacitor is not changed by the heat treatment in the wiring forming process, whereby the 1-MOS / multi-capacitor FRA is formed.
The operating characteristics of M can be further stabilized.

As shown in the above-mentioned embodiment, by applying the present invention to a semiconductor memory device such as a 1-MOS / multi-capacitor type FRAM having a ferroelectric capacitor as a memory element, the following operational effects are obtained. Is obtained. That is, (1) In a 1-MOS / multi-capacitor type FRAM or the like in which a predetermined number of ferroelectric capacitors are provided corresponding to one selection MOSFET, a predetermined number of ferroelectric capacitors whose lower electrodes are commonly coupled By forming a part or all of the selected select MOSFETs so as to overlap the upper layer of the corresponding select MOSFETs, a predetermined number of ferroelectric capacitors corresponding to the select MOSFETs are three-dimensionally formed to improve the layout efficiency of the memory array section. The effect of being able to do is obtained.

(2) In the above item (1), a stress prevention MOSFET is provided corresponding to a predetermined number of ferroelectric capacitors whose lower electrodes are commonly coupled, and a part or all of each stress prevention MOSFET is provided. By forming the ferroelectric capacitors in a lower layer corresponding to a predetermined number of them, the layout efficiency of the memory array section can be further improved while preventing stress on the ferroelectric capacitors that are in the non-selected state. The effect of being able to be obtained is obtained. (3) According to the above items (1) and (2), the chip area of the FRAM or the like can be reduced, and the cost reduction can be promoted.

(4) In the above items (1) to (3),
By forming a sub data line, to which the lower electrodes of a predetermined number of ferroelectric capacitors are commonly coupled, horizontally with respect to the semiconductor substrate surface and flattening the upper surface by the CMP method, especially at both ends of the sub data line. The effect of preventing deformation of the formed ferroelectric capacitor is obtained. (5) In the above item (4), the ferroelectric capacitor and related sub data lines are
By forming it on the upper layer of the metal wiring layer, it is possible to eliminate the effect of the heat treatment in the wiring forming step on the retention characteristics of the ferroelectric capacitor. (6) According to the above items (4) and (5), it is possible to obtain the effect that the operating characteristics of the 1MOS / multi-capacitor type can be stabilized.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the memory array MARY and the peripheral portion of the FRAM can be divided into a plurality of memory mats. Also, the FRAM has a × 1 or × 16 bit configuration,
An arbitrary bit configuration can be adopted, and the block configuration, the combination of the activation control signal and the address signal, the kind of the internal voltage and the potential relation, and the like can adopt various embodiments.

In FIGS. 2, 5, and 8, the number of memory blocks forming the memory array MARY can be set arbitrarily, and the number of plate lines and data lines forming each memory block and the number of sub-data lines can be combined. The number of ferroelectric capacitors to be used can be set arbitrarily. Figure 5
, Stress prevention MOSFETs QP0 and QP
The drain of 1 may be coupled to the supply point of the internal voltage HVO, for example. Furthermore, the specific circuit configuration of the memory array MARY shown in FIGS. 3, 4, 6, 7, 9, 10 and 11 and the conductivity type of the MOSFET, the layout, the element structure, and the like are the same as those of the embodiment. Not restricted by example.

In the above description, the case where the invention made by the present inventor is mainly applied to the FRAM of the single-chip microcomputer which is the field of application which is the background of the invention has been described, but the present invention is not limited to this. , FRAM formed as a single unit or FRAM
It can also be applied to various digital integrated circuit devices having a built-in RAM. The present invention can be widely applied to at least a 1-MOS / multi-capacitor type semiconductor memory device having a ferroelectric capacitor as a memory element.

[0049]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, 1M in which a predetermined number of ferroelectric capacitors are provided corresponding to one selection MOSFET
In an OS / multi-capacitor type FRAM or the like, a part or all of a predetermined number of ferroelectric capacitors whose lower electrodes are commonly coupled are formed so as to overlap an upper layer of a corresponding selection MOSFET, and a predetermined number of ferroelectric capacitors are formed. By forming a ferroelectric capacitor and a sub-data line, etc., which is a lower electrode commonly connected to the ferroelectric capacitor, on the upper layer of the metal wiring layer after the wiring forming process, a predetermined number of ferroelectric capacitors corresponding to the selection MOSFET are formed. The three-dimensional formation can improve the layout efficiency of the memory array section and reduce the chip area of the FRAM or the like. In addition, the sub-data lines, which are the commonly coupled lower electrodes of a predetermined number of ferroelectric capacitors, are flattened,
It is possible to prevent the deformation of the ferroelectric capacitor at both ends thereof, and it is possible to eliminate the influence of the heat treatment in the wiring forming process on the retention characteristics of the ferroelectric capacitor. As a result, cost reduction of a 1-MOS / multi-capacitor type FRAM or the like can be promoted and its operation characteristics can be stabilized.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an FRAM to which the present invention is applied.

FIG. 2 is a first memory array included in the FRAM of FIG.
3 is a partial circuit diagram showing an embodiment of FIG.

FIG. 3 is a partial plan layout view showing an embodiment of the memory array of FIG.

FIG. 4 is a cross-sectional structural view taken along the line AB of the memory array of FIG.

5 is a second memory array included in the FRAM of FIG.
3 is a partial circuit diagram showing an embodiment of FIG.

FIG. 6 is a partial plan layout view showing an embodiment of the memory array of FIG.

7 is a CD cross-sectional structural view showing an embodiment of the memory array of FIG.

8 is a third memory array included in the FRAM of FIG.
3 is a partial circuit diagram showing an embodiment of FIG.

9 is a partial plan layout view showing an embodiment of the memory array of FIG. 8. FIG.

10 is an EF showing an embodiment of the memory array of FIG.
FIG.

FIG. 11 is a G-H showing an embodiment of the memory array of FIG.
FIG.

12 is an IJ showing an embodiment of the memory array of FIG. 9;
FIG.

FIG. 13 is a partial sectional structural view showing an example of a FRAM memory array developed by the inventors of the present invention prior to the present invention.

[Explanation of symbols]

MARY ... memory array, XD ... X address decoder, PD ... plate driver, XB ... X address buffer, YS ... Y switch, YD ... Y
Address decoder, YB ... Y address buffer, R
W ... Read / write circuit, OB ... Data output buffer, IB ... Data input buffer, VG ... Internal voltage generation circuit, TC ... Timing control circuit. MB0
0-MB07, MB10-MB17 ... Memory block, W0-W1, W0U-W1U, W0L-W1L.
..Word lines, P00 to P03, P10 to P13 ...
Plate line, D00 to D0n to D70 to D7n ...
・ Data line, d000 to d00n to d070 to d0
7n, d100 to d10n to d170 to d17n
..Sub data lines, C00 to C03, C10 to C13
..Ferroelectric capacitors, QN0 to QN4 ... Enhancement type N-channel MOSFETs, QP0 to QP
1-enhancement type P-channel MOSFE
T, QD1 to QD4 ... Depletion type N-channel MOSFET. PSUB ... P-type semiconductor substrate, NW
... N-type well region, PW ... P-type well region, N
D, ND1 to ND7 ... N-type diffusion layer, N ⁺ ... N-type high-concentration semiconductor region, PD, PD1 to PD2 ... P-type diffusion layer, P ⁺ ... P-type high-concentration semiconductor region, P ^- ··· P
Type low-concentration semiconductor region, D ·· drain, S ... Source, BC1 to BC6 ... Buried conductive layer, CHS ... Channel stopper, SE ... Ferroelectric material, FI ... Field insulating film , IL ... Insulating film, SVSS ... Ground potential supply wiring, P00S to P03S, P10S to P1
1S: Plate shunt wire.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display location G11C 14/00 H01L 21/304 321 Z 27/10 451 7210-4M

Claims (5)

[Claims] 1. A ferroelectric capacitor in which a predetermined number of electrodes are commonly coupled to each other and the other electrode is coupled to a corresponding plate line, and the predetermined number of ferroelectric capacitors are commonly coupled to each other. A memory array including a selection MOSFET provided between one electrode and a corresponding data line is provided, and a part or all of the predetermined number of ferroelectric capacitors overlaps the upper layer of the corresponding selection MOSFET. A semiconductor memory device characterized by being formed as follows. 2. One electrode of the predetermined number of ferroelectric capacitors that is commonly connected is integrated as a sub-data line, and the sub-data line is formed horizontally with respect to the semiconductor substrate surface. In addition, the upper surface of the buried conductive layer is subjected to the planarization process by the CMP method, and the buried conductive layer formed by the selective burying method is formed between the sub-data line and the corresponding diffusion layer serving as the source of the selection MOSFET. 2. The semiconductor memory device according to claim 1, wherein a layer is provided. 3. The memory array is provided between one electrode of the predetermined number of ferroelectric capacitors commonly coupled to each other and a predetermined potential supply point, and a part or all of the memory array corresponds to the predetermined number. For preventing stress formed by overlapping the lower layer of ferroelectric capacitor
3. The semiconductor memory device according to claim 1, further comprising: 4. The ferroelectric capacitor and the sub data line are formed on an upper layer of a metal wiring layer after the wiring forming process is completed. Semiconductor memory device. 5. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is built in a single-chip microcomputer.