JP2572746B2 - Method for manufacturing semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a mask-read-only memory (M-M) of a semiconductor memory device.
The present invention relates to a memory structure for realizing high speed and high integration of ask ROM).

[Conventional technology]

At present, as a ROM (Read-Only-Memory), an EPROM (Erasable and Programmable-Read-Only-ROM) that can be electrically programmed and erased by irradiation with ultraviolet rays.
Mask R, which can program the memory contents by switching between the memory and manufacturing process masks
There is OM.

The problem with Mask ROM is that the user submits the data to be programmed into the memory to the semiconductor maker, and the semiconductor maker creates a mask (usually one mask for one process) that matches the data, and Then, the semiconductor memory units “1” and “0” in the silicon wafer state are determined,
It is built into a package and supplied to the user, so how to shorten the delivery time, and how to reduce the unit price per bit by reducing the unit price per bit by increasing the integration like a normal semiconductor memory. There is a problem. General Mask ROM 3 which is manufactured in consideration of the above two points
The three types of plan views are shown in FIGS. Figure A shows the Mask ROM (field RO) by switching the field mask.
M) and Fig. B shows the mask by switching the contact mask.
ROM (hereinafter referred to as contact ROM), and FIG. C shows Mask ROM (hereinafter referred to as implanted ROM) by switching the ion implantation mask.
It is. For the sake of simplicity, a broken line (1) is indicated by a polysilicon gate, a dashed line is indicated by a dashed line for convenience, (2) is a drain aluminum conductor, and a dot is indicated (3) is an impurity diffusion region. (4) is a contact hole for connecting the drain aluminum conductor (2) and the impurity diffusion region (3), (5) is a portion of the impurity diffusion region not formed by switching the field mask, and FIG. (6) indicated by the mark is a portion of the contact hole which is not formed by switching the contact mask, and (7) is a 1-bit memory transistor where the polysilicon gate (1) and the impurity diffusion region (3) cross each other. Area. (8) is an implantation region where the threshold value of the transistor is changed by switching the implantation mask. Field ROM (Figure A), Contact ROM (Figure B),
The injection ROM (FIG. C) is composed of the above plan view, and the area for two memories is 1 in the field ROM.
Contact ROM is 1.4-1.5, injection ROM is 1.2-1.3,
The field ROM is the most advantageous in terms of cost, and the injection RO
M, then contact ROM. Next, a general silicon wafer manufacturing process will be described below.

Field oxide film formation ← Field ROM ↓ Mask switching Gate oxide film formation ↓ Ion implantation (I) ↓ Ion implantation (II) ← Implantation ROM ↓ Mask switching Polysilicon formation ↓ Source / drain formation ↓ Contact hole / etching ← Contact ROM ↓ Mask Switching Aluminum conductor formation ↓ Passivation formation As can be seen at first glance, in the case of field ROM, from the mask switching process to the passivation formation process
FLOW has 8 steps. 5 steps for injection ROM, 2 steps for contact ROM, and 2 steps for contact ROM.
It is getting longer in ROM order. As described above, injection ROMs are increasingly used in recent years from the viewpoint of cost and work period. FIG. 4 is a block diagram showing a circuit configuration of a conventional injection ROM. (10) is the external address input terminal,
(11) is an address buffer, (12) is an X decoder, (1)
3) is a memory array, (14) is a Y decoder, (15) is a sense amplifier, (16) is an output buffer, (17) is an output terminal of a data output Do, and (18) and (19) are memory arrays ( 13) Word line and bit line. Although FIG. 4 shows only the data output Do,
~ Dx are in parallel.

First, an address buffer (11) receives an external address input (10) consisting of Ao to Ax, and receives an X and Y decoder (1).
Send signals to 2) and (14). The X decoder (12) selects a predetermined word line (18) according to the transmitted signal. Similarly, a predetermined bit line (1
9) Select The selected word line (1
8) and bit line (19) for memory array (13)
, The only memory transistor for the data output Do is selected, and its memory contents are read.

FIG. 5 is a diagram showing the internal circuit configuration of the memory cell (13) of this injection ROM, and each memory transistor Cli-Cni, Clj-
The transfer gates between the common source lines Cnj and Clk to Cnk and the ground point have word lines WLi and WL, respectively.
Inverted signals of j and WLk are included. The "H" level is supplied to the word line when not selected, and the "L" level is applied when selected. Memory transistors are provided with two types of threshold transistors of an enhancement type and a depth type by ion implantation. In FIG. 5, the memory transistors of Cmj are of a depletion type and the rest are of an enhancement type. When word line WLj is selected,
Since the word line is at "L" level, the memory transistor
Clj and Cuj are non-conductive, Cmj is conductive and the common source line is GN
The bit lines BLl and BLn are at the power supply voltage level, and BLm is at a potential (hereinafter referred to as K level) depending on the on-resistance ratio of the load transistor (A) and the memory transistor Cmj.
Is selected, the sense amplifier determines "1", and if BLm is selected, it becomes "0".

In this manner, "1" or "0" of the memory content can be selected depending on whether the memory transistor is an enhancement type or a depletion type by ion implantation.

[Problems to be solved by the invention]

Since the conventional ion-implanted ROM is configured as described above, when the memory transistor of the depletion type is selected, it takes time to reduce the bit line from the “H” level to the “K” level due to the ON resistance of the transistor. And the access time is slow.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a ROM having a simple configuration and a short access time and capable of high integration.

[Means for solving the problem]

In the method of manufacturing a semiconductor memory device according to the present invention, a source impurity diffusion region and a drain impurity diffusion region are formed at a predetermined interval in a semiconductor substrate, and a gap between the source impurity diffusion region and the drain impurity diffusion region is formed. A first transistor having a gate conductor layer formed on a surface of the semiconductor substrate via a gate insulating film, and a source impurity diffusion region and a drain impurity diffusion region connected to each other in the semiconductor substrate to have the same potential; And a second transistor formed so that the first and second transistors are memory transistors respectively corresponding to stored binary information. A step of ion-implanting one conductivity type impurity into the region, and forming a gate insulating film over the entire surface of the ion-implanted predetermined region. A step of forming a resist film in a first transistor forming region on the gate insulating film, and a step of etching and removing the gate insulating film other than the first transistor forming region using the resist film as a mask; Using the gate insulating film and the resist film as a mask, introducing and diffusing an impurity of a conductivity type opposite to the one conductivity type to form an impurity diffusion region, removing the resist film, and removing a predetermined region of the semiconductor substrate; Forming a gate insulating film over the entire surface, forming a gate conductor layer over the first and second transistor forming regions, forming an insulating film over the entire predetermined region of the semiconductor substrate, Forming contact holes in the drain regions of the first and second transistor formation regions, and forming a conductor film forming a bit line through the contact holes. It is obtained by the.

[Action]

In the method of manufacturing a semiconductor memory device according to the present invention, since the above-described configuration is employed, a ROM capable of high-speed read operation using a source-drain short-circuit transistor as an OFF-state transistor is improved in integration degree. Can be manufactured.

〔Example〕

Hereinafter, the structure of the embodiment will be clarified by describing a manufacturing process of an embodiment of the present invention. Fig. 1 (a)-
(F) is a sectional view of a main part showing a state in a main stage of manufacturing according to an embodiment of the present invention. First, the semiconductor substrate (10
For (0), a field oxide film is formed, and respective ion implantations for the enhancement type, the depletion type and the like are performed. In this embodiment, the enhancement type ion implantation is performed for the entire memory array ( First
Figure a). Next, a gate insulating film (9) is formed on the entire surface (FIG. 1b), and a first transistor region corresponding to memory information "1" on the gate insulating film (9) formed on the entire surface. In (a), a resist film (20) is formed, and in the second transistor region (b) corresponding to the memory information "0", no resist film is formed as shown by a broken line (21) (first).
Figure c). Subsequently, etching is performed using the resist film (20) as a mask to leave the gate insulating film (9) only in the first transistor region (A).
When the impurity diffusion region (3) is formed by introducing and diffusing an impurity using the gate insulating film (9) as a mask, the source and drain regions are formed separately from each other in the first transistor region (A) and the second transistor region (A) is formed. Transistor area (b)
Then, the source and drain regions are formed by continuous connection (FIG. 1d). Next, the resist film (20) is removed, an insulating film is uniformly formed on the entire upper surface by thermal oxidation, and a gate conductor layer is formed in both the first transistor region (a) and the second transistor region (b). Form (1) (FIG. 1e). After that, in consideration of the displacement of the mask at the time of forming the gate, soft doping of the source and the drain is performed (FIG. 1f), and a phosphosilicate glass (PSG) film (22) is formed on the entire upper surface.
(FIG. 1g). Next, a contact hole (4) is formed in the drain region, and a drain aluminum conductor (2) forming a bit line is formed through the contact hole (4).
Figure h). Although not shown, a passivation protective film is formed thereon to complete the memory cell.

 FIG. 2 shows a ROM circuit diagram completed in this manner.

In FIG. 2, Cmj is a short-circuited memory transistor of this embodiment. Assuming that the remaining memory transistors are all enhancement type, when WLj is selected, the word line is at "L" level, so Clj and Cmj are non-conductive, and Cmj is
Since the source / drain regions are connected, they are conductive. Since the common source line is at the GND level, B
Ll and BLm are at the power supply voltage level, BLm is at the GND level, and are "1" when the bit lines BLl and BLn are selected by the Y decoder, and "0" when the bit line BLm is selected. Thus, the same operation can be expected even if the memory transistor having the short-circuited structure of this embodiment is used in place of the conventional memory transistor of the ion implantation ROM. However, when the memory transistor having the short-circuit structure of the present embodiment is used, the resistance value is sufficiently smaller than the conventional on-resistance of the depletion type, and without delay, falls below the determination level (K level) of the sense amplifier. can get.

Further, since all the transistors in the memory array are single type transistors, there is no dimensional limitation due to the mask, and the degree of integration is improved.

〔The invention's effect〕

As described above, according to the method for manufacturing a semiconductor memory device of the present invention, the source impurity diffusion region and the drain impurity diffusion region are formed at a predetermined interval in the semiconductor substrate, and the source impurity diffusion region and the drain impurity diffusion region are formed. A first transistor in which a gate conductor layer is formed on a surface of the semiconductor substrate between the impurity diffusion region and a gate insulating film via a gate insulating film; and a source impurity diffusion region and a drain impurity diffusion region in the semiconductor substrate. A second transistor connected to each other and formed to have the same potential, wherein the first and second transistors are memory transistors respectively corresponding to stored binary information. A step of ion-implanting one conductivity type impurity into a predetermined region of the semiconductor substrate; Forming an over gate insulating film, forming a first transistor forming region in the resist film on the gate insulating film, the resist film as a mask,
A step of etching away the gate insulating film other than the first transistor formation region; and introducing and diffusing an impurity of a conductivity type opposite to the one conductivity type using the gate insulation film and the resist film as a mask to form an impurity diffusion region. Forming a gate insulating film on the entire surface of a predetermined region of the semiconductor substrate by removing the resist film;
Forming a gate conductor layer in the transistor formation region, forming an insulating film over the entire surface of the predetermined region of the semiconductor substrate, and forming contact holes in the drain regions of the first and second transistor formation regions. And forming a conductive film forming a bit line through the hole, so that one memory transistor of binary information can be replaced with a high-speed transistor using a short-circuited transistor between the source and drain regions. There is an effect that the access ROM can be manufactured with high integration.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main part showing a state in a main stage of manufacture of an embodiment of the present invention, FIG. 2 is a circuit diagram of a memory cell of a ROM according to an embodiment of the present invention, and FIG. FIG. 4 is a plan view of a memory cell of the conventional three types of ROM, FIG. 4 is a block diagram showing a circuit configuration of a conventional ion implantation ROM, and FIG. 5 is a circuit diagram of a memory cell of the conventional ion implantation ROM. . In the figure, (100) is a semiconductor substrate, (1) is a gate conductor layer, (3) is an impurity diffusion layer, (9) is a gate insulating film, (A) is a first transistor region, and (B) is a first transistor region. 2 transistor region. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] A source impurity diffusion region and a drain impurity diffusion region formed at a predetermined distance from each other in a semiconductor substrate, and are formed on a surface of the semiconductor substrate between the source impurity diffusion region and the drain impurity diffusion region; A first transistor in which a gate conductor layer is formed via a gate insulating film, and a first transistor formed in the semiconductor substrate so that a source impurity diffusion region and a drain impurity diffusion region are connected to each other and have the same potential. And the first transistor.
A method of manufacturing a semiconductor memory device in which a second transistor is a memory transistor corresponding to stored binary information, wherein a step of ion-implanting one conductivity type impurity into a predetermined region of the semiconductor substrate; Forming a gate insulating film over the entire surface of the predetermined region, forming a resist film in a first transistor forming region on the gate insulating film, and using the resist film as a mask, forming the first transistor forming region A step of etching and removing the gate insulating film other than the above; a step of introducing and diffusing an impurity of a conductivity type opposite to the one conductivity type using the gate insulating film and the resist film as a mask to form an impurity diffusion region; Removing the film and forming a gate insulating film on the entire surface of the predetermined region of the semiconductor substrate; Forming a gate conductor layer in the formation region; forming an insulating film over the entire surface of the predetermined region of the semiconductor substrate; forming a contact hole in a drain region of the first and second transistor formation regions; Forming a conductive film forming a bit line through the semiconductor memory device.