JP3631562B2 - Nonvolatile semiconductor memory device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device such as a mask ROM and a manufacturing method thereof.
[0002]
[Prior art]
The mask ROM program method includes a NOR type ion implantation program method, a NOR type contact hole program method, a NOR type diffusion layer program method, a NAND type ion implantation program method, etc. ("CMOS VLSI design" supervised by Takuo Kanno, 1989, pp 168-169). The NOR type mask ROM has an advantage that the operation speed is high although the memory cell area is slightly larger than that of the NAND type mask ROM.
[0003]
[Problems to be solved by the invention]
However, since the conventional mask ROM can store information only in the memory cell portion, in order to increase the storage capacity of the entire ROM, the number of memory cells, that is, the total area of the memory cells must be increased. There wasn't. However, if the total area of the memory cells is increased, the entire ROM becomes larger, and there is a problem that the chip becomes larger when an IC chip is formed.
[0004]
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a nonvolatile semiconductor memory device such as a mask ROM capable of increasing the storage capacity without increasing the number of memory cells, that is, the total area of the memory cells, and a method for manufacturing the same. It is.
[0005]
[Means for Solving the Problems]
In order to solve the above-described problems, a nonvolatile semiconductor memory device according to the present invention includes a plurality of memories arranged in a matrix by shield plate electrodes formed on a field region of a semiconductor substrate via a shield gate insulating film. A non-volatile semiconductor memory device in which element isolation between cell transistors is performed, wherein the shield plate electrode on the field region is used as a gate electrode, and the source or drain of a pair of memory cell transistors adjacent to each other with the field region interposed therebetween And a field shield transistor having a pair of impurity diffusion layers adjacent to each other with the field region sandwiched between the source and drain to store information, and a variable voltage applied to the shield plate electrode. Applying to the shield plate electrode Reading means for reading information stored in the field shield transistor by changing the pressure is provided, and the shield plate electrodes are formed in patterns separated from each other in the row direction and the column direction of the matrix, and are separated from each other. A wiring layer is provided for connecting the shield plate electrodes in the row direction of the matrix.
[0006]
A method for manufacturing a nonvolatile semiconductor memory device according to the present invention includes element isolation between a plurality of memory cell transistors arranged in a matrix by a shield plate electrode formed on a field region of a semiconductor substrate via a shield gate insulating film. A method of manufacturing a non-volatile semiconductor memory device in which a first conductivity type impurity is implanted into a memory cell region and a field region of a first conductivity type semiconductor substrate, and the first conductivity type is manufactured. Forming a shield gate insulating film on the surface of the semiconductor substrate of the type, forming a semiconductor film doped with an impurity of the second conductivity type on the shield gate insulating film, and Process the semiconductor film doped with impurities to form shield plate electrodes with patterns separated from each other in the row and column directions of the matrix. Covering the shield plate electrode with an insulating film, forming a field shield element isolation structure on the field region, and forming a shield gate insulating film formed on the element region sandwiched between the field regions Removing, forming a gate insulating film on the element region sandwiched between the field regions, forming a word line serving as a gate electrode of a memory cell transistor on the gate insulating film, and the memory After forming the drain diffusion layer of the cell transistor, a step of forming a first interlayer insulating film on the entire surface, and forming a first contact hole reaching the drain diffusion layer in the first interlayer insulating film, Forming a bit line made of a conductor film connected to the drain diffusion layer through the first contact hole; and a second interlayer on the entire surface Forming an edge film and opening a second contact hole reaching the shield plate electrode in the first interlayer insulating film, the second interlayer insulating film, and the insulating film covering the shield plate electrode; Forming a wiring layer made of a conductive film connected to the shield plate electrode through the second contact hole and connecting the shield plate electrode in the row direction of the matrix. Features.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments in which the present invention is applied to a NOR type ion implantation program type mask ROM will be described below with reference to the drawings.
[0010]
First, a first embodiment of the present invention will be described with reference to FIGS.
[0011]
FIG. 2 is a schematic plan view of the memory cell array portion of the mask ROM according to the first embodiment. In the memory cell array portion, a field shield element isolation structure including a shield plate electrode 22 is formed in a field region (element isolation region) extending along the column direction of the memory cell array arranged in a matrix. Therefore, in this embodiment, element isolation between the memory cells is performed only in the row direction of the memory cells, and element isolation by the element isolation structure is not performed in the column direction.
[0012]
In the row direction of the memory cell array, a word line 24 that constitutes the gate electrode of each memory cell transistor is provided across the field region on the field shield element isolation structure. On the other hand, a bit line 25 is provided on each element region sandwiched between field regions extending in the column direction, and is connected to the drain diffusion layer of each memory cell transistor by a bit contact 26. On the source side of each memory cell transistor, the substrate portion constitutes a source line (ground line).
[0013]
Next, the memory cell array part of FIG. 2 and its peripheral circuit configuration will be described. FIG. 1 shows a memory cell array and its peripheral circuit configuration according to the present embodiment. In FIG. 1, memory cell transistors Q ₀₀ , Q ₀₁ ,..., Q ₁₀ ,... Are arranged in a matrix corresponding to each crossing position of the word line 24 and the bit line 25. Then, the word line _x 0 is a row _line, x 1, _{x 2,} ... are connected to a row decoder 32, On the other hand, the bit line _y 0 is a column _{line, y 1, ..., y n} -1 is a column decoder 33 It is connected to the. Reference numeral 27 denotes a source line. Reference numeral 35 denotes a sense amplifier for detecting the potentials of the bit lines y ₀ , y ₁ ,..., Y _n−1 .
[0014]
Each memory cell transistors _{Q 00, Q 01, ...,} Q 10, ... stores the information in the respective memory cell transistors _{Q 00, Q 01, ...,} Q 10, pre-selective ... silicon semiconductor substrate in the channel region of the .., Q ₁₀ ,..., And the threshold voltage (V _th ) of each of the memory cell transistors Q ₀₀ , Q _{01 ,.} Is done.
[0015]
Next, how to read information will be described. First, the row decoder 32 sets the selected word line to the “H” level, the non-selected word line to the “L” level, and the column decoder 33 sets the selected bit line to the “H” level. . Then, when the threshold voltage _Vth of the selected memory cell transistor corresponding to the crossing position of the selected word line and the selected bit line is high, the potential of the selected bit line remains at “H” level. On the other hand, when the threshold voltage _{Vth of} the selected memory cell transistor is low, a current flows through the selected bit line and becomes “L” level. Therefore, by detecting the potential of the selected bit line with the sense amplifier 35, the information stored in each of the memory cell transistors Q ₀₀ , Q ₀₁ ,..., Q ₁₀ ,.
[0016]
In the mask ROM according to the present embodiment, in addition to the above-described normal memory cell transistors Q ₀₀ , Q ₀₁ ,..., Q ₁₀ ,. Information is also stored in and read from the transistor.
[0017]
FIG. 3 is a cross-sectional view taken along the line III-III of FIG. 2. The shield plate electrode 22 formed on the field region of the silicon semiconductor substrate 41 via the shield gate oxide film 21 is used as a gate electrode. A parasitic MOS transistor is formed using the pair of drain diffusion layers 23 of adjacent memory cell transistors with the source and drain interposed therebetween. In the figure, 25 is a bit line, 26 is a bit contact, and 47 and 51 are interlayer insulating films. In a normal state, the potential of the shield plate electrode 22 is fixed to the ground potential, and conduction of this parasitic MOS transistor is blocked.
[0018]
As shown in FIG. 1, one such parasitic MOS transistor (field shield transistor FT ₁ , FT ₂ ,...) Is formed corresponding to each column. In this case, it does not matter which memory cell transistor the drain diffusion layer of the source / drain of each field shield transistor FT ₁ , FT ₂ ,.
[0019]
In the present embodiment, when the memory cell transistors Q ₀₀ , Q ₀₁ ,..., Q ₁₀ ,... Are written (programmed), impurities are selectively ion-implanted into the field region, so that the field shield transistor FT ₁ , FT ₂ ,..., Threshold voltage V _{th (f)} is previously made to be a high value (for example, 2 V) and a low value (for example, 1 V).
[0020]
And the shield plate electrode 22 is connected to the voltage control circuit 34, and the applied voltage is comprised variably.
[0021]
In a normal state, as described above, the potential of the shield plate electrode 22 is fixed to the ground potential. At this time, even if the ground potential of the shield plate electrode 22 is somewhat unstable by setting the lower value of the threshold voltage V _{th (f)} of each field shield transistor FT ₁ , FT ₂ ,. Each field shield transistor FT ₁ , FT ₂ ,..., Which is a parasitic MOS transistor, is surely prevented from conducting accidentally.
[0022]
On the other hand, when reading the information stored in the field shield transistors FT ₁ , FT ₂ ,..., For example, when reading the information stored in the field shield transistor FT ₁ , the column decoder 33 sets the potential of the bit line y ₀ . The precharge potential V _pcg (“H” level) is set, and all the remaining bit lines y ₁ ,..., Y _n−1 are set to the ground potential (“L” level). The row decoder 32 sets the potentials of all the word lines x ₀ , x ₁ , x ₂ ,... To a low logic level (“L” level), and the voltage control circuit 34 _sets the potential V _gate of the shield plate electrode 22 to 1V. <V _gate <2V.
[0023]
Then, the field shield transistor FT ₁ threshold voltage _{V th (f)} is if set to 2V, since the field shield transistor FT ₁ does not conduct, the bit line _{y 0} potential of the precharge voltage _{V pcg} It remains unchanged. On the other hand, if the field shield transistor FT ₁ threshold voltage _{V th (f)} is set to 1V, the field shield transistor FT ₁ conducts, since the bit line _{y 0} current flows to the bit line _{y 1} , the potential of the bit line _{y 0} is changed to the ground potential (0V). Accordingly, the information stored in the field shield transistor FT ₁ can be read by detecting the potential of the bit line y ₀ with the sense amplifier 35.
[0024]
As described above, in the mask ROM according to the present embodiment, the field shield transistors FT ₁ , FT formed in the field region in addition to the normal memory cell transistors Q ₀₀ , Q ₀₁ ,..., Q ₁₀ ,. ₂ ,... Can also store information and read it, so that the storage capacity can be increased without increasing the total area of the memory cells as compared with the conventional mask ROM. For example, when the memory capacity of a conventional mask ROM composed of only normal memory cell transistors Q ₀₀ , Q ₀₁ ,..., Q ₁₀ ,... Is 4 MB, about 2 kB is further provided by the field shield transistors FT ₁ , FT ₂ ,. Storage capacity can be added.
[0025]
In each field shield transistor FT ₁ , FT ₂ ,..., The channel region into which impurities are selectively introduced may be a single channel region between a pair of sources / drains. If there are a plurality of channel regions, the channel region through which current flows increases, and the reading speed is improved.
[0026]
Next, a second embodiment of the present invention will be described with reference to FIGS.
[0027]
FIG. 5 is a schematic plan view of the memory cell array portion of the mask ROM according to the second embodiment. In the memory cell array portion according to the second embodiment, unlike the first embodiment described above, the shield plate electrodes 22 are separated from each other in the column direction at positions on the source lines 27 as shown in the figure. It is formed in a pattern. In other words, in the second embodiment, the shield plate electrodes 22 are formed in patterns separated from each other in the row direction and the column direction of the matrix of the memory cell array. These shield plate electrodes 22 are connected to each other in the row direction by an upper wiring layer 37 (see FIG. 6D) via a field contact 36.
[0028]
Next, the memory cell array portion of FIG. 3 and its peripheral circuit configuration will be described. FIG. 4 shows a memory cell array according to the second embodiment and its peripheral circuit configuration. In the second embodiment, a plurality of field shield transistors FT are formed also in the column direction of the matrix of the memory cell array. As a result, field shield transistors FT ₀₀ , FT ₀₁ ,..., FT ₁₀ , FT ₁₁ ,. Arranged in a matrix. The wiring layer 37 described above includes the row lines of the field shield transistors FT ₀₀ , FT ₀₁ ,..., FT ₁₀ , FT ₁₁ ,... (Field shield word lines z ₀ , z ₁ , z ₂ , z ₃ , And is connected to the field shield decoder circuit 38.
[0029]
In the second embodiment, storage and reading of information in the memory cell transistors Q ₀₀ , Q ₀₁ ,..., Q ₁₀ ,... Are the same as those in the first embodiment described above. On the other hand, the field shield transistor _{FT 00, FT 01, ...,} FT 10, FT 11, the writing of information of ... to, the memory cell transistor _{Q 00, Q 01, ...,} Q 10, ... program at the time, each field shield transistor of _{FT 00, FT 01, ...,} FT 10, FT 11, selectively impurity is ion-implanted ... silicon semiconductor substrate of the field region portion serving as a channel region of each field shield transistor _FT 00, _{FT 01,} ..., Threshold values V _{th (f)} of FT ₁₀ , FT ₁₁ ,... Are controlled in advance to a high value (for example, 2 V) and a low value (for example, 1 V).
[0030]
For example, when information stored in the field shield transistor FT ₀₀ is read, the column decoder 33 _sets the voltage of the bit line y _{0 to} the precharge voltage V _pcg (“H” level), and all the remaining bit lines The potentials y ₁ , y ₂ ,... are set to the ground potential (“L” level). The row decoder 32 sets all the word lines x ₀ , x ₁ , x ₂ , x ₃ , x ₄ , x ₅ ,... To a low logic level (“L” level), and the field shield decoder 38 Only the potential V _{gate of the} field shield word line z ₀ is set to 1V <V _gate <2V.
[0031]
Then, the threshold voltage _{V th} of field shield transistor _{FT 00 (f)} is if set to 2V, since the field shield transistor _{FT 00} does not conduct, the bit line _{y 0} potential of the precharge voltage _{V pcg} It remains unchanged. On the other hand, if the threshold voltage _{V th} of field shield transistor _{FT 00 (f)} is set to 1V, the field shield transistor _{FT 00} is rendered conductive, since the bit line _{y 0} current flows to the bit line _{y 1} , the potential of the bit line _{y 0} is changed to the ground potential (0V). Therefore, the information stored in the field shield transistor FT ₀₀ can be read by detecting the potential of the bit line y ₀ with the sense amplifier 35.
[0032]
In the second embodiment, the field shield decoder circuit 38 functions as a voltage control circuit for variably configuring the potential of the shield plate electrode 22, and field shield transistors FT ₀₀ , FT ₀₁ ,..., FT ₁₀ , FT _11, field shield wordline _z 0 selected when reading the stored information in _{..., z 1, z 2,} z 3, except for increasing the ... potential always field shield wordline _z 0, z ₁ , z ₂ , z ₃ ,..., that is, the potential of each shield plate electrode 22 is held at the ground potential.
[0033]
According to the second embodiment, although the circuit configuration is slightly complicated as compared with the first embodiment described above, the number of field shield transistors FT can be increased. Can be increased.
[0034]
Next, a manufacturing method of the memory cell array according to the second embodiment will be described with reference to FIG. 6 corresponds to a cross section taken along line VI-VI in FIG.
[0035]
First, as shown in FIG. 6A, for example, a photoresist 42 having a pattern corresponding to a program to be written is formed on a p-type silicon semiconductor substrate 41 by photolithography, and this photoresist 42 is used as a mask. Then, boron (B) 43 is ion-implanted into the memory cell region and the field region where data is not written (data “0” is written), respectively, with an acceleration energy of about 60 keV and a dose of about 1 × 10 ¹² cm ^−2. . As a result, data “1” is written relatively to the memory cell region and the field region of the region where the ions are not implanted.
[0036]
Next, as shown in FIG. 6B, after removing the photoresist 42, a shield gate oxide film 21 having a film thickness of about 40 nm is formed on the surface of the silicon semiconductor substrate 41 by thermal oxidation, and further thereon. A polycrystalline silicon film having a thickness of about 200 nm doped with phosphorus (P) is formed and processed into a pattern of the shield plate electrode 22. Thereafter, the shield plate electrode 22 is covered with a cap oxide film and a sidewall oxide film to form a field shield element isolation structure on the field region.
[0037]
Next, although not shown in the figure, a gate oxide film having a thickness of about 15 nm is formed by thermal oxidation on the surface of the silicon semiconductor substrate 41 on the element region sandwiched between the field regions (in this region, the gate oxide film is formed first). The shield gate oxide film 21 is removed by anisotropic etching when forming the side wall oxide film of the field shield element isolation structure.) Further, the word serving as the gate electrode of the memory cell transistor is formed thereon. Line 24 is formed (see FIG. 5).
[0038]
Next, as shown in FIG. 6C, after forming the drain diffusion layer 23 of the memory cell transistor, an interlayer insulating film 47 is formed on the entire surface. A contact hole 26 reaching the drain diffusion layer 23 is opened in the interlayer insulating film 47, and a bit line 25 made of a metal film connected to the drain diffusion layer 23 through the contact hole 26 is formed.
[0039]
Next, as shown in FIG. 6D, a second interlayer insulating film 51 is formed, and contact holes 36 reaching the shield plate electrode 22 are opened in the interlayer insulating films 51 and 47 and the like. Then, after forming a wiring layer (field shield word line) 37 made of a metal film connected to the shield plate electrode 22 through the contact hole 36, a surface protective film (not shown) or the like is formed to complete the mask ROM. Let
[0040]
【The invention's effect】
According to the present invention, the storage capacity can be increased without increasing the total area of the memory cells of the nonvolatile semiconductor memory device such as a mask ROM or the chip area.
[Brief description of the drawings]
FIG. 1 is a circuit configuration diagram of a memory cell array of a mask ROM according to a first embodiment of the present invention.
FIG. 2 is a schematic plan view of a memory cell array of a mask ROM according to the first embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a configuration of a field shield transistor of the mask ROM according to the first embodiment of the present invention.
FIG. 4 is a circuit configuration diagram of a memory cell array of a mask ROM according to a second embodiment of the present invention.
FIG. 5 is a schematic plan view of a memory cell array of a mask ROM according to a second embodiment of the present invention.
FIG. 6 is a process sectional view showing a method for manufacturing a mask ROM according to a second embodiment of the present invention.
[Explanation of symbols]
21 shield gate oxide film 22 shield plate electrode 23 drain diffusion layer 24 word line 25 bit line 26 bit contact 27 source line 32 row decoder 33 column decoder 34 voltage control circuit 35 sense amplifier 36 field contact 37 wiring layer (field shield word line)
38 field shield decoder circuit _x 0, _{x 1,} ... word line _y 0, _{y 1,} ... bit line _z 0, _{z 1,} ... field shield word line _{Q 00, Q 01,} ... memory cell transistors _FT 1, _FT 2, ..., FT ₀₀ , FT ₀₁ , ... Field shield transistor

Claims (3)

A non-volatile semiconductor memory device in which element isolation is performed between a plurality of memory cell transistors arranged in a matrix by a shield plate electrode formed on a field region of a semiconductor substrate via a shield gate insulating film,
The shield plate electrode on the field region is used as a gate electrode, and a pair of impurity diffusion layers adjacent to each other across the field region that is the source or drain of a pair of memory cell transistors adjacent to each other across the field region It is configured to store information in the field shield transistor as the drain,
While variably configuring the voltage applied to the shield plate electrode,
Changing the voltage applied to the shield plate electrode, and providing reading means for reading information stored in the field shield transistor;
The shield plate electrode is formed in a pattern separated from each other in the row direction and the column direction of the matrix,
A nonvolatile semiconductor memory device comprising a wiring layer for connecting the shield plate electrodes separated from each other in a row direction of the matrix. By selectively controlling the impurity concentration of the semiconductor substrate in the field region portion in advance, the threshold voltage of the field shield transistor is set to one value selected from at least two kinds of values, and the setting is performed. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the threshold voltage thus read is read out as information stored in the field shield transistor. A method of manufacturing a nonvolatile semiconductor memory device in which element isolation is performed between a plurality of memory cell transistors arranged in a matrix by a shield plate electrode formed on a field region of a semiconductor substrate via a shield gate insulating film. And
Injecting a first conductivity type impurity into the memory cell region and the field region of the first conductivity type semiconductor substrate;
Forming a shield gate insulating film on a surface of the semiconductor substrate of the first conductivity type;
Forming a semiconductor film doped with an impurity of the second conductivity type on the shield gate insulating film;
Processing the semiconductor film doped with impurities of the second conductivity type to form shield plate electrodes with patterns separated from each other in the row direction and the column direction of the matrix;
Covering the shield plate electrode with an insulating film, forming a field shield element isolation structure on the field region, and removing a shield gate insulating film formed on the element region sandwiched between the field regions; ,
Forming a gate insulating film on an element region sandwiched between the field regions;
Forming a word line serving as a gate electrode of a memory cell transistor on the gate insulating film;
Forming a first interlayer insulating film on the entire surface after forming the drain diffusion layer of the memory cell transistor;
A first contact hole reaching the drain diffusion layer is opened in the first interlayer insulating film, and a bit line made of a conductor film connected to the drain diffusion layer through the first contact hole is formed. And a process of
Forming a second interlayer insulating film on the entire surface;
A second contact hole reaching the shield plate electrode is opened in the insulating film covering the first interlayer insulating film, the second interlayer insulating film, and the shield plate electrode, and this second contact is formed. A non-volatile semiconductor memory device comprising a step of forming a wiring layer comprising a conductive film connected to the shield plate electrode through a hole and connecting the shield plate electrode in a row direction of the matrix. Manufacturing method.

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