JPH07509814A - read-only memory cell - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] read-only memory cell Technical field This invention relates to electronic memory devices. More specifically, the present invention relates to a semiconductor substrate. This relates to the read-only memory (ROM) manufactured above.

Unlike volatile memory devices such as random access memory (RAM), R Non-volatile memory, such as OM, retains its information content even when power is removed. In the information The content is incorporated into the ROM cell in advance as a ROM code during the manufacturing process. .

Back C1 technology In the past, various methods have been attempted to realize computational storage elements. Of these One method is to insert a fuse or diode between two address lines. It is. For example, a fuse or diode can be switched on or off. They are used in correspondence with digital bits "0" and "1", respectively. Furthermore, more advanced In particular, metal oxide semiconductor field effect transistors (MO There is also a method using SFET). In this method, for example, the drain of MOSFET The presence or absence of conduction can be used to represent digital bits "1" and "0".

Additionally, different threshold voltage levels of MOSFETs can be paired with different digital data. It can also be used accordingly.

With the increasing demand for large-scale integrated circuits, ROM cells are becoming smaller and smaller in structure. It's getting simpler. These ROM cells are commonly referred to as "flat cells" Are known. An example of such a cell is shown in FIG. 1a. In this figure, the top of the semiconductor substrate 10 is Six cells 01 to C6 are densely arranged. Figures 1b and 10 represent Figure 1a, respectively. FIG. 2 is a cross-sectional view taken along lines 1b-1b and 1c-1c. inside the semiconductor substrate 10 What is formed are a plurality of parallel diffused N1 bit lines 12. multiple A channel region 14 is formed between the bit lines 12 . various dough By doping the channel region 14 with a punt concentration, the ROM code can be modified. It can be decided in advance. For example, an ion implantation process can The channel region 14 is doped with a certain P+ ion implant. This allows you to Thus, the threshold voltage of the MOSFET formed on the channel region 14 can be increased.

A MOFSET with a high threshold voltage stores, for example, a logical bit "1". . Formed on the insulating layer 16 are a plurality of polysilicon word lines 18. be. The word line 18 is above the bit line 12, substantially perpendicular thereto, and has a voltage placed in a physically insulated manner. Beyond the channel region 14 is a P-insulator. The region 2o forms an individual ROM (R). FIG. 2 is a schematic diagram of an OM cell. -It may seem simple, but such a ROM cell is In practice, very complex addressing and decoding circuits are required. So Second, a very sensitive sense amplifier is also required to read the memory. child An example of a ROM circuit of this type was presented at the VLS held in Tokyo on August 22-230, 1988. 1 Circuit Symposium, co-authored by Okada et al. r16Mb ROM DesignUsing Excerpt from the technical document titled “Bank 5elect Architecture” No. 5,117,389, p. 85-86 or Yiu U.S. Pat. Name rFlat-Cell Read-Only Memory Integr ated C1rcuit” published on May 26, 1992. .

Disclosure of invention According to this invention, a small size, high-speed random access, and complex addressing are possible. , decoding, and current sensing circuit-independent 10M cells. Ru.

The ROM cell of this invention achieves these objectives through its unique design.

Generally speaking, the ROM cell of the present invention has a source and a train formed in a semiconductor substrate. It will be. A channel is formed between the source and drain. The channel is that The subsequently formed MOSFET is doped to a predetermined threshold voltage level. is being logged. The predetermined threshold voltage level may be, for example, the logical bit rl' or Corresponds to "o". electrically insulated and formed over the first portion of the channel. The first control gate is the first control gate. Also formed in the second part of the channel This is the second control gate. In a preferred embodiment, the first and second control gates are Polysilicon layers are arranged on a semiconductor substrate at substantially right angles to each other. . Isolation between cells is provided by diffusion isolation regions, field-forming oxide regions, and oxide trenches.

In the field of application, the ROM cells of the present invention are typically arranged in rows and columns on a semiconductor substrate. Arranged in a matrix. Each memo in the row direction 1) +! The first control gate of the The ports are connected to each other to form a YIIilJ control line. Similarly, each column The first control gates of each memory cell are connected to each other to form an X control line.

Addressing each ROM cell of the matrix requires a complex addressing method. No circuit is required. To select a specific ROM cell during a read operation, cross Activate the X and Y control line pair simultaneously to turn on the channel below it. R.O. The threshold voltage of the MOSFET in the M cell causes current to flow from source to drain. is applied to a sense amplifier to determine the appropriate logic level. X is Y system All other ROM cells with only one side of the control line active are connected to the channel below it. is not fully turned on and cannot be used for read operations.

Brief description of the drawing Figure 1a shows a conventional read-only memory cell commonly called a “flat cell.” A plan view showing the Figure 1b is a cross-sectional view of Figure 1a taken along line 1b-1b; Figure 1c is a cross-sectional view of Figure 1a taken along line 1b; Cross-sectional view taken along line c-1c; Figure 2 shows the read-only memory cell shown in Figures 1a-1c. FIG. 3a shows a preferred embodiment of the read-only memory cell of the present invention. Figure 3b is a cross-sectional view of Figure 3a taken along line 3b-3b; Figure 30 is Figure 3a A cross-sectional view taken along line 3cm3c; Figure 4 is a schematic diagram of a read-only memory cell. ; FIG. 5a shows memory cells arranged in a matrix of rows and columns as shown in FIGS. 3a-3c. FIG. 5b is a top view of a portion of the memory array of the present invention; A cross-sectional view taken along line 5b-5b; Figure 50 is a cross-sectional view taken along line 5cm5c of Figure 5a. Figures; Figure 6 is a schematic diagram of the memory array shown in Figures 5a-5c; Figures 7a-7b are diagrams of Figures 3a-3. A process diagram of each manufacturing stage of the memory cell shown in c; Cross-sectional view of a read-only memory cell with a channel consisting of an interface-forming oxide layer; Figure 9a shows another memo with an intermediate layer that uses predefined patterns to realize the ROM code. Plan view of rear array; 9b is a cross-sectional view of FIG. 9a taken along line 9b-9b; FIG. 90 is a cross-sectional view of FIG. Cross-sectional view taken at cm9c; Figure 10a was arranged exactly the same as the adjacent cell. A top view of another memory array with each memory cell in the array; Figure 10b is a cross-sectional view of Figure 10a taken along line 10b-10b; Reference numeral 9 indicates a first embodiment of the invention. Figure 3a shows the ROM FIG. 3b and 30, on the other hand, connect FIG. 3a to line 3b-3, respectively. FIG. In this embodiment, for example, a P-type half Formed inside the conductive substrate 31 are an N-type source 32 and a drain 33. There is a channel 34 between them. Semiconductor at source 6, drain 8, and channel 10 A basic MOSFET II is configured in the body substrate 4 t7. Functionally, cha The channel 34 is divided into a first portion 34A and a second portion 34B. channel 34 A first control gate 36 is electrically insulated from one portion 34Δ.

electrically isolated over the first control gate 36 and the second portion 34B of the channel 34. There is a second control gate 39. Different games can be achieved by several insulation layers. The conductor board 31 is electrically insulated from the conductor board 31. In this example, the insulating layer It is grown silicon dioxide (SiO+). For example, the first control game An insulating layer 35 is formed between the groove 36 and the first portion 34^ of the channel 34. be. On the other hand, JFg is formed between the first control gate 3G and the second control gate 39. It is the insulating layer 30. Furthermore, the second control gate 39 and the second Insulating layer 38 is formed between portions 34B.

In this embodiment, the first control gate 36 and the second control gate 39 are elongated semiconductor gates. The two electrodes are electrically insulated and arranged substantially orthogonally to each other on the negative side of the body substrate 31. . This configuration is shown in Figure 3a. Also, doped into the semiconductor substrate for cell insulation. There is also an insulating region 40 that has been removed. In this embodiment, insulating region 40 is a P-type diffusion region. area. Alternatively, the insulating region 40 may be made of an insulating material such as silicon dioxide. It is possible to form the

FIG. 4 shows a schematic diagram of the memory cell 9. For clarity, the inside of memory cell 9 is MOSFET II is divided into two transistors IIA and IIB. In Figure 3b The same parts are shown in curly brackets. Here node 43 is connected to the first part of channel 34. This is a hypothetical point between the minute 34A and the second portion 34B. clearly shown in the diagram As such, transistor IIA is controlled by second control gate 39A, while transistor IIA is controlled by second control gate 39A; Transistor IIB is controlled by a first control gate 36. transistor 11 ^ and IIB indicate that the first control gate 36 and the second control gate 39 are activated at the same time. It turns on. In order to make the explanation simple and accurate, in the explanation and additional claims, "simultaneous The term "at the same time" or "simultaneously" means that one or more events occur simultaneously. do. Therefore, in this case, it is stated that two control gates are activated simultaneously. The timing of activation of the control gate may be different when Shicala However, there is always time to activate both control gates redundantly.

Next, the read operation of the memory cell 9 will be explained below. First, the selected memory It is necessary to activate the first control gate 36 and the second control gate 39 of the circuit 39 to 3V. Ru. The drain is set to 3■, and the source is at the same level as the ground potential. Ru. Positively charged ions are implanted into some or all of the channel 34 in advance. As a result, the threshold voltage of MOSFET II is programmed in advance. It becomes the value of +5■.

The potential of 3V applied to the first and second control gates 36 and 39 is applied to the MOSFET II exceeding the threshold voltage of +5.times. is insufficient to turn on channel 34.

When channel 34 is off, current flows from drain 33 to source 32. This means that, for example, bit r□ has been read out. But choose The threshold voltage of MOSFET II of memory cell 9 is programmed in advance. In the case of +1v, the potential of 3v is greater than the threshold voltage of MOSFET II +1v. is applied to control gates 36 and 39, turning channel 34 on. Therefore, A current flows from the drain 33 to the source 32, which means that, for example, when bit “1” is read, It will happen.

Again, the selected memory cell is activated only when both control gates 36 and 39 are activated. 9 can be addressed for read operations. All other memory cells also , cannot be addressed simply by activating either control gate. The reason for this is The first portion of the channel 34, regardless of the threshold voltage of the Morisel MOSFET. This is because one of the second portion 34A and the second portion 34B is turned off. this This feature is particularly useful when the ROM cells of this invention are arranged in a matrix. Ru. Figures 5a-5c show such matrix arrangements. Multiple memories in Figure 5a FIG. 3 shows a top view of a portion of a memory array including cells C1-C8. Each memory cell in the column direction The first control gates of the lines are connected to each other to form a first control line 37. similar The second control gates of each memory cell in the row direction are connected to each other and connected to a second control line 4. 1 is formed. Figures 5b and 50 show Figure 5a at lines 5b-5b and 5cm5c. A cut sectional view is shown. FIG. 6 is a schematic diagram of the memory array shown in FIG. 5a.

7a and 70 are process diagrams at each stage of manufacturing the memory cell 9. FIG. First By selectively oxidizing the surface of the P-type silicon substrate 31, a thickness of about 20 nanometers is formed. It is used as an insulating film for the data. A polysilicon layer is then deposited over the insulating film and further , doped to form a 4Ω resistance. The formation of the first control gate 36 is performed using conventional methods. It uses masking and etching techniques. The other insulating layer 30 has a first control gate. A film is formed on the sheet 36. The structure formed through the steps up to this point is shown in FIG. 7a.

Conventional masking and ion implantation methods are used to form the source 32 and drain 33. used. To achieve more complete isolation between cells, another ion implantation is performed as shown in Figure 3c. A P-type insulating region 4o must be formed through a process. After that, about 450 na depositing a second layer of polysilicon with a thickness of 100 mm on the semiconductor substrate 31; . The deposited polysilicon layer is then doped to form a 4Ω resistor. again , masking and etching the formed polysilicon film using conventional methods. A second control line 39 is formed. The structure formed through the steps up to this point is shown in FIG. 7b.

Note that the material used to form the first and second control gates is not polysilicon. Should. For example, metals such as aluminum, tungsten silicide, and It is a soluble silicon-based compound such as tanim silicide.

Finally, it is possible to make some modifications within the scope of the invention. For example, Figure 3 The ion implanted insulating regions 40 shown in C and 5C can be replaced with insulating oxide film regions.

The oxide insulating layer 30 shown in FIGS. 3b and 3C17a is a composite layer of oxide-nitride monoxide. It can be replaced with

The shapes and sizes of the first control gate 36 and the second control gate 39 are different. favorable fruit Instead of the ion implantation formed channel described in the example, the channel shown in FIG. ROM code with or without field forming oxide region 81 over 34 can be created. Moreover, the first control line 37 and the second control line 41 shown in FIGS. 9a-9c A ROM code can be created by sandwiching an intermediate polysilicon layer 80 between them. Figure 9 a is a plan view showing the above arrangement, and FIGS. 9b and 90 show FIG. 9a along line 9b-9 They are cross-sectional views taken at lines b and 9cm9c, respectively. The intermediate layer 8° is connected to the ground potential. Continued. A memory cell with an intermediate layer 8o overlapping the channel portion is a digital Data “0” is stored. On the other hand, memory cells without intermediate layer 8o are digital Data “1” is stored. More specifically, as shown schematically in Figure 9b, Cell D6 stores digital bit “1” and other cells store digital data “o”. I have paid.

Another embodiment of the invention is shown in FIG. 10a and Job. In the memory cell array, Unlike cells that are arranged horizontally opposite to adjacent cells, cells that are the same as adjacent cells in the memory array is located. In the common diffusion region 32/22, the source region 32 is the drain region. It can be used for any of 33, and can be replaced. Figure 10a shows this arrangement. A plan view is shown in FIG. 10b, and a sectional view taken along the line Job-10b in FIG. 10a is shown.

The invention has been described in terms of preferred embodiments. Changes in shape and details may be requested It is possible for a person skilled in the art to carry out the invention without departing from the scope and spirit of the invention as described in the scope of I understand that it is possible.

Figure 7b Fish box - → Thin sleeve

Claims (13)

[Claims] 1. A read-only memory cell that has a drain and is formed on a semiconductor substrate. and: a first portion and a second portion having a predetermined conductivity disposed between the source and the drain; channel; a first control gate electrically insulated over the first portion of the channel; a second control gate electrically insulated above the second portion of the channel; The channel with electric current constitutes the information storage device of the ROM, and and the second control gate are simultaneously activated. read-only memory cells spaced apart from the source. 2. The first and second control gates are elongated and electrically insulated on the semiconductor substrate. 2. The lead optics of claim 1, wherein the lead optics are arranged substantially perpendicularly to each other. memory cell. 3. 5. The channel further comprises implanted ions having a predetermined conductivity. 1. The read-only memory cell according to 1. 4. 2. The channel of claim 1, wherein the channel further comprises a field-forming oxide region. Read-only memory cell. 5. The method of claim 1-4, wherein the first and second control gates are made of polysilicon. The read-only memory cell described in any of the above. 6. Any one of claims 1-4, wherein the first and second control gates are made of metal. The read-only memory cell described. 7. 2. The first and second control gates are comprised of a soluble silicon compound. -4. The read-only memory cell according to any one of 4. 8. Memory formed on a semiconductor substrate that includes multiple read-only memory cells In the cell array, A source formed on a semiconductor substrate; A drain formed on a semiconductor substrate apart from the source; an electrically insulating arrangement in a first portion of said channel; a first control gate electrically insulated over the second portion of the channel; the plurality of read-only memory cells are arranged in rows and columns; arranged in a matrix on a semiconductor substrate, each second control in the row direction of the matrix; The control gates are electrically connected to each other, and each first control gate in the column direction of the matrix The ports are electrically connected to each other, thereby controlling the selected first and second controls. When the gate pairs are simultaneously activated to a predetermined potential value, each read-only memory Selective reading from the cell becomes possible. 9. further comprising an intermediate layer disposed between the first and second control gates; The intermediate layer constitutes a read-only memory code of the memory cell array. The memory cell array of claim 1, comprising a predetermined pattern. 10. Furthermore, an insulating region disposed between the read-only memory cells The memory cell array according to claim 8. 11. Prepare a semiconductor substrate; Implanting ions into a semiconductor substrate to form a channel with a predetermined conductivity; forming a first control gate electrically insulated from a first portion of the first control gate; forming a second control gate electrically isolated from the gate and the second portion of the channel; , a method for forming a read-only memory cell on a semiconductor substrate, comprising the steps of: 12. Before the second control gate forming step, a source and a drain are formed in the semiconductor substrate. 12. The read-only memory cell form of claim 11, further comprising the step of forming a read-only memory cell. How to create. 13. The second control gate is disposed substantially directly on the semiconductor substrate with the first control gate. The read-only device according to claim 11 or 12, wherein the read-only device is formed to intersect with each other. How to form memory cells.