JPH1022481A - Read-only semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a read-only semiconductor storage device with high speed and high reliability by using an almost final wiring process for data write in consideration of a fault which requires a long time for a manufacturing process after writing because of using a width of a gate insulating film of a MOSFET and ion implantation as a means of data writing in a conventional ROM(read-only memory). SOLUTION: This device consists of N<+> well region 2 formed between a plurality of gate electrodes 4 and at both ends of the arrays thereof and contact holes 6, 10, 11 provided on the interlayer insulating film 5, 8, 9 thereon and elements with metal electrodes 7, 12, 13 formed on the contact holes so as to reach the uppermost layers of the interlayer insulating films. Writing in this element is performed by mutually connecting a pair of adjacent metal electrodes in the uppermost layers of the interlayer insulating films. A NAND type read-only semiconductor storage device can be constituted by using a plurality of above elements.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a read-only semiconductor memory device, and more particularly to a device for writing data using a wiring pattern.

[0002]

2. Description of the Related Art A conventional read-only semiconductor memory device (R)
There are OM (Read Only Memory) in which data can be electrically written and data in which data is written using a mask pattern in a manufacturing process such as a mask ROM.

[0003] As an electrically writable device, for example, a device that blows a fuse and a device that breaks a junction are known. In recent years, electrical writing using electron injection and emission phenomena into the polysilicon floating gate and the interface state of the nitride film / oxide film and electrical or ultraviolet /
ROMs that can be erased by X-rays or the like have come to be used. However, these ROMs do not always satisfy the demands of users in terms of reliability, and have been problematic.

On the other hand, a mask ROM is manufactured by a method of controlling the thickness of a gate insulating film of a MOSFET constituting the ROM and the presence / absence of ion implantation just below the gate by a mask pattern according to write data. Since the method of manufacturing a mask ROM is based on a combination of steps usually used for an integrated circuit, there is no problem in reliability.

However, the data written in the ROM is usually different for each user, and in order to supply a mask ROM corresponding to this, as described above, the threshold value of the MOSFET is controlled by etching the gate insulating film or ion implantation. Since it is necessary to respond to the individual specifications for each user, the turnaround time from order receipt to product supply is long, and it is possible to sufficiently respond to the user's request for promptly writing the necessary information. Did not.

[0006]

As described above, in the conventional ROMs, those with easy data writing have low reliability, and those with high reliability such as mask ROMs have the following disadvantages.
There is a problem that it takes a long time to write data.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and describes steps located upstream of a manufacturing process, such as the thickness of a gate insulating film and ion implantation related to the threshold value of a MOSFET. Avoid using it for writing,
An attempt is made to reduce the turnaround time of the writing by using a step near the end of the manufacturing process as much as possible for information writing.

[0008]

A read-only semiconductor memory device according to the present invention comprises a plurality of gate electrodes formed on a semiconductor substrate of a first conductivity type with a thin gate insulating film interposed therebetween and between and between the plurality of gate electrodes. A second conductivity type well region formed at both ends of the column, at least one interlayer insulating film formed on the gate electrode and the well region, and a contact reaching the well region provided in the interlayer insulating film on the well region An ohmic contact is formed in the well region through the contact hole, and a metal electrode is formed so as to reach an uppermost layer of the at least one interlayer insulating film, and at least one pair of the metal electrodes is adjacent to each other The metal electrode is formed of elements connected to each other by a final wiring layer on the uppermost layer of the interlayer insulating film. The fact that the adjacent metal electrodes are connected to each other by the final wiring layer in the uppermost layer of the interlayer insulating film is defined as the data write state of the read-only semiconductor memory device.

A read-only semiconductor memory device according to the present invention comprises:
A NAND type circuit is constituted by using a plurality of the elements. At this time, the plurality of gate electrodes formed on the semiconductor substrate of the first conductivity type via a thin gate insulating film, and wells of the second conductivity type formed between the plurality of gate electrodes and at both ends of the column. The plurality of MOSFETs constituted by the regions are all enhancement type.

[0010] Further, among the plurality of MOSFETs, one in which at least a gate electrode is connected to a select line of an element constituting a read-only semiconductor memory device may be an enhancement type.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows the first embodiment of the present invention.
14 is a schematic diagram showing a cross-sectional structure of an element constituting the read-only semiconductor memory device according to the embodiment. A thin thermal oxide film 3 serving as a gate oxide film of a MOSFET is formed on a P-type silicon substrate, and ions are implanted for controlling a threshold voltage so that the MOSFET becomes an enhancement type.

Next, a polysilicon layer is deposited on the entire surface by the CVD method. The polysilicon is patterned using the resist as a mask, and the row of the gate electrodes 4 of the MOSFET is shown in FIG.
As shown in FIG. At this stage, the gate oxide film 3 is not etched and covers the entire surface of the silicon substrate 1.

Subsequently, the entire surface is covered with a resist, and patterning is performed to expose the region where the polysilicon gate electrode row is formed. Using the row of the resist and the polysilicon gate electrode 4 as a mask, the gate insulating film 3 is passed through the gate insulating film 3.
Is ion-implanted. Thereafter, through a heat treatment step for activating the implanted As, the N ⁺ -type (N ⁺ indicates high-concentration N-type) well region 2 which becomes the source / drain of the MOSFET in a self-aligned manner is formed. It is formed between and at both ends of the gate electrode row.

Here, a region 2 serving as a source or a drain
Unlike a normal individual MOSFET, as shown in FIG. 1, the MOSFET is configured to share a source and a drain between adjacent MOSFETs. In the process of ion implantation into the N ⁺ -type well region 2, A
s is implanted at a high concentration to form an N ⁺ -type conductive polysilicon gate 4.

In the above description, the step of simultaneously implanting ions into the well region 2 and the polysilicon gate 4 has been described. However, after depositing N ⁺ polysilicon with a high concentration of donor by CVD, patterning is performed. To form an array of conductive gate electrodes of polysilicon,
The implantation or diffusion of the donor into the drain region may be performed as a separate step. Although the case where As is used as the donor impurity has been described, another kind of donor impurity such as P may be used.

Next, a first interlayer insulating film 5 made of a silicon oxide film is deposited by a CVD method, and the gate oxide film 3 is formed.
Then, after forming a contact hole 6 reaching the well region 2 through the first interlayer insulating film 5, aluminum is deposited by a sputtering method, and a first layer aluminum electrode 7 is formed by patterning.

Subsequently, a second interlayer insulating film 8 is deposited, and a contact hole 10 reaching the aluminum electrode 7 of the first layer is formed.
After forming, aluminum is deposited using a sputtering method,
The second layer aluminum electrode 12 is formed by patterning and connected to the lower layer aluminum electrode 7.

Finally, a third interlayer insulating film 9 is deposited, and a contact hole 11 reaching the aluminum electrode 10 of the second layer is formed.
After forming, aluminum is deposited using a sputtering method,
The third layer aluminum electrode 13 is formed by patterning and connected to the lower layer aluminum electrode 12.

In the element shown in FIG. 1, the third layer is the uppermost aluminum wiring layer, but an element having three or more layers can be formed in the same manner. The main point of the present invention is to connect adjacent N ⁺ wells formed on a silicon substrate using an uppermost aluminum wiring layer as shown in FIG. To write data to the memory.

In a conventional mask ROM, data is written by using a change in the thickness of a gate insulating film or a change in the threshold value of a MOSFET due to ion implantation. Although it took a long time, if data is written in the uppermost wiring step near the end, the time required for writing can be greatly reduced because the manufacturing process after writing is short.

Note that reference numeral 15 in FIG. 1 indicates a lead line from the element. Leader lines are used for interconnection between elements when a large-scale read-only semiconductor memory device is configured using a plurality of elements shown in FIG. Such lead lines are not necessarily drawn from the electrodes at both ends of the uppermost layer, but may be drawn from the aluminum electrodes provided on each layer from the first layer to the uppermost layer in a direction perpendicular to the cross section of the drawing. it can.

FIG. 2 shows an equivalent circuit when this element is used in a read-only semiconductor memory device in order to clarify the connection relationship between the electrodes shown in FIG. 2 correspond to FIG. 1 respectively. Reference numeral 14 in FIG. 2 shows a situation in which data is written by short-circuiting the source and drain of the MOSFET. A word line is connected to each gate electrode, but the word line is not shown in the sectional view of FIG.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 3 is a diagram showing an equivalent circuit when a NAND-type read-only semiconductor memory device is formed using the elements described in the first embodiment. FIG. 3 shows the four elements shown in the first embodiment.
It is arranged above and below the connection line with the central data line. Note that the MOSFETs shown here are all of the enhancement type as described above.

An element selecting MOSFE connected to a selecting line
T16 to T19 are off unless a positive selection signal is input to the gate. The other MOSFETs 20 to 23 in the region where the selection line runs (selection region) are always in a conductive state because the source and the drain are connected as shown in FIG.

When a positive selection signal is input to the selection line, one of the four elements is selected. For example, MOSFE for element selection
It is assumed that a signal voltage is applied to T17 and an element surrounded by a broken line in FIG. 3 is selected. Reading of data from the element is performed as follows.

As shown in the figure, one end of the element is grounded, a read voltage is applied to the data line, the word line is addressed, for example, the gate of the MOSFET 24 constituting the element is set to 0 V, +5
V. At this time, since no read current is generated in the data line, it is understood that the source and drain of the addressed MOSFET 24 are not short-circuited (data is not written).

If a read current flows through the data line even when the address signal voltage is applied to the word line, the source and drain of the addressed MOSFET are short-circuited, for example, 25, that is, data is written. It turns out that it is in a state.

The data read current is controlled by the MOS in the device.
It is read out to the data line through the series resistance of the FET,
In some of these MOSFETs, since the source and drain are short-circuited by the data writing of the present invention, the sum of the series resistances is small as a whole, so that high-speed reading can be performed as compared with the related art.

The present invention is not limited to the above embodiment. For example, data writing using the uppermost layer wiring may be performed by forming a connection mask pattern, or may be performed by maskless connection using a metal beam deposition method. Alternatively, a method may be adopted in which all adjacent wells are connected in advance and fusing is performed later, or unnecessary portions are removed by laser processing. The wiring material does not necessarily have to be aluminum, and for example, a laminated structure of titanium / aluminum or an alloy such as aluminum / silicon can be used.

In the above embodiment, the case where all the MOSFETs constituting the element are of the enhancement type has been described, but the MOSF whose gate is connected to the selection line is described.
Even if only the ET is of the enhancement type and all others are of the depletion type, the same function can be obtained by inverting the address signal. In addition, various modifications can be made without departing from the scope of the present invention.

[0031]

As described above, according to the present invention, unlike a conventional mask ROM, steps located upstream of the manufacturing process, such as the thickness of a gate insulating film of a MOSFET and ion implantation, are not used for information writing. In addition, by performing information writing using a wiring process near the end, a write-around time can be reduced, and a high-speed and highly reliable read-only semiconductor memory device can be obtained.

[Brief description of the drawings]

FIG. 1 is a view showing a cross-sectional structure of an element according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an equivalent circuit of the element according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a circuit configuration of a NAND-type read-only semiconductor memory device according to a second embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... P type silicon substrate 2 ... N ⁺ type well region 3 ... Gate oxide film 4 ... Polysilicon gate electrode 5,8,9 ... Interlayer insulating film 6,10,11 ... Contact hole formed in interlayer insulating film 7,12 , 13 ... aluminum electrode provided on the N ⁺ type well region 14 ... aluminum wiring for writing data 15 ... aluminum lead 16, 16, 18, 19 ... enhancement type MOSFET for element selection 20, 21, 22, 23 ... selection MOSFET in which the source / drain is short-circuited in the region 24 ... Enhancement-type MOSFET in which no data is written 25 ... Enhancement-type MOSFET in which data is written by short-circuiting the source / drain

Claims (5)

[Claims] 1. A plurality of gate electrodes formed on a semiconductor substrate of a first conductivity type via a thin gate insulating film; and a second conductivity type formed between the plurality of gate electrodes and at both ends of a column thereof. A well region, at least one interlayer insulating film formed on the gate electrode and the well region, a contact hole reaching the well region provided in the interlayer insulating film on the well region, and the contact hole And a metal electrode formed so as to reach an uppermost layer of the at least one interlayer insulating film, and at least one pair of adjacent metal electrodes of the metal electrodes A read-only half comprising at least one element connected to each other by a final wiring layer in an uppermost layer of the interlayer insulating film. Body storage device. 2. The method according to claim 1, wherein at least one pair of adjacent metal electrodes of the metal electrodes is formed in an uppermost layer of the interlayer insulating film.
2. The semiconductor device according to claim 1, wherein said at least one device is connected to the last wiring layer and has a data write state.
13. The read-only semiconductor memory device according to claim 1. 3. The method according to claim 1, further comprising:
3. The read-only semiconductor memory device according to claim 1, wherein the read-only semiconductor memory device has a D-type configuration. 4. A plurality of gate electrodes formed on the semiconductor substrate of the first conductivity type via a thin gate insulating film, and second gate electrodes formed between the plurality of gate electrodes and at both ends of the column. 4. The read-only semiconductor memory device according to claim 3, wherein all of the plurality of MOSFETs formed by the conductive well regions are enhancement type. 5. A plurality of gate electrodes formed on the semiconductor substrate of the first conductivity type via a thin gate insulating film, and second conductive films formed between the plurality of gate electrodes and at both ends of the column. MOS composed of well regions
4. The read-only semiconductor memory device according to claim 3, wherein in the FET, at least a MOSFET whose gate electrode is connected to a selection line of the element constituting the read-only semiconductor memory device is an enhancement type.