JP3253583B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for miniaturizing a semiconductor device having a logic circuit section and a mask ROM (Read Only Memory) section on the same semiconductor substrate. About the method.

[0002]

2. Description of the Related Art A mask ROM is a semiconductor device for writing a program by implanting impurity ions into predetermined regions of memory cell transistors arranged in a matrix. Various techniques for performing ion implantation for writing are known. Figure 8 below
A conventional manufacturing method will be described with reference to FIG. Step 1: As shown in FIG. 8A, a p-type semiconductor substrate 51
A pad oxide film 52 made of a silicon oxide film is formed to a thickness of 500.degree. By using thermal oxidation or CVD. The pad oxide film 52 is formed for the purpose of protecting the surface of the semiconductor substrate 51. Next, a silicon nitride film 53, which is an oxidation-resistant film, is formed on the entire surface. Thereafter, a strip-shaped opening 53a long in a direction perpendicular to the paper surface for forming an element isolation film 54 is formed in the silicon nitride film 53. . Step 2: As shown in FIG. 8B, the silicon nitride film 53
The semiconductor substrate 51 is oxidized using the LOCOS method using the mask as a mask to form an element isolation film 54. At this time, an oxidized region penetrates between the semiconductor substrate 51 and the silicon nitride film 53 to form a bird's beak 54a. Next, the silicon nitride film 53 and the pad oxide film 52 are removed, and a gate insulating film 55 is formed to a thickness of 140 ° to 170 ° using a thermal oxidation method.
Next, a polysilicon film is formed to a thickness of 2500 ° by the CVD method, and is doped with phosphorus to form an n-type conductive film 56. Step 3: As shown in FIG. 8C, the conductive film 56 is etched to form a gate electrode 56a in a strip shape long in a direction intersecting with the element isolation film 54 (however, the etching region is parallel to the paper surface). (Not shown). Next, p-type ions such as boron are implanted using the gate electrode 56a as a mask to form a source region and a drain region. (The source region and the drain region are formed below both ends of the gate electrode in a direction perpendicular to the plane of the drawing. It has not been). Thus, memory cell transistors arranged in a matrix are formed. Next, an interlayer insulating film 57 made of SiO2 is formed on the entire surface to a thickness of 6000.degree. Next, a strip-shaped Al wiring 58 long in a direction perpendicular to the plane of the paper as a bit line is formed above the element isolation film 54. Up to this point, the semiconductor device can be manufactured regardless of what kind of program is written in the memory cell transistor, so that a wafer can be prepared. Note that, in the case of performing the fabrication, a silicon oxide film 59 is formed on the entire surface as a protective film. Step 4: Upon receiving a request from the customer and determining the program to be written, as shown in FIG.
Photomask 60 having opening 60a for OM writing
To form Next, a predetermined memory cell transistor is depleted by ion-implanting a p-type impurity such as boron into the semiconductor substrate 51 directly below the gate electrode 56a from the opening. As a result, the threshold voltage of the memory cell transistor is reduced, and ROM data is written.

[0003]

However, generally, the processing accuracy of the above photoresist is low, for example, 0.5 μm
It is about. Therefore, when the opening 60a is formed in the photoresist, a variation of 0.5 μm occurs. Further, as described above, the bird's beak 54a is formed in the element isolation film 54, and the end of the element isolation film 54 is thin. Therefore, when the variation of the opening 60a occurs, the impurity ions are implanted. Then, as shown in FIG. 9, impurity ions are implanted through the bird's beak 54a to the semiconductor substrate 51 below the element isolation film 54 surrounded by a circle A in the figure. When such elements are adjacent to each other, a leak current that passes under the element isolation film 54 indicated by an arrow is generated between the adjacent elements, which causes an element isolation failure.
Further, improving the processing accuracy of the photomask has led to a significant increase in cost.

In addition, since ion implantation for writing data is performed through the interlayer insulating film, the gate electrode, and the gate insulating film, it is necessary to perform the ion implantation at a high energy of about 1 MeV to 3 MeV. When ion implantation is performed with high energy, the diffusion of the implanted ions in the lateral direction increases, which also leads to the above-described element isolation failure. In addition, an apparatus for performing ion implantation with such high energy is generally expensive, leading to an increase in cost.

[0005] From the above factors, it is necessary to design the element isolation film to have a sufficient margin to prevent the element isolation failure and to design the element isolation film to have a width larger than the processing limit, which leads to an increase in the cell size. . In the mask ROM described above, a logic unit for controlling the memory unit is usually formed around the memory unit. Forming the logic part and the memory part separately causes an increase in the number of steps, and has been a problem from the viewpoint of cost reduction and TAT reduction.

[0006]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and generally has a processing accuracy of metal wiring of, for example, 0.1.
Utilizing the fact that it is 1 μm, which is higher than the processing accuracy of the photomask of 0.5 μm, and using this as a mask for ion implantation, miniaturization of the element is achieved. Further, by forming the memory unit at the same time as the formation of the logic unit, the cost and the TAT can be reduced.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIG.
An embodiment will be described. The present embodiment is a method for manufacturing a semiconductor device having a logic portion constituted by two-layer aluminum alloy wiring. Step 1: As shown in FIG. 1A, a pad oxide film 2 is formed on a semiconductor substrate 1 and a silicon nitride film 3 having an opening is formed in the same manner as Step 1 of the conventional manufacturing process. Step 2: As shown in FIG. 1B, the surface of the semiconductor substrate 1 is oxidized by the LOCOS method using the silicon nitride film 3 formed on the semiconductor substrate 1 as a mask to form an element isolation film 4. Next, the pad oxide film 2 and the silicon nitride film 3 are removed, the gate insulating film 5 is formed to a thickness of 140 ° to 170 ° using a thermal oxidation method, and the polysilicon film is
Then, an n-type conductive film 6 is formed by doping impurities such as phosphorus. Next, a silicide film 7 of a refractory metal such as tungsten is formed at 1500 °. The silicide film 7 becomes a gate electrode together with the conductive film 6, and not only reduces the electric resistance of the gate electrode, but also has a function of protecting the gate electrode as described later. Step 3: As shown in FIG. 1C, the conductive film 6 and the silicide film 7 are etched to form a gate electrode 8 in a strip shape long in a direction intersecting with the element isolation film 4 (however, the etching region is a paper surface). , Which are not shown in the drawing). Next, p-type ions such as boron are implanted using the gate electrode 8 as a mask to form a source region and a drain region. Not shown). Thus, memory cell transistors arranged in a matrix are formed. Next, an interlayer insulating film 9 of BPSG is formed on the entire surface to a thickness of 6000 mm.
Formed. Next, a first metal film made of an Al alloy is formed on the entire surface, and the first metal film is etched to form a first wiring of an arbitrary shape in a region on the interlayer insulating film 9 where the memory cell transistor is not formed. Form 10. In each of the drawings showing the manufacturing process of this embodiment, that is, in FIGS. 1 to 4, the left area shown in FIG. 1C is a logic section, and the right area is a ROM section. Step 4: As shown in FIG. 2A, an interlayer insulating film 11 made of SiO2 is formed on the entire surface to a thickness of 6000.degree. Next, a photoresist is applied to the entire surface to form a photomask 12 having an opening above the contact formation region of the first wiring of the interlayer insulating film and over the entire surface of the region where the memory cell transistor is formed. Step 5: As shown in FIG. 2B, the interlayer insulating film 11 is etched using the photomask 12 as a mask to form a contact hole 13 and expose the BPSG interlayer insulating film 9 above the memory cell transistor. At this time, since the selectivity of the BPSG interlayer insulating film 9 to the interlayer insulating film 11 is small,
Etched about 3500Å. Step 6: As shown in FIG. 2C, a second metal film made of an Al alloy is formed on the entire surface. Next, this is etched to form a logic part second wiring 14 of an arbitrary shape connected to the first wiring 10 via a contact hole. At the same time, the bit line 15 of the memory cell transistor is formed. The bit line 15 extends in a direction perpendicular to the plane of the drawing, and its end is located above the end of the element isolation film 4. Up to this point, since the semiconductor device can be manufactured regardless of what kind of program is written in the memory cell transistor, a wafer can be prepared. In the case of making a reservoir, a protective film 16 of a thin silicon oxide film of about 500 ° is formed on the surface in order to protect the metal wiring layer and prevent corrosion. Step 7: Upon receiving a request from a customer, when a program to be written is determined, as shown in FIG. 3A, a photoresist is formed on the entire surface to about 10,000 °, exposed and developed, and exposed above a predetermined memory cell. A photomask 17 is formed by providing an opening in the region of FIG. Step 8: The protective film 16 is etched using the photomask 17 as a mask to expose the BPSG interlayer insulating film 9 and the end 15a of the bit line 15. At this time, as in step 5, the BPSG interlayer insulating film 9 is also etched, but the gate electrode is not damaged if the interlayer insulating film 9 is left at least 1000 ° from the upper surface of the gate electrode 8. In addition, by etching the BPSG interlayer insulating film 9, the energy at the time of performing the ion implantation in the step 8 can be reduced. Therefore, in step 5 and this step, the BPSG interlayer insulating film 9 may be positively etched. Step 8: As shown in FIG. 3B, a predetermined memory cell transistor is depleted by ion-implanting a p-type impurity such as boron into the semiconductor substrate 1 directly below the gate electrode 8 through the opening. As described above, since the end of the bit line 15 is formed immediately above the end of the element isolation film 4, more precise ion implantation can be performed by using this as a mask. As a result, the threshold voltage of the memory cell transistor is reduced, and ROM data is written. Here, the ion implantation energy can be performed at a low energy of about 130 keV to 160 keV because the interlayer insulating film 9 is etched. Therefore, the diffusion of the implanted ions in the horizontal direction can be prevented, and more precise ion implantation can be performed. Further, since the interlayer insulating film 9 of at least 1000 ° remains, even if an etching error occurs, the insulation of the gate electrode 8 is not broken. Also, even if the etching is too much and the interlayer insulating film 9 does not remain, the silicide film 7 formed on the gate electrode 8 functions as an etching stopper, so that the gate electrode 8 is not likely to be damaged. . Step 9: As shown in FIG. 3C, the photomask 17 is removed, and then a protective film 18 is formed entirely.

As described above, a mask ROM in which a program having a logic section is written can be formed. Step 3
At this time, as shown in FIG.
Between the first wiring layer 10 and SiO2 such as polysilicon.
The etching stopper 19 made of an insulator having a large selection ratio may be formed. Etching stopper 19 thickness
By forming it at about 300 °, the BPSG interlayer insulating film 9 can be prevented from being etched in the step 5 or the step 7, so that the gate electrode 8 can be prevented from being damaged. However, on the other hand, the film thickness at the time of performing the ion implantation for writing the program in the step 7 becomes large, so that it becomes necessary to increase the energy of the implanted ions.

In step 3, as shown in FIG. 4 (b), the BPSG interlayer insulating film 9a is
To 2000 mm, and etch stopper 20 to a thickness of 300
Then, an interlayer insulating film 9b made of BPSG or SiO2 may be formed. In this case, damage to the gate electrode 8 can be prevented, and the energy of the implanted ions during programming can be reduced. However, on the other hand, the number of steps for forming the interlayer insulating film 9 increases.

Next, a second embodiment of the present invention will be described. The manufacturing method of the present embodiment is a manufacturing method in the case where the wiring of the logic section is a three-layer aluminum alloy wiring. Steps 1 to 3: As shown in FIGS. 5A to 5C, the steps are the same as Steps 1 to 3 of the manufacturing method of the first embodiment. In each of the drawings showing the manufacturing process of this embodiment, that is, in FIGS. 5 to 7, the left and right regions shown in FIG. 5D are the logic portion, and the central region is the ROM portion. Step 4: As shown in FIG. 5D, substantially the same as Step 4 of the manufacturing method of the first embodiment,
Is left in a region where the first wiring 10 and the memory cell transistor are not formed. Step 5: As shown in FIG. 6A, the step is almost the same as Step 5 of the manufacturing method of the first embodiment. Step 6: As shown in FIG. 6 (b), a second metal film made of an Al alloy is formed on the entire surface, and the second metal film is etched to form a first wiring having an arbitrary shape and a contact hole 1.
The second wiring 23 connected through the third wiring 3 is formed. At the same time, a third wiring 24 having an arbitrary shape that functions differently from the first wiring and a bit line 25 of a memory cell transistor are formed. The bit line 25 extends in a direction perpendicular to the plane of the drawing, and its end is located above the end of the element isolation film 4. At this time, the interlayer insulating films 9 at both ends of the bit line 25 are simultaneously etched. This leads to a reduction in implantation energy when performing ion implantation in step 9. After forming the bit line 25, the interlayer insulating film 9 may be further etched. However, the gate electrode 8
In order to ensure the insulation of the gate electrode 8, the interlayer insulating film 9 is left at least 1000 ° from the upper surface of the gate electrode 8. Next, Si
An interlayer insulating film 26 made of O2 and having a thickness of 6000 ° is formed. Step 7: As shown in FIG. 6 (c), a photoresist is formed on the entire surface, and a portion of the interlayer insulating film other than the bit line 25 above an arbitrary region of the third wiring and a region where the memory cell transistor is formed is formed. An opening is formed in the region, and a photomask 28 is formed. Step 8: As shown in FIG. 7A, the interlayer insulating film 26 is etched using the photomask 28 as a mask. At this time, the side wall protection film 29 is formed on the side surface of the bit line 25.
Is formed. Next, a third metal film made of an Al alloy is formed on the entire surface, and this is etched to form a fourth wiring 30 connected to a third wiring of an arbitrary shape via a contact hole. At this time, the bit line 25 is not etched since the interlayer insulating film 26 and the sidewall protection film 29 are formed. So far,
Since it can be manufactured regardless of what program is written in the memory cell transistor, it is possible to make a wafer. In the case where the reservoir is formed, a protective film 31 of a thin silicon oxide film of about 500 ° is formed on the surface in order to protect the metal wiring layer and prevent corrosion. Step 9: Upon receiving a request from the customer, when the program to be written is determined, as shown in FIG. 7 (b), a photoresist is formed on the entire surface to about 10000, exposed, developed, and exposed above the predetermined memory cell. A photomask 32 is formed by providing an opening in the region of FIG. At this time, the end portion 25a of the bit line 25 is exposed by making the size of the opening larger than the implantation region. Next, a predetermined memory cell transistor is depleted by ion-implanting a p-type impurity such as boron into the semiconductor substrate 1 directly below the gate electrode from the opening. As described above, bit line 2
Since the end 25a of 5 is formed immediately above the end of the element isolation film 4, more precise ion implantation can be performed by using this as a mask. As a result, the threshold voltage of the memory cell transistor is lowered, and the ROM
Data is written. Here, the energy of the ion implantation is 130 keV since the interlayer insulating film 9 is etched.
It can be performed with energy as low as about 160 keV.
Therefore, the diffusion of the implanted ions in the horizontal direction can be prevented, and more precise ion implantation can be performed. Further, since the interlayer insulating film 9 of 1000 ° remains, even if an etching error occurs, the insulation of the gate electrode 8 is not broken. Also, even if the etching is too much and the interlayer insulating film 9 does not remain, the tungsten silicide film 7 formed on the gate electrode 8 functions as an etching stopper. Absent. Step 10: As shown in FIG.
Is removed, and then a protective film 33 is formed entirely.

As described above, it is possible to form a mask ROM in which a program having a logic portion of a multilayer wiring is written.
In the present embodiment, the logic section has a two-layer wiring structure, but the same applies to a multilayer wiring. Also,
In the present embodiment, the bit line 25 is formed of the second metal film in the step 6, but the third line is formed in the step 8
May be formed by the metal film described above. Further, when the logic section has a multilayer wiring structure, the bit lines may be formed by metal wiring of any layer. The same effect can be obtained regardless of which metal film is used to form the bit line. However, since the step between the logic part and the memory cell part when forming the bit line becomes larger, it is desirable to form the bit line with the second metal film.

In step 8, in the step of exposing the end of the bit line, if the elements to be written are adjacent to each other, not only the end but also the entire bit line portion between the elements is exposed. May be. In all embodiments,
The formation of the gate electrode in steps 3 and 4 is not performed after forming the silicide film, but rather by forming a polysilicon film, patterning the polysilicon film, and selectively forming the silicide film on the polysilicon film, so-called. It may be formed using salicide technology.

In this specification, the case where a p-type semiconductor substrate is used has been described. However, an n-type semiconductor substrate may be used. In this case, each conductivity type is reversed. Further, a well formed on a semiconductor substrate may be used. In this specification, the depletion ion implantation method in which the threshold voltage is lowered is described; however, a program can be written even by performing ion implantation in which the threshold value is raised.

[0014]

According to the first or second aspect of the present invention, firstly, ion implantation for programming is performed by using a metal wiring having higher processing accuracy as a mask, so that an ion implantation is performed under the element isolation film. It is possible to prevent ions from being implanted and to suppress element isolation failure.

Second, since ion implantation is performed by etching the interlayer insulating film while leaving a predetermined thickness, ion implantation energy can be suppressed low, and ion diffusion in the lateral direction can be prevented. Separation failure can be suppressed. Third
In addition, as described above, since the element isolation failure can be suppressed, it is not necessary to form the element isolation film with a large width to avoid the element isolation failure, and the element isolation film can be formed with a small width. Can be reduced.

Fourth, since the wafer can be formed and stored up to the step of forming the metal wiring, the TAT of the product can be reduced. Fifth, since a logic part is formed simultaneously with the memory part,
The manufacturing process can be shortened, and the TAT of the product can be shortened. According to the third aspect of the present invention, since the gate electrode has silicide, the silicide acts as an etching stopper even when the interlayer insulating film is excessively etched, so that the gate electrode is damaged. There is no fear of doing.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for describing a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a cross-sectional view for explaining the method for manufacturing a semiconductor device according to the present invention.

FIG. 3 is a cross-sectional view for describing the method for manufacturing a semiconductor device according to the present invention.

FIG. 4 is a cross-sectional view for describing the method for manufacturing a semiconductor device according to the present invention.

FIG. 5 is a sectional view for illustrating the method for manufacturing a semiconductor device according to the present invention.

FIG. 6 is a cross-sectional view for describing the method for manufacturing a semiconductor device according to the present invention.

FIG. 7 is a cross-sectional view for explaining the method for manufacturing a semiconductor device according to the present invention.

FIG. 8 is a cross-sectional view for explaining a conventional method for manufacturing a semiconductor device.

FIG. 9 is a cross-sectional view for describing a problem of a conventional method of manufacturing a semiconductor device.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/8246 H01L 27/10 H01L 27/112

Claims (3)

(57) [Claims] A step of forming a plurality of element isolation films extending in one direction on a semiconductor substrate of a first conductivity type; a step of forming a gate insulating film on the semiconductor substrate; Forming a plurality of gate electrodes as word lines extending in a direction intersecting with the element isolation film on the element isolation film; and implanting impurity ions into the surface of the semiconductor substrate using the gate electrode as a mask. Forming a source region and a drain region to form a memory cell transistor; forming a first interlayer insulating film over the entire surface; and forming a first metal wiring on the first interlayer insulating film Forming a second interlayer insulating film on the entire surface;
Forming a contact hole on the first metal wiring of the second interlayer insulating film, removing the second interlayer insulating film above the memory cell transistor, exposing the first interlayer insulating film, Removing a part of the first interlayer insulating film above the memory cell transistor; forming a second metal interconnect connected to the first metal interconnect via the contact hole; Forming a metal wiring as a bit line having an end immediately above an end of the element isolation film, extending on the one interlayer insulating film in the one direction, and an opening above a predetermined gate electrode Forming a photomask having: and the first mask using the photomask and the bit line as a mask.
Etching the interlayer insulating film of the semiconductor device while leaving a predetermined thickness, and writing information by implanting impurity ions from the opening into the surface of the semiconductor substrate. . A step of forming a plurality of element isolation films extending in one direction on a semiconductor substrate of a first conductivity type; a step of forming a gate insulating film on the semiconductor substrate; Forming a plurality of gate electrodes as word lines extending in a direction intersecting with the element isolation film on the element isolation film; and implanting impurity ions into the surface of the semiconductor substrate using the gate electrode as a mask. Forming a source region and a drain region to form a memory cell transistor; forming a first interlayer insulating film over the entire surface; and forming a first metal wiring on the first interlayer insulating film Forming a second interlayer insulating film on the entire surface;
Forming a contact hole on the first metal wiring of the second interlayer insulating film, removing the second interlayer insulating film above the memory cell transistor, exposing the first interlayer insulating film, Removing a part of the first interlayer insulating film above the memory cell transistor; forming a second metal interconnect connected to the first metal interconnect via the contact hole; Forming a metal wiring as a bit line having an end directly above an end of the device isolation film on the first interlayer insulating film and extending on the first interlayer insulating film;
Forming a third interlayer insulating film over the entire surface; etching the third interlayer insulating film in a region other than the gate electrode of the memory cell transistor; While exposing the interlayer insulating film of
Forming a sidewall protection film on the bit line and forming a contact hole on the third metal wiring; and forming a fourth metal wiring connected to the third metal wiring via the contact hole. Forming a photomask having an opening above the predetermined gate electrode on the entire surface; and forming the first interlayer insulating film to a predetermined thickness using the photomask and the bit line as a mask. A method of manufacturing a semiconductor device, comprising: a step of etching while remaining; and a step of writing information by injecting impurity ions from the opening into the surface of the semiconductor substrate. 3. The method according to claim 1, wherein the step of forming the gate electrode includes a step of forming a conductive film made of polysilicon containing impurities and a step of forming a metal silicide on the conductive film. 3. The method for manufacturing a semiconductor device according to claim 1 or 2.