JP2002270702A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To establish a stable manufacturing method of a mask ROM. SOLUTION: The mask ROM includes a gate electrode 8 formed via a gate insulating film 5 on a semiconductor substrate 1, a source/drain region formed in an adjoined state to the gate electrode 8, and an Al wiring 15 via an interlayer insulting film 14 that covers the gate electrode 8. Impurity ions are implanted in the surface layer of the substrate with masks of the Al wiring 15 and photoresist formed on the Al wiring 15. In this case, the photoresist is not formed on the Al wiring 15 arranged on each adjoining element region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a mask ROM (Read On
The present invention relates to a manufacturing technique for stabilizing an operation of writing information to each element constituting a ly memory.

[0002]

2. Description of the Related Art Mask ROM TAT (Turn Around Tim)
Various techniques are known for performing ion implantation for writing information (also referred to as program writing or ROM writing) after forming an Al wiring in order to shorten e). Hereinafter, a conventional manufacturing method will be described with reference to FIG.

Step 1: As shown in FIG. 6A, a pad oxide film 52 made of a silicon oxide film is formed on a P-type semiconductor substrate 51 by a thermal oxidation method or a CVD method to a thickness of 25 n.
m. The pad oxide film 52 is formed for the purpose of protecting the surface of the semiconductor substrate 51.

Next, a silicon nitride film 53, which is an oxidation-resistant film, is formed on the entire surface. Thereafter, a strip-shaped opening 53a long in a direction perpendicular to the plane of the drawing for forming an element isolation film 54 is formed on the silicon nitride film 53. To form

Step 2: As shown in FIG. 6B, the semiconductor substrate 51 is oxidized using a LOCOS method using the silicon nitride film 53 as a mask to form an element isolation film 54. At this time, an oxidized region invades between the semiconductor substrate 51 and the silicon nitride film 53 to form a bird's beak 54a.
Next, the silicon nitride film 53 and the pad oxide film 52 are removed, and the gate insulating film 55 is formed to a thickness of 14 nm using a thermal oxidation method.
To 17 nm. Next, a polysilicon film is formed to a thickness of 350 nm by a CVD method, and is doped with phosphorus to form an N-type conductive film 56.

Step 3: As shown in FIG. 6C, a gate electrode 56a is formed by etching the conductive film 56 in a long strip shape in a direction orthogonal to the element isolation film 54 (however, the etching area is in relation to the paper surface). (Not shown in the figure). Next, using the gate electrode 56a as a mask, a P-type impurity such as boron is ion-implanted to form a source region and a drain region (the source region and the drain region are formed below both ends of the gate electrode in a direction perpendicular to the plane of the paper). (Not shown).

As described above, the memory cell transistors arranged in a matrix are formed. Next, an interlayer insulating film 57 made of a silicon oxide film is formed on the entire surface to a thickness of 500 n.
m. Next, a strip-shaped Al wiring 58 long in a direction perpendicular to the plane of the paper as a bit line is formed above the element isolation film 54. Up to this point, since the semiconductor device can be manufactured regardless of what kind of program is written in the memory cell transistor, a wafer can be prepared.
In the case of making a reservoir, a silicon oxide film 59 is formed on the entire surface as a protective film.

Step 4: Upon receiving a request from the customer and determining the program to be written, a photoresist 60 having an opening 60a for writing a mask ROM is formed as shown in FIG. 6D. Next, a predetermined memory cell transistor is depleted by ion-implanting a P-type impurity such as boron into the semiconductor substrate 51 directly below the gate electrode 56a from the opening. As a result, the threshold voltage of the memory cell transistor decreases, and ROM data is written.

[0009]

However, generally, the processing accuracy of the photoresist is low, for example, 0.5%.
It is about μm. Therefore, when the openings 60a are formed in the photoresist 60, a variation of 0.5 μm occurs. As described above, the bird's beak 54a is formed in the element isolation film 54, and the end of the element isolation film 54 is thin. As shown in FIG. 7, impurity ions may be implanted through the bird's beak 54a to the semiconductor substrate 51 below the element isolation film 54 surrounded by a circle A in the figure. If such elements are adjacent to each other, a leak current is generated between the adjacent elements under the element isolation film 54 indicated by an arrow, thereby causing an element isolation failure. Further, improving the processing accuracy of a photoresist mask has led to a significant increase in cost.

Further, in a semiconductor device in which various transistors having different withstand voltages are mounted, the thickness of the gate insulating film is set according to the various transistors. At this time, for example, when forming a gate insulating film having two kinds of film thicknesses, a thicker gate insulating film is once formed as a whole, and the gate insulating film on the side where the thinner gate insulating film is to be formed is removed by etching. Then, a process of forming a thinner gate insulating film again is adopted.

At this time, the element isolation film is scraped by the etching when the thicker gate insulating film is removed by etching. In such a process, the film thickness of the element isolation film in the ROM section is decreasing.

In the process of post-installing a ROM, ion implantation for writing data is performed through an interlayer insulating film, a gate electrode, and a gate insulating film.
It was necessary to carry out with high energy of about V to 3 MeV. When ion implantation is performed with such high energy,
The lateral diffusion of the implanted ions was increased, which also led to the above-described device isolation failure.

Furthermore, an apparatus for performing ion implantation with such a high energy is generally expensive and has led to an increase in cost.

From the above factors, it is necessary that the element isolation film is set to have a width larger than the processing limit so as to have a sufficient margin for preventing an element isolation defect, and to have a thin film having a film thickness of the element isolation film. The downsizing was in a severe situation, which hindered miniaturization.

[0015]

SUMMARY OF THE INVENTION In view of the above-mentioned problems, a method of manufacturing a semiconductor device according to the present invention is directed to a method of manufacturing a semiconductor device, comprising: a gate electrode formed on a semiconductor substrate via a gate insulating film; A source / drain region formed, and a metal wiring formed via an interlayer insulating film covering the gate electrode, wherein a photoresist formed on the metal wiring and the metal wiring are used as a mask to form a surface layer of the substrate. Wherein the photoresist is not formed on the metal wiring on the region where the impurity ions are implanted over adjacent elements.

Further, the metal wiring has a multilayer wiring structure, wherein an interlayer insulating film is removed using a photoresist as a mask to expose a lowermost metal wiring, and impurity ions are implanted using the metal wiring as a mask. And

Further, the step of implanting the impurity ions is a step of writing information into each element constituting the mask ROM.

In this way, since ion implantation is performed using a metal wiring having a higher processing accuracy as compared with a photoresist as a mask, occurrence of a conventional element isolation defect can be suppressed.

In the case where ions are implanted into adjacent elements, the photoresist is not formed on the metal wiring disposed on the region, so that the photoresist itself may fall due to the thinning of the photoresist. In the case of the multi-layer wiring structure, the lower interlayer insulating film together with the photoresist does not fall and cause a product failure.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of a method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings.

Step 1: As shown in FIG. 1A, a pad oxide film 2 is formed on a semiconductor substrate 1 and a silicon nitride film 3 having an opening is formed in the same manner as Step 1 of the conventional manufacturing process.
To form

Step 2: As shown in FIG. 1B, using the silicon nitride film 3 formed on the semiconductor substrate 1 as a mask, the semiconductor substrate 1 is oxidized by the LOCOS method to form an element isolation film 4.

Next, the pad oxide film 2 and the silicon nitride film 3 are removed, and the gate insulating film 5 is formed to a thickness of 1 using a thermal oxidation method.
A polysilicon film is formed to a thickness of 4 nm to 17 nm, a polysilicon film is formed to a thickness of 100 nm by a CVD method, and phosphorus is doped to form an N-type conductive film 6.

Subsequently, a silicide film 7 of a refractory metal such as tungsten is formed to a thickness of 150 nm. The silicide film 7 serves as a gate electrode together with the conductive film 6, and not only reduces the electrical resistance of the gate electrode, but also has a function of protecting the gate electrode as described later.

Step 3: As shown in FIG. 1C, a gate electrode 8 is formed by etching the conductive film 6 and the silicide film 7 in a strip shape long in a direction orthogonal to the device isolation film 4 (however, The etching region is not shown because it is formed on a plane parallel to the paper surface).

Next, P-type ions such as boron are implanted using the gate electrode 8 as a mask to form a source region and a drain region (the source region and the drain region are formed below both ends of the gate electrode 8 in a direction perpendicular to the plane of the paper). (Not shown).

As described above, memory cell transistors arranged in a matrix are formed.

Then, a silicon oxide film 10, a silicon nitride film 11, a polysilicon film 12,
Further, the interlayer insulating film 14 made of the silicon oxide film 13 is
Formed at 0 nm. Here, the polysilicon film 12
Serves as an etching stopper when etching an interlayer insulating film 14 described later.

Step 4: As shown in FIG. 2A, a metal film made of an Al film or the like is formed on the interlayer insulating film 14, and the metal film is patterned to form an Al wiring 1 serving as a word line.
5 is formed.

At this time, the end 15 of the Al wiring 15
a is formed so as to be disposed immediately above the end of the element isolation film 4. Up to this point, since the semiconductor device can be manufactured regardless of what kind of program is written in the memory cell transistor, a wafer can be prepared. In the case of making a reservoir, a protective film 16 of a thin silicon oxide film of about 50 nm or the like is formed on the surface in order to protect the metal wiring layer and prevent corrosion.

Step 5: Upon receiving a request from the customer and determining the program to be written, as shown in FIG. 2B, a photoresist 17 is formed on the entire surface to a thickness of about 1000 nm, and is exposed and developed for a predetermined time. An opening 17a is provided in a region above the memory cell. At this time, by forming the size of the opening 17a larger than that of the implantation region, Al
The end 15a of the wiring 15 is exposed. Next, the interlayer insulating film 14 is etched using the photoresist 12 and the Al wiring 15 as a mask. The etching is anisotropic dry etching, and the interlayer insulating film 14 is left by 100 nm from the upper surface of the gate electrode.

Further, a predetermined memory cell transistor is depleted by ion-implanting a P-type impurity such as boron into the semiconductor substrate 1 directly below the gate electrode 8 through the opening 17a. As described above, since the end of the Al wiring 15 is formed immediately above the end of the element isolation film 4,
By using this as a mask, more accurate ion implantation can be performed. As a result, the threshold voltage of the memory cell transistor decreases, and ROM data is written.

Moreover, in the present invention, when writing ROM data, a metal film (Al wiring 15) having higher processing accuracy than a conventional photoresist is used as a mask.
As in the conventional case, it is not necessary to set the element isolation film to a width larger than the processing limit by providing a sufficient margin for avoiding the occurrence of the element isolation failure, thereby enabling miniaturization.

Here, the energy of the ion implantation can be performed at a low energy of about 130 KeV to 160 KeV because the interlayer insulating film 14 is etched. Therefore, the diffusion of the implanted ions in the horizontal direction can be prevented, and more precise ion implantation can be performed.

Through the above steps, a mask ROM in which a desired program is written is completed.

Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

Here, the feature of the second embodiment is that in the step of exposing the end portion of the metal wiring in the step 5 of the first embodiment, if an element to which a program is written is adjacent, Is to expose all the metal wirings existing in the writing region of FIG.

That is, in the first embodiment, when a photoresist used for forming a program writing area is patterned, a predetermined space is provided between the program writing areas. Therefore, a thin photoresist remains on the metal wiring arranged in the region where the writing element is adjacent.

In particular, in a process employing a two-layer wiring or a three-layer wiring structure, when an opening is formed in an interlayer insulating film covering each wiring by using the photoresist as a mask, the photoresist or the interlayer is formed. The insulating film has collapsed,
There was a risk of causing product failure.

Therefore, in the second embodiment, no space is provided between the program writing areas at a place where such a program writing area is adjacent.

In FIG. 3, reference numeral 18 denotes a photoresist, which exposes the entire upper surface of the Al wiring 15 disposed at a location (hatched area in the figure) where an element area for writing a program is adjacent as shown in the figure. The opening 18a is formed so as to perform the above.

FIG. 4 shows a third embodiment in which the present invention is applied to a method of manufacturing a semiconductor device having a multilayer wiring structure. The same components as those in the first and second embodiments described above are denoted by the same reference numerals in order to avoid redundant description.
Further, the description will be simplified with reference to FIG.

Step 1: As shown in FIG. 1A, a pad oxide film 2 is formed on a semiconductor substrate 1, and a silicon nitride film 3 having an opening is formed.

Step 2: As shown in FIG. 1B, after forming an element isolation film 4 on the semiconductor substrate 1 using the silicon nitride film 3 formed on the semiconductor substrate 1 as a mask, the pad oxide film is formed. 2 and the silicon nitride film 3 are removed, a gate insulating film 5 is formed to a thickness of 14 to 17 nm by a thermal oxidation method, and a polysilicon film is formed to a thickness of 100 nm by a CVD method.
And an N-type conductive film 6 is formed by doping with phosphorus.

Subsequently, a silicide film 7 of a refractory metal such as tungsten is formed to a thickness of 150 nm.

Step 3: As shown in FIG. 1C, a gate electrode 8 is formed by etching the conductive film 6 and the silicide film 7 in a strip shape long in a direction perpendicular to the device isolation film 4 (however, The etching region is not shown because it is formed on a plane parallel to the paper surface).

Next, P-type ions such as boron are implanted using the gate electrode 8 as a mask to form a source region and a drain region (the source region and the drain region are formed below both ends of the gate electrode 8 in a direction perpendicular to the plane of the paper). (Not shown).

As described above, memory cell transistors arranged in a matrix are formed.

Then, a silicon oxide film 10, a silicon nitride film 11, a polysilicon film 12,
Further, a first interlayer insulating film 14 made of a silicon oxide film 13
a (see FIG. 4) is formed at 600 nm.

Step 4: As shown in FIG. 4A, a metal film made of an Al film or the like is formed on the interlayer insulating film 14a.
The first A which becomes a word line by patterning the metal film
An l wiring 15 is formed. At this time, similarly to the above embodiment, the end 15a of the Al wiring 15 (see FIGS. 2 and 3)
Is formed just above the end of the element isolation film 4.

Then, a second interlayer insulating film 23 made of a three-layer film of a silicon oxide film 20, an SOG film 21 and a silicon oxide film 22 is formed to a thickness of 600 nm on the entire surface for planarization. A metal film made of an Al film or the like is formed, and the metal film is patterned to form a second bit line.
Is formed.

Step 5: As shown in FIG. 4B, a 600 nm-thick third interlayer insulating film 25 is formed on the entire surface so as to cover the second Al wiring 24, and is formed on the interlayer insulating film 25. A metal film made of an Al film or the like is formed, and the metal film is patterned to form a third Al wiring 26.

Up to this point, since it is possible to manufacture the memory cell transistor irrespective of what kind of program is written in the memory cell transistor, it is possible to make a wafer. In the case of making a reservoir, a protective film 27 of a thin silicon oxide film of about 50 nm or the like is formed on the surface in order to protect the metal wiring layer and prevent corrosion.

Step 6: Upon receiving a request from the customer, when a program to be written is determined, a photoresist 28 is formed to a thickness of about 1000 nm on the entire surface, exposed and developed, and an opening 28a is formed in an area above a predetermined memory cell. Is provided.

At this time, the size of the opening 28a is larger than that of the implantation region. For example, when a program is written in each adjacent element, the entire upper portion of the Al wiring 15 arranged on the region can be exposed. The opening diameter of the photoresist is set in advance.

Then, using the photoresist 28 as a mask, the interlayer insulating film 2 on a region where a program is to be written is formed.
5, 23, and 14 are removed by etching. At this time, the etching is completed on the polysilicon film 12.

Here, FIG. 5 shows the first embodiment and the third embodiment.
In order to compare with the second embodiment, a case where a semiconductor device having a multilayer wiring structure shown in FIG. 4 is formed based on the first embodiment is illustrated.

As shown in FIG. 5, in the first embodiment, when ions are implanted into each adjacent element, a thin photoresist 2 is formed on an Al wiring 15 disposed on that area.
8, the photoresist 28 falls when etching the interlayer insulating films 25, 23, 14a using the photoresist 28 as a mask, or the interlayer insulating films 25, 23, etc. fall along with the photoresist 28, resulting in defective products. May cause

On the other hand, according to the third embodiment, when a program is written in each adjacent element as shown in FIG.
Since no photoresist is present on the l-wiring 15, the photoresist and the interlayer insulating film do not fall when the interlayer insulating films 25, 23, and 14a are etched, and a stable product can be manufactured in a process.

Further, a predetermined memory cell transistor is depleted by ion-implanting a P-type impurity such as boron into the semiconductor substrate 1 directly below the gate electrode 8 through the opening 28a. As described above, since the end 15a of the Al wiring 15 is formed immediately above the end of the element isolation film 4, more precise ion implantation can be performed by using this as a mask. As a result, the threshold voltage of such a memory cell transistor is lowered, and RO
M data is written.

Further, in the present invention, when writing ROM data, a metal film (Al wiring 15) having higher processing accuracy than a conventional photoresist is used as a mask.
As in the conventional case, it is not necessary to set the element isolation film to a width larger than the processing limit by providing a sufficient margin for avoiding the occurrence of the element isolation failure, thereby enabling miniaturization.

Here, the energy of the ion implantation is Al
Interlayer insulating film 1 together with interlayer insulating films 23 and 25 on wiring 15
Since part of 4 is etched, it can be performed with a low energy of about 130 KeV to 160 KeV. Therefore, the diffusion of the implanted ions in the horizontal direction can be prevented, and more precise ion implantation can be performed.

Through the above steps, a mask ROM in which a desired program is written is completed.

The technical idea of the present invention can be easily applied to a case where a multilayer metal wiring is formed.

Step 3 of each of the first, second and third embodiments
In the above, the formation of the gate electrode may be a polysilicon film formation, a polysilicon film patterning, or a selective formation of a silicide film on the polysilicon film.

In each of the above embodiments, the case where a P-type semiconductor substrate is used has been described, but an N-type semiconductor substrate may be used.
A well formed on a semiconductor substrate may be used.

In each of the above embodiments, the depletion type ion implantation method for lowering the threshold voltage has been described. However, the program can be written even if ion implantation for increasing the threshold value is performed.

Further, the scope of application of the present invention is not limited to a program writing method in a mask ROM or the like, but can be applied to various products having a step of implanting impurity ions using a metal wiring as a mask.

[0069]

According to the present invention, since the impurity ions are implanted into the surface of the substrate by using a metal wiring having higher processing accuracy as a mask, it is possible to implant an appropriate amount of impurity ions at an appropriate position. it can.

Also, by applying the present invention to a mask ROM manufacturing method and using it in an ion implantation step for writing information, it is possible to prevent impurity ions from being implanted under the element isolation film, and to improve the element isolation failure. Can be suppressed.

Further, when impurity ions are respectively implanted into adjacent elements using a photoresist or a metal wiring as a mask, the photoresist is prevented from remaining on the metal wiring disposed on the adjacent element region. Thus, when the interlayer insulating film is etched using the photoresist as a mask, the photoresist and the interlayer insulating film do not fall down, and a stable operation in a process becomes possible.

Further, since ion implantation is performed after etching the interlayer insulating film by a predetermined amount using the metal wiring as a mask, ion implantation energy can be suppressed low, lateral diffusion of ions can be prevented, and element isolation failure can be prevented. Can be suppressed.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for describing a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a cross-sectional view for explaining the method for manufacturing a semiconductor device according to the present invention.

FIG. 3 is a cross-sectional view for explaining the method for manufacturing a semiconductor device according to the present invention.

FIG. 4 is a cross-sectional view for describing the method for manufacturing a semiconductor device according to the present invention.

FIG. 5 is a sectional view for illustrating the method for manufacturing a semiconductor device according to the present invention.

FIG. 6 is a cross-sectional view for explaining a conventional method for manufacturing a semiconductor device.

FIG. 7 is a cross-sectional view for explaining a problem of a conventional semiconductor device.

Continued on the front page (72) Inventor Junichi Ariyoshi 2-5-5 Keihanhondori, Moriguchi-shi, Osaka F-term (reference) in Sanyo Electric Co., Ltd. 5F083 CR02 GA27 JA35 JA36 JA39 KA20 NA02 PR01 PR06 PR23 PR36

Claims (4)

[Claims] A gate electrode formed on a semiconductor substrate via a gate insulating film, a source / drain region formed adjacent to the gate electrode, and an interlayer insulating film covering the gate electrode. A method of manufacturing a semiconductor device having a metal wiring formed by forming a photoresist on the metal wiring and implanting impurity ions into a surface layer of the substrate using the metal wiring as a mask. A method of manufacturing a semiconductor device, wherein a photoresist is not formed on a metal wiring disposed on a region into which a semiconductor device is implanted. 2. The method according to claim 1, wherein the metal wiring has a multilayer wiring structure, wherein an interlayer insulating film is removed using a photoresist as a mask to expose a lowermost metal wiring, and impurity ions are implanted using the metal wiring as a mask. The method of manufacturing a semiconductor device according to claim 1. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the step of implanting the impurity ions is a step of writing information into each element constituting a mask ROM. 4. A plurality of device isolation films formed on a semiconductor substrate and extending in one direction; a gate electrode extending on the substrate via a gate insulating film in a direction orthogonal to the one direction; Source / drain regions formed so as to be adjacent to the gate electrode, and formed above the element isolation film via an interlayer insulating film;
In the method for manufacturing a semiconductor device in which information is written by implanting impurity ions into the surface of the substrate using the metal wiring extending in one direction as a mask, the semiconductor device is arranged on a region into which impurity ions are implanted into adjacent elements. A method of manufacturing a semiconductor device, comprising: writing information using a metal wiring as a mask without forming a photoresist on the metal wiring.