JP2002313960A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To establish a stable manufacturing method for a mask ROM. SOLUTION: This semiconductor device has a gate electrode 8 formed on a semiconductor substrate 1 across a gate insulating film 5, a source-drain area formed adjacently to the gate electrode 8, a narrow Al wire 15 and a wide Al wire 15A formed across an inter-layer insulating film 14 of a lower layer covering the gate electrode 8, and an inter-layer insulating film 21 of an upper layer flattened by using an SOG film 19 formed to cover the Al wires 15 and 15A, and is constituted by implanting impurity ions into the substrate surface layer with the inter-layer insulating films 21 and 14 etched off by a specific quantity by using a photoresist 24 formed above the Al wires 15 and 15A and the Al wires 15 and 15A as a mask. A recessed part 17 is formed in the surface part of the wide Al wire 15A.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a mask ROM (Rea
d Only Memory), which relates to a manufacturing technique for stabilizing the work of writing information to each element constituting each element.

[0002]

2. Description of the Related Art Mask ROM TAT (Turn Around Tim)
Various techniques are known for performing ion implantation for writing information (also referred to as program writing or ROM writing) after forming an Al wiring in order to shorten e). Hereinafter, a conventional manufacturing method will be described with reference to FIG.

Step 1: As shown in FIG. 5A, a pad oxide film 52 made of a silicon oxide film is formed on a P-type semiconductor substrate 51 by a thermal oxidation method or a CVD method to a thickness of 25 n.
m. The pad oxide film 52 is formed for the purpose of protecting the surface of the semiconductor substrate 51.

Next, a silicon nitride film 53, which is an oxidation-resistant film, is formed on the entire surface. Thereafter, a strip-shaped opening 53a long in a direction perpendicular to the plane of the drawing for forming an element isolation film 54 is formed on the silicon nitride film 53. To form

Step 2: As shown in FIG. 5B, the semiconductor substrate 51 is oxidized using a LOCOS method using the silicon nitride film 53 as a mask to form an element isolation film 54. At this time, an oxidized region invades between the semiconductor substrate 51 and the silicon nitride film 53 to form a bird's beak 54a.
Next, the silicon nitride film 53 and the pad oxide film 52 are removed, and the gate insulating film 55 is formed to a thickness of 14 nm using a thermal oxidation method.
To 17 nm. Next, a polysilicon film is formed to a thickness of 350 nm by a CVD method, and is doped with phosphorus to form an N-type conductive film 56.

Step 3: As shown in FIG. 5C, a gate electrode 56a is formed by etching the conductive film 56 so as to extend the element isolation film 54 in a direction perpendicular to the direction perpendicular to the paper. (Not shown in the figure). Next, using the gate electrode 56a as a mask, a P-type impurity such as boron is ion-implanted to form a source region and a drain region (the source region and the drain region are formed below both ends of the gate electrode in a direction perpendicular to the plane of the paper). (Not shown).

As described above, the memory cell transistors arranged in a matrix are formed. Next, an interlayer insulating film 57 made of a silicon oxide film is formed on the entire surface to a thickness of 500 n.
m. Next, a strip-shaped Al wiring 58 long in a direction perpendicular to the plane of the paper as a bit line is formed above the element isolation film 54. Up to this point, since the semiconductor device can be manufactured regardless of what kind of program is written in the memory cell transistor, a wafer can be prepared.
In the case of making a reservoir, a silicon oxide film 59 is formed on the entire surface as a protective film.

Step 4: Upon receiving a request from the customer and determining a program to be written, a photoresist 60 having an opening 60a for writing a mask ROM is formed as shown in FIG. 5D. Next, a predetermined memory cell transistor is depleted by ion-implanting a P-type impurity such as boron into the semiconductor substrate 51 directly below the gate electrode 56a from the opening. As a result, the threshold voltage of the memory cell transistor decreases, and ROM data is written.

[0009]

However, generally, the processing accuracy of the photoresist is low, for example, 0.5%.
It is about μm. Therefore, when the openings 60a are formed in the photoresist 60, a variation of 0.5 μm occurs. As described above, the bird's beak 54a is formed in the element isolation film 54, and the end of the element isolation film 54 is thin. 6, impurity ions may be implanted through the bird's beak 54a and into the semiconductor substrate 51 below the element isolation film 54 surrounded by a circle A in the figure. If such elements are adjacent to each other, a leak current is generated between the adjacent elements under the element isolation film 54 indicated by an arrow, thereby causing an element isolation failure. Further, improving the processing accuracy of a photoresist mask has led to a significant increase in cost.

Further, in a semiconductor device in which various transistors having different withstand voltages are mounted, the thickness of the gate insulating film is set according to the various transistors. At this time, for example, when forming a gate insulating film having two kinds of film thicknesses, a thicker gate insulating film is once formed as a whole, and the gate insulating film on the side where the thinner gate insulating film is to be formed is removed by etching. Then, a process of forming a thinner gate insulating film again is adopted.

At this time, the element isolation film is scraped by the etching when the thicker gate insulating film is removed by etching. In such a process, the film thickness of the element isolation film in the ROM section is decreasing.

In the process of post-installing a ROM, ion implantation for writing data is performed through an interlayer insulating film, a gate electrode, and a gate insulating film.
It was necessary to carry out with high energy of about V to 3 MeV. When ion implantation is performed with such high energy,
The lateral diffusion of the implanted ions was increased, which also led to the above-described device isolation failure.

Furthermore, an apparatus for performing ion implantation with such a high energy is generally expensive and has led to an increase in cost.

From the above factors, it is necessary that the element isolation film is set to have a width larger than the processing limit so as to have a sufficient margin for preventing an element isolation defect, and to have a thin film having a film thickness of the element isolation film. The downsizing was in a severe situation, which hindered miniaturization.

Therefore, a technique for writing the above information using a metal film (Al wiring or the like) having a higher processing accuracy than a photoresist as a mask has been implemented.

For example, in the process of writing information using the Al wiring 58 as a mask, a planarized interlayer insulating film is often formed on the Al wiring 58 in many cases. Incidentally, as the interlayer insulating film subjected to the above-mentioned flattening treatment, a silicon oxide film 61 was formed as shown in FIG. 7A, and a spin-on-glass film 62 (hereinafter abbreviated as SOG film) was formed. Later, there is a configuration in which the SOG film 62 is etched back by a predetermined amount and the silicon oxide film 63 is formed again.

At this time, as shown in FIG. 7A, a wide Al wiring 58 is formed around the random logic portion and the memory portion.
When A (for example, 15 μm or more) exists, the SOG in the periphery thereof is affected by the effect of the wide Al wiring 58A.
The film 62 becomes thicker than necessary.

Therefore, when an opening is formed by etching a region where information is to be written, as shown in FIG. 7B, the SOG film 62 which is unnecessarily thick leaves an etching residue 65, and causes a contact via or a ROM. The opening amount of the opening for writing information to the portion is insufficient, and the yield is reduced.

Therefore, it is conceivable to suppress the occurrence of the above-mentioned etching residue by increasing the etching amount (time). In this case, however, the Al wiring itself serving as a mask is also slightly etched. As a result, a side wall deposit is formed on the side wall of the opening. This does not cause any particular problem if the set etching amount (time) is appropriate. However, as described above, the remaining etching is suppressed. Therefore, if an excessive etching amount (time) is set,
The influence of the deposit on the side wall becomes large, the coverage at the time of forming the passivation film is deteriorated, and there are reliability problems such as generation of pinholes and deterioration of moisture resistance. Further, since the cross-sectional area of the Al wiring is reduced, the life of electromigration is also deteriorated.

For this reason, it is impossible to unnecessarily increase the etching amount (time) in order to suppress the generation of the remaining etching.

[0021]

SUMMARY OF THE INVENTION In view of the above problems, a semiconductor device of the present invention has a gate electrode formed on a semiconductor substrate via a gate insulating film, and a gate electrode formed adjacent to the gate electrode. A source / drain region, a narrow metal wiring and a wide metal wiring formed via an interlayer insulating film of a lower layer covering the gate electrode, and a planarization process formed so as to cover the metal wiring. Having an upper interlayer insulating film applied thereto, and implanting impurity ions into the surface layer of the substrate while etching the interlayer insulating film by a predetermined amount using the photoresist formed above the metal wiring and the metal wiring as a mask. A concave portion is formed in a surface portion of the wide metal wiring.

Further, slits are provided at predetermined intervals so as to subdivide the wide metal wiring.

[0023] The manufacturing method is characterized in that the upper interlayer insulating film is formed such that a planarizing film is buried in a recess formed in a surface portion of the wide metal wiring.

Further, the upper interlayer insulating film is formed so that a flattening film is buried in slits formed at predetermined intervals so as to subdivide the wide metal wiring.

Further, the step of implanting the impurity ions is a step of writing information into each element constituting the mask ROM.

Since the flattening film is buried in the concave portions and the slits, the flattening film is not laminated unnecessarily around the wide metal wiring.
Insufficiency of the opening due to the remaining etching is suppressed.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a semiconductor device and a method for manufacturing the same according to the present invention will be described below with reference to the drawings.

Step 1: As shown in FIG. 1 (a), a pad oxide film 2 is formed on a semiconductor substrate 1 and a silicon nitride film 3 having an opening is formed in the same manner as step 1 of the conventional manufacturing process.
To form

Step 2: As shown in FIG. 1B, using the silicon nitride film 3 formed on the semiconductor substrate 1 as a mask, the semiconductor substrate 1 is oxidized by LOCOS to form an element isolation film 4.

Next, the pad oxide film 2 and the silicon nitride film 3 are removed, and the gate insulating film 5 is formed to a thickness of 1 using a thermal oxidation method.
A polysilicon film is formed to a thickness of 4 nm to 17 nm, a polysilicon film is formed to a thickness of 100 nm by a CVD method, and phosphorus is doped to form an N-type conductive film 6.

Subsequently, a silicide film 7 of a refractory metal such as tungsten is formed to a thickness of 150 nm. The silicide film 7 serves as a gate electrode together with the conductive film 6, and not only reduces the electrical resistance of the gate electrode, but also has a function of protecting the gate electrode as described later.

Step 3: As shown in FIG. 1C, a gate electrode 8 is formed by etching the conductive film 6 and the silicide film 7 in a strip shape long in a direction perpendicular to the device isolation film 4 (however, The etching region is not shown because it is formed on a plane parallel to the paper surface).

Next, P-type ions such as boron are implanted using the gate electrode 8 as a mask to form a source region and a drain region (the source region and the drain region are formed below both ends of the gate electrode 8 in a direction perpendicular to the plane of the paper). (Not shown).

As described above, the memory cell transistors arranged in a matrix are formed.

Then, a silicon oxide film 10, a silicon nitride film 11, a polysilicon film 12,
Further, a first interlayer insulating film 14 made of a silicon oxide film 13
Is formed at 600 nm. Here, the polysilicon film 12 serves as an etching stopper in an interlayer insulating film etching process described later.

Step 4: As shown in FIG. 2A, a metal film made of an Al film or the like is formed on the interlayer insulating film 14, and the metal film is patterned to form a first Al film serving as a word line.
The wiring 15 is formed.

This step is a step that characterizes the present invention,
First, a metal film made of an Al film or the like is formed on the interlayer insulating film 14 to a thickness of 500 nm, and is patterned using a photoresist (not shown) as a mask to form an Al wiring 15 serving as a word line. A wide Al wiring 15A (for example, 15 μm or more) is formed in the peripheral portion of. Then, patterning is performed using the photoresist 16 as a mask to form a concave portion 17 having a predetermined depth in the surface portion of the wide Al wiring 15A. In the drawing, the recess 17 is used.
Is shown, but actually, they are provided at predetermined intervals according to the size of the wide Al wiring 15A.

At this time, the Al wiring 15 is formed such that the Al wiring end 15 a of the Al wiring 15 is disposed immediately above the end of the element isolation film 4. As the Al wirings 15 and 15A, a barrier metal film formed by forming a titanium film under the metal film with a thickness of 20 nm and further forming a titanium nitride film with a thickness of 35 nm may be formed.

Step 5: As shown in FIG. 2B, a silicon oxide film 18 is formed on the entire surface, and SO
A G film 19 is formed, and as shown in FIG.
After the G film 19 is etched back by a predetermined amount, a silicon oxide film 20 is formed, thereby forming a second interlayer insulating film 21 of a three-layer film with a thickness of 600 nm.

Step 6: As shown in FIG. 3A, a metal film made of an Al film or the like is formed on the interlayer insulating film 21, and the metal film is patterned to form a second Al film serving as a bit line.
Wiring (not shown) is formed, a third interlayer insulating film 22 of 600 nm is formed on the entire surface so as to cover the second Al wiring, and a metal film made of an Al film or the like is formed on the interlayer insulating film 22. And forming a third Al layer by patterning the metal film.
Wiring (not shown) is formed.

Up to this point, since the manufacturing can be performed regardless of what kind of program is written in the memory cell transistor, it is possible to store the wafer.
In addition, when the reservoir is formed, it can be dealt with by forming a protective film such as a thin silicon oxide film of about 50 nm on the surface in order to protect the metal wiring layer and prevent corrosion.

Step 7: Upon receiving a request from the customer, when the program to be written is determined, the fourth
After a photoresist 24 is formed on the interlayer insulating film 23, the interlayer insulating film is etched using the photoresist 24 as a mask to provide an opening 24a in a region above a predetermined memory cell in which a program is to be written. Contact via 24b contacting on the Al wiring 15
To form At this time, the etching for forming the opening 24a ends on the polysilicon film 12 (FIG. 3).
(B)).

Step 8: As shown in FIG. 3B, a predetermined memory cell transistor is depleted by ion-implanting a P-type impurity such as boron into the semiconductor substrate 1 directly below the gate electrode 8 through the opening 24a. Become
As described above, since the end 15a of the Al wiring 15 is formed immediately above the end of the element isolation film 4, more precise ion implantation can be performed by using this as a mask. As a result, the threshold voltage of the memory cell transistor decreases, and ROM data is written.

In addition, in the present invention, when writing ROM data, a metal film (Al wiring 15) having higher processing accuracy than a conventional photoresist is used as a mask.
As in the conventional case, it is not necessary to set the element isolation film to a width larger than the processing limit by providing a sufficient margin for avoiding the occurrence of the element isolation failure, thereby enabling miniaturization.

Here, the energy of the ion implantation is Al
Since a part of the interlayer insulating film 14 is etched together with the interlayer insulating films 23, 22 and 21 on the wiring 15, it is 130 Ke.
It can be performed with energy as low as about V to 160 KeV. Therefore, the diffusion of the implanted ions in the horizontal direction can be prevented, and more precise ion implantation can be performed.

Step 9: Although illustration is omitted, a pad portion is formed via the contact via and then a passivation film is formed on the entire surface to complete a mask ROM in which a desired program is written.

As described above, in the present invention, a wide A
By forming a concave portion 17 having a predetermined depth in the surface portion of the l-wiring 15A, the wide Al wiring 15A can be formed in a manufacturing process having an interlayer insulating film subjected to a planarization process using an SOG film or the like. Since the SOG film 19 is not formed unnecessarily thick thereon, etching residue does not occur when the SOG film 19 is etched back and when the interlayer insulating film is subsequently etched. Therefore, it is possible to suppress the occurrence of insufficient opening at the time of etching the interlayer insulating film, to stably open the contact via and the information writing opening of the ROM section, and to stabilize the characteristics and the yield. In addition, the uniformity in planarizing the wafer surface is improved.

Hereinafter, another embodiment of the present invention will be described with reference to the drawings. Note that a manufacturing process equivalent to that of the embodiment will be described with reference to the drawings used in the embodiment.

Here, another embodiment is characterized in that, after the step shown in FIG. 1 (that is, the step of forming the interlayer insulating film 14) in the above-described embodiment, the interlayer insulating film is formed as shown in FIG. A first Al wiring 15 is formed on the film 14, and slits 3 are formed at predetermined intervals in a wide Al wiring 15A.
0 was formed.

By forming the slits 30 at predetermined intervals in the wide Al wiring 15A, the SOG film 19 forming the interlayer insulating film 21 is formed in the slit 30.
Is buried, so that the wide Al
The SOG film is not formed unnecessarily thick in the peripheral portion of the wiring 15A.

Therefore, also in the present embodiment, it is possible to suppress the occurrence of insufficient opening at the time of etching the interlayer insulating film,
The information writing opening of the contact via and the ROM section can be stably opened, and the characteristics and the yield can be stabilized. In addition, the uniformity in planarizing the wafer surface is improved.

More specifically, in this embodiment, after forming the Al wiring 15A as in the embodiment, the Al wiring 1A is formed.
Unlike the case where the concave portion 17 is formed in the surface portion of 5A in a separate step, the number of manufacturing steps does not increase because the slit 30 is formed at the time of patterning the Al wirings 15 and 15A.

The technical idea of the present invention can be easily applied to a case where a multi-layered metal wiring is formed.

In the above-mentioned step 3, the gate electrode may be formed by forming a polysilicon film, patterning the polysilicon film, or selectively forming a silicide film on the polysilicon film.

In the above embodiments, the case where a P-type semiconductor substrate is used has been described. However, an N-type semiconductor substrate may be used.
A well formed on a semiconductor substrate may be used.

In each of the above embodiments, the depletion type ion implantation method for lowering the threshold voltage has been described. However, the program can be written even if ion implantation for increasing the threshold value is performed.

Further, the scope of application of the present invention is not limited to a program writing method in a mask ROM or the like, but can be applied to various products having a step of implanting impurity ions using a metal wiring as a mask.

[0058]

According to the present invention, by forming a recess in the surface of a wide metal wiring or forming a slit in the wide metal wiring, an interlayer insulating film is formed in the recess or slit. Since the processing film is buried, the flattening processing film is not unnecessarily laminated on the periphery of the wide metal wiring, and the deterioration of the characteristics and the decrease in the yield due to the unetched portion can be suppressed.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 4 is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to another embodiment of the present invention.

FIG. 5 is a cross-sectional view for explaining a conventional method for manufacturing a semiconductor device.

FIG. 6 is a cross-sectional view for explaining a conventional method for manufacturing a semiconductor device.

FIG. 7 is a diagram for explaining a conventional problem.

Continued on front page F term (reference)

Claims (5)

[Claims] 1. A gate electrode formed on a semiconductor substrate via a gate insulating film, a source / drain region formed adjacent to the gate electrode, and a lower interlayer insulating film covering the gate electrode. A narrow metal wiring and a wide metal wiring formed through the metal wiring, and an upper interlayer insulating film formed so as to cover the metal wiring and having been subjected to a planarization process; A semiconductor device formed by implanting impurity ions into the surface layer of the substrate while etching the interlayer insulating film by a predetermined amount using the photoresist formed on the substrate and the metal wiring as a mask, wherein a concave portion is formed in a surface portion of the wide metal wiring. A semiconductor device characterized by being performed. 2. The semiconductor device according to claim 1, wherein slits are provided at predetermined intervals so as to subdivide said wide metal wiring. 3. A gate electrode formed on a semiconductor substrate via a gate insulating film, source / drain regions formed adjacent to the gate electrode, and an interlayer insulating film covering the gate electrode. A narrow metal wiring and a wide metal wiring formed by the above method, and an upper interlayer insulating film formed so as to cover the metal wiring and subjected to a planarization process, and formed above the metal wiring. A method of manufacturing a semiconductor device, comprising implanting impurity ions into the surface layer of the substrate while etching the interlayer insulating film by a predetermined amount using the photoresist and the metal wiring as a mask, wherein the interlayer insulating film is formed on the surface of the wide metal wiring. A method of manufacturing a semiconductor device, comprising: forming an upper interlayer insulating film such that a planarization film is buried in a recess. 4. The method according to claim 1, wherein the upper interlayer insulating film is formed such that a planarizing film is buried in slits formed at predetermined intervals so as to subdivide the wide metal wiring. Item 4. The method for manufacturing a semiconductor device according to Item 3. 5. The method according to claim 3, wherein the step of implanting the impurity ions is a step of writing information into each element constituting a mask ROM.