JPS6130063A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To provide a cell-array with a high integration rate, by providing with a high melting-point metal silicide on the surface of a source diffusing region or on the surface of a diffusing wiring region connected to the source diffusing region, in an MOS type nonvolatile memory transistor which can write by flowing current across the source and drain. CONSTITUTION:On a P type Si substrate 21, a gate oxidation film 22, a floating gate electrode 23 of polycrystalline Si, an inter-gate insulating film 24, and a control electrode 25 of polycrystalline Si are sequentially formed. Next, a drain region 26, a source region, and a source common diffusing layer wiring region 27 are formed by implanting As ions, and the surface of the memory transistor and the diffusing region is covered with an SiO2 film 28. Thereafter, through the film 28 on the region 27, a slit 29 is bored, in which Ti is coated with sputtering and annealed in an N2 atmosphere, for the purpose of creating a Ti silicide layer 30 only on the Si surface being exposed in the slit 29 to reduce layer resistance considerably.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to nonvolatile semiconductor memory devices, and more particularly to devices having improved memory cell arrangements.

(Prior art) Various M
An OS device is being developed, but currently the technology, source,
A so-called channel electron device has a drain, a floating gate, and a control gate made of polysilicon (polycrystalline silicon), and performs writing by flowing current between the source and drain and injecting electrons accelerated in the channel into the floating gate. Injected floating gate MOS memory transistors are widely used.

If this memory transistor is used, one bit of a memory device can be constructed from one transistor, and it is very suitable for high integration. Conventionally, when configuring a cell array by integrating the above-mentioned floating MOS memory transistors, the memory transistors are arranged in a matrix,
The drains of the memory transistors arranged in the column direction are commonly connected to an aluminum wire to form a bit line, and the polysilicon control gate electrodes of the memory transistors arranged in the row direction are commonly connected to form a polysilicon word line. The sources of the mesori transistors are connected to a common diffusion layer wiring, and connected to an aluminum ground wiring placed parallel to the bit line at an appropriate location. A circuit diagram of a conventional memory cell array configured as described above is shown in FIG. t-14.

Writing into a memory transistor will be explained by taking as an example the case where the device shown in FIG. 44 is an N-channel type. When writing to the memory transistor QIK, a high positive voltage is applied to the polysilicon word line Wl, and a positive write voltage is applied to the aluminum bit line Bl. At this time, the channel of the memory run raster Ql becomes conductive, and current flows from the bit line B1 through the channel of the memory transistor Q1, through the source common diffusion layer wiring SL, and into the aluminum ground line GL. A portion of the electrons flowing through the channel of the memory transistor Q1 are accelerated by the electric field between the source and drain, obtain high energy, overcome the barrier of the gate oxide film, and are injected into the floating gate to perform writing. In this case, if the resistance of the source common diffusion layer wiring SL is too large, a voltage determined by the product of the write current and the wiring resistance will be applied to the source of the memory transistor Ql. The electric field that accelerates the electrons weakens, and writing to the memory transistor Ql becomes insufficient. In this way, the resistance of the source common diffusion layer interconnection added between the source of the memory transistor and the ground potential becomes a ℃ hindrance to writing, and therefore it is desirable that it be as low as possible.

In conventional memory cell arrays, the distance between the source common diffusion layer wiring between the source of each memory transistor and the aluminum ground line can be increased by increasing the width of the common source diffusion layer wiring or by increasing the number of aluminum grounding edges. By shortening , the resistance value added between the source of the memory transistor and the ground potential is reduced. However, all of the above methods reduce the integration density of the memory cell array, and have the disadvantage that they are not compatible with the miniaturization and larger capacity of nonvolatile semiconductor memory devices, which are becoming increasingly demanding. .

(Object of the Invention) An object of the present invention is to reduce the layer resistance of the source common diffusion layer wiring in the mesoricell array, thereby increasing the width of the diffusion layer wiring, or reducing the number of aluminum ground lines. It is an object of the present invention to provide a memory cell array that can guarantee the write characteristics of each memory transistor without increasing the number of memory transistors, that is, a memory cell 7 array suitable for high integration.

(Structure of the Invention) A nonvolatile semiconductor memory device of the present invention performs writing by flowing a current between a source and a drain on a semiconductor substrate, and five MOS type nonvolatile memory transistors are arranged in a matrix and a matrix, and the memory transistors are arranged in a matrix. The memory cell array includes a refractory metal silicide formed on the surface of the source diffusion region or the surface of the diffusion wiring region connected to the source-diffusion region. Also,
In the present invention, titanium silicide can be used as the refractory metal silicide, which is particularly desirable in terms of manufacturing and properties.

Furthermore, in the present invention, the same material as the high melting point silicide formed on the surface of the source diffusion region or the surface of the diffusion wiring region connected to the source diffusion region is used as a polycrystalline material constituting the gate of the mesori transistor. It can be formed on the silicon surface (ie, on the word lines in the array).

(Effects of the Invention) By forming high melting point metal silicide on the surface of the impurity diffusion region of the semiconductor substrate, the diffusion ttiiortb resistance is reduced to about 1/1O. By using such a low-resistance arrangement, the common source arrangement can achieve the same resistance value of 1! When forming a layer, there is an advantage that it can be formed with a narrow wiring layer width compared to forming only an impurity diffusion layer. That is, the degree of integration of the cell array can be improved.

(Embodiment 1) FIG. 1 shows a plan view of a memory cell array according to a preferred embodiment of the present invention. In this embodiment, an N-channel floating gate type memory transistor is used as the memory transistor. Further, in this embodiment, titanium silicide is used as the high melting point metal silicide. Titanium silicide has the highest layer resistance among commonly used high-melting point metal silicides, so its use can provide a very remarkable effect.

In FIG. 1, a titanium silicide layer 1 is formed on a slit in the center of the surface of the source common diffusion layer wiring SL. The diffusion region used here is formed by ion implantation of arsenic, which is an N-type impurity, and has a layer resistance Fi of 30Ω/hole. In contrast, the layer resistance of the titanium silicide layer was 2Ω/hole.

In FIG. 1, as in the conventional source common diffusion layer wiring 8L,
When making only an arsenic diffusion layer, the source additional resistance is 5
In order to suppress the resistance to 00Ω or less, the width of the diffusion layer SL is 4 μm, and the distance J from the source of the memory transistor to the connection contact hole 2 with the aluminum ground line GL is approximately 67 μm.
It must be done within m. On the other hand, in this embodiment, in order to suppress the source added resistance to the same 5000 or less, the diffusion layer SL
The width of the titanium silicide layer is 2 μm, and the slit-shaped titanium silicide layer l
Assuming that the width of is 1 μm, the distance from the source of the memory transistor to the contact hole 2 with the ground line GL is 250 μm.
It is possible to do this. That is, compared to the conventional method, the width of the source common diffusion layer wiring can be reduced from 4 μm to 2 μm, and the distance between the source of the memory transistor and the aluminum ground line can be increased by about 4 times. Therefore, the number of ground lines in the cell array can be reduced. This power reduction effect becomes more pronounced as the number of bits increases and the size of the cell array increases.

Next, regarding the method for manufacturing the cell array of this example, Section C-2 will be explained.
This will be explained using figures. FIG. 2 shows a sectional view taken along line a-a/ in FIG. 1. A gate oxide film 22 is formed on a P-type silicon semiconductor substrate 21. Polysilicon floating gate electrode 23. An intergate insulating film 24 and a polysilicon control gate electrode 25 are sequentially formed, and then a drain 26 . A source and source common diffusion layer wiring region 27 is formed by arsenic ion implantation, and a silicon oxide film 28 covers the surface of the memory transistor and the diffusion region. The steps up to this point can be manufactured by any known method, so the details will be omitted.

Next, using PR as a mask, a slit 29 is formed in the silicon oxide film 28 on the source common diffusion layer wiring region 27 by a normal etching method, and then titanium, which is a high melting point metal, is deposited to a thickness of 100 OA. Although titanium can be deposited by various methods, in this example, ViDC sputtering is used. Thereafter, by annealing in a nitrogen atmosphere at 600 C, titanium silicide is formed only on the silicon surface in the slit 29 where silicon and titanium are in direct contact. Next, unreacted titanium is removed using an etching solution containing ammonia and hydrogen peroxide, leaving a titanium silicide layer 30 in the slit 29. Next, by performing a heat treatment at 900C, the titanium silicide layer 30 is made uniform and becomes a stable layer having a layer resistance of about 2Ω/gate. Subsequent passivation layer formation,
Steps such as forming a contact hole and forming an aluminum wiring layer can be performed by a conventional method.

(Embodiment 2) In this embodiment, a memory cell array in which the same titanium silicide layer is formed on the source common diffusion layer wiring region and the polysilicon word line will be described. The plan view of this embodiment is the same as that of FIG. 1, but the only structural difference is that a titanium silicide layer is formed on the surfaces of the polysilicon word lines W1 to W3 in FIG. 1. The manufacturing method will be explained using FIG. FIG. 3 is a sectional view taken along line a-a' in FIG. 1, similar to FIG. 2.

A gate oxide film 22 , a polysilicon floating gate electrode 23 and an inter-gate insulating film 24 are formed on a silicon semiconductor substrate 21 .
form. Next, the polysilicon control gate electrode 25 is patterned using the silicon nitride film 31 as a mask to obtain the pattern shown in FIG. 3 (al).

Next, the drain 26 and the source and source common diffusion regions 27 are formed by arsenic ion implantation. Using the silicon nitride #31 as a mask, a silicon oxide film 28 is formed on the side surfaces of the memory transistor and the surface of the diffusion region by thermal oxidation.

Then by removing silicon nitride J[31,
Figure 3 (obtain bl.

The subsequent steps are exactly the same as those described in Example 1. However, in this embodiment, since the deposited titanium is also in direct contact with the control gate polysilicon 25, a titanium silicide layer 32 of polysilicon is finally formed on the polysilicon 25 as shown in FIG. Obtain C1.

The titanium silicide layer 32 of polysilicon thus formed also has a layer resistance of about 20/hole.

Furthermore, in this embodiment, as described above, the surfaces of the common source diffusion wiring region and the polysilicon word line are simultaneously silicided with the same material, resulting in a memory cell array with low resistance. In this way, by forming refractory metal silicide, which is the same material as the surface of the source common diffusion layer wiring, on the gate polysilicon surface in the memory cell array, it is possible to simultaneously increase switching speed and high integration without increasing the number of steps. realizable.

In the above two embodiments, titanium silicide was used as the refractory metal silicide, but good results can also be obtained using molybdenum silicide, platinum silicide, chromium silicide, or the like.

As described in detail above, according to the present invention, by lowering the layer resistance of the source common diffusion layer wiring in the memory cell array, the resistance added between the source of the memory transistor and the ground potential can be increased. It is possible to increase the integration density of memory transistors in play.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a preferred embodiment of the present invention, FIG. 2 is a cross-sectional view taken along line a-a' in FIG. 1, FIG. 3 is a cross-sectional view of a second embodiment of the present invention, and FIG. is a circuit diagram of a 2×2 matrix memory cell array. 1.30.32...Titanium silicide layer, 2.
...Contact hole, 21...Silicon substrate, 2
2...Gate oxide film, 23...Floating gate electrode, 24...Inter-gate insulating film, 25...
・Control gate electrode, 26...Drain, 27.
...Source and source common diffusion layer wiring region, 28
...Silicon oxide film, 29...Slit, 3
1...Silicon nitride film. Camellia 1? Or number? figure

Claims (3)

[Claims] (1) On a semiconductor substrate, MOS type nonvolatile memory transistors that perform writing by flowing a current between the source and drain are arranged in a matrix, and are connected to the surface of the source diffusion region of the memory transistor or the source diffusion region. A nonvolatile semiconductor memory device characterized in that a high melting point metal silicide is formed on the surface of a diffusion wiring region. (2) The nonvolatile semiconductor memory device according to claim 1, wherein the high melting point metal silicide is titanium silicide. (3) The gate of the MOS type nonvolatile memory transistor is formed of polycrystalline silicon, and the surface of the polycrystalline silicon and the surface of the source diffusion region or the surface of the diffusion wiring region connected to the source diffusion region are made of the same high-melting point metal. Claim 1 characterized in that it is formed of silicide.
The non-volatile semiconductor memory device described in 2.