KR19990002554A - Manufacturing Method of Flash Memory Array Device - Google Patents

Abstract

The present invention relates to a method of manufacturing a flash memory array device having a common source region. Since the silicide film is formed on the common source region to reduce the resistance of the common source region, the circuit design is made constant by the constant Vt of each cell. Facilitates, and enables multi-bit programming.

Description

Manufacturing Method of Flash Memory Array Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash memory array device. In particular, in a flash memory array device having a common source region, a silicide film is formed on the common source region to reduce the sheet resistance and contact resistance of the common source region, thereby being applied to each cell. The present invention relates to a method of manufacturing a flash memory array device having a constant source voltage, which is easy to design a circuit, and is multi-bit programmable.

Generally, a memory device such as an electrically erasable programmable ROM (hereinafter referred to as E2PROM) capable of electrically writing and erasing data is called a flash memory. In the case of a stack gate type of the flash memory, There is a floating gate interposed between the gate and the gate oxide film. When a high voltage in the forward direction is applied to the upper gate electrode and the drain, electrons having high energy are generated near the drain. The hot carrier injection effect is injected into the floating gate over the potential barrier of the thin gate underlayer. It is injected into the floating gate beyond the potential barrier of the oxide film injected into the floating gate. According to the amount of charge injected into the floating gate, the threshold voltage of the transistor is changed to write data. In addition, when a reverse voltage is applied to the gate electrode and the drain, electrons injected into the floating gate are F-N tunneled to the semiconductor substrate to erase the stored data.

Such a flash memory has to be formed thin enough so that the gate oxide layer on the floating channel through which writing and erasing is performed can tunnel the charges, and the characteristics such as the punch-through of the transistor and the threshold voltage should also be considered.

1 is a circuit diagram of a general NOR flash memory array device, in which each cell is connected to one common source contact through a resistor (R).

Since the common source region is formed by diffusion of impurities, the resistance is very high as compared with a metal layer such as A1. For example, in the case of A1, which is frequently used as the first metal wiring, the sheet resistance is 60 mΩ, whereas in the case of N + diffusion, the resistance is about 1000 times or more. Therefore, considering that the magnitude of the current flowing to program one cell is about 400 μA, the difference between the voltage delivered to the cell closest to the cell farthest from the common source contact of FIG. 1 is about 0.6V. In this case, since the voltage of the common source is different for each cell, the time taken for programming of each cell is different, or when programming for the same time, the Vt value of each cell is different.

The difference in Vt values between the cells prevents Vt from having a uniform distribution in the entire cell array, making it difficult to design a circuit, and distributes Vt values in a wide area to store multiple bits in one cell. There is a problem that makes bit programs difficult.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to form a silicide film on a common source of a flash memory array device having a common source contact, thereby reducing the resistance of the common source to facilitate the design of the circuit. A method of manufacturing a multi-bit programmable flash memory array device is provided.

1 is a circuit diagram of a typical flash memory array element.

2A to 2D are manufacturing process diagrams of a flash memory array device according to the present invention.

3 is a cross-sectional view taken along line II of FIG. 2D.

4 is a cross-sectional view taken along the line II-II of FIG. 2D;

* Description of the symbols for the main parts of the drawings *

10 semiconductor substrate 12 device isolation oxide film

13 gate oxide film 14 first polycrystalline silicon layer

15: interlayer insulating film 16: upper gate electrode

17 second polycrystalline silicon layer 18 W-silicide film

20: lower gate electrode 22: photosensitive film pattern

24: N + common source region 26: oxide spacer

28: silicide film 30: N + drain

A feature of the flash memory array device manufacturing method according to the present invention for achieving the above object is to form a device isolation oxide film, a lower gate and an upper gate on a semiconductor substrate of the first conductive type, a common source in the semiconductor substrate And a step of forming a diffusion region with a second conductivity type impurity on a portion intended to be a region, and a step of forming a silicide film on the diffusion region.

Hereinafter, a method of manufacturing a flash memory array device according to the present invention will be described in detail with reference to the accompanying drawings.

2A to 2D are manufacturing process diagrams of a flash memory array device according to the present invention, and are layout diagrams. Since the two partial cross-sections of FIG. 2D are FIGS.

First, a device isolation oxide film 12 is formed on a first conductive type, for example, a P-type semiconductor substrate 10 so that the device isolation region and the active region cross in parallel, and then the gate oxide film 13 is formed on the active region. After the formation, a first polycrystalline silicon layer 14 pattern is formed on the gate oxide layer 13. In this case, the first polycrystalline silicon layer 14 is formed in a horizontally extending straight shape in which both ends of the device isolation oxide layer 12 overlap each other.

Next, an interlayer insulating film 15 is formed on the entire surface of the structure, and a plurality of upper gate electrodes 16 extending in a vertical direction thereon are formed of the second polycrystalline silicon layer 17 pattern and the W-silicide film 18. ) To form a laminated structure of patterns. (See FIG. 2A).

Subsequently, the lower gate 20 is formed by using the upper gate electrode 16 as a mask to etch the first polycrystalline silicon layer 14 below the self-alignment so that only the lower portion of the upper gate electrode 16 remains below the upper gate electrode 16. (See FIG. 2B).

A photoresist pattern 22 is then formed on the semiconductor substrate 10 to cover a portion scheduled for bit line contact and an area of the element isolation oxide film 12 for separating the semiconductor substrate 10, and is exposed by the photoresist pattern 22. The semiconductor substrate 10 is exposed by sequentially removing the interlayer insulating film 15 and the device isolation oxide film 12, and then ion implanted at a high concentration in a second conductivity type, for example, an N-type impurity, to form an N + common source region ( 24). (See FIG. 2C).

Thereafter, the photoresist layer pattern 22 is removed, and an oxide spacer 26 is formed on sidewalls of the upper gate electrode 16 and the device isolation oxide layer 12, and then on the N + common source region 24. The silicide film 28 is formed of one of Ti, Ta, Cr, and Mo, for example. Although the silicide layer 28 is formed on the W-silicide layer 18 pattern, the silicide layer 28 is not illustrated, and the upper gate electrode 16 is formed to prevent diffuse reflection when the W-silicide layer 18 is patterned. The process may be performed in a state where the nitride film is formed on the silicide film 18 by about 500 Å. In this case, the nitride film pattern is present on the W-silicide film 18 pattern so that the silicide film 28 is not formed at the portion thereof. Do not. The silicide film 28 is also formed on the N + drain 30. (See FIG. 2D).

Although not shown, a subsequent metallization process is performed to complete the flash memory array device.

As described above, in the method of manufacturing the flash memory array device according to the present invention, since the silicide film is formed on the common source region to reduce the resistance of the common source region, the voltage drop occurring at the common source is minimized to minimize the Vt of each cell. The constant has the advantage of facilitating the design of the circuit and enabling multi-bit programming.

Claims (3)

A method of manufacturing a flash memory array device comprising the step of forming a device isolation oxide film, a lower gate, an upper gate, and a common source region on a first conductive semiconductor substrate. Forming a diffusion region of a second conductivity type impurity on a portion of the semiconductor substrate which is intended to be a common source region; And forming a silicide film on the diffusion region. 2. The method of claim 1, wherein the first and second conductivity types are opposite P and N or N and P types. The method of claim 1, wherein the silicide layer is formed of one of Ti, Ta, Cr, and Mo.