KR100976673B1 - Flash memory device and Manufacturing method thereof - Google Patents

Abstract

In an embodiment, a flash memory device may include: first and second gate stacks formed on a semiconductor substrate; Spacers formed on sidewalls of the first and second gate stacks; An RCS region formed between the first and second gate stacks; A drain region formed on one side of the first and second gate stacks; And a salicide layer formed in the RCS region.

Flash Memory, Gate Stack, Common Source Line

Description

Flash memory device and manufacturing method thereof

The embodiment relates to a flash memory device and a method of manufacturing the same.

Semiconductor memory devices are classified into volatile memory and nonvolatile memory. Most of volatile memory is occupied by RAM such as DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory), and it is possible to input and save data when power is applied, but it is impossible to save data by volatilization when power is removed. Has On the other hand, nonvolatile memory, which occupies most of read only memory (ROM), is characterized in that data is preserved even when power is not applied.

In general, a flash memory device is manufactured by taking advantage of EPROM having programming and erasing characteristics and EEPROM having electrical programming and erasing characteristics.

The flash memory device includes a floating gate in which data is stored, a tunnel oxide film formed between the floating gate and the substrate, a control gate serving as a word line, and a dielectric film formed therebetween to separate the control gate and the floating gate. And a spacer having an ON structure to isolate and protect the gate stack. Thereafter, the spacer includes a source / drain region formed by ion implantation using the spacer as a mask.

In particular, the source region of the flash memory device applies a common source line made of an impurity diffusion layer through a self aligned source (SAS) process.

Specifically, in the SAS process, a source oxide of a cell is opened using a separate SAS mask in a state in which a gate stack having a stacked structure is formed, and then a field oxide layer is formed to form a common source line with an adjacent cell. Refers to the process of performing anisotropic etching to remove.

This SAS technology shrinks the size of the cell in the direction of the bit line BL, which has become an essential process in recent years because the gate to source space can be reduced. . However, since the common source line is formed along the trench profile in the memory cell to which the SAS technology is applied, the contact resistance of the source per cell is rapidly increased.

Junction is widely used as a source line of the flash memory as described above, and in the conventional method of forming the source line, the junction is formed by ion implantation into a recessed common source. The method is widely used.

However, since the source line formed as the junction generally supplies one current by forming one source contact for each of 16 to 24 cells, the current line has a high electric resistance for each cell, so the loss of the current is large.

In addition, in order to solve voids when depositing a PMD layer (metal insulating film), an ON structure spacer is used. In particular, after the addition of a Nitride (SBN) spacer process, the nitride and oxide layers can be removed at the same time in non-salicide patterning. This method has a problem in that a ridge key current is generated because the channel is shortened by a thermal budget in the SBN process.

The embodiment provides a flash memory device capable of forming a common source line by changing a spacer structure to an NO structure and salicided an RCS region, and a method of manufacturing the same.

In addition, by opening the RCS region during the non-salicide process and performing the salicide process for the RCS region, a salicide layer is formed on a common source line to simplify the process and reduce power consumption, thereby improving performance. A flash memory device and a method of manufacturing the same are provided.

In an embodiment, a flash memory device may include: first and second gate stacks formed on a semiconductor substrate; Spacers formed on sidewalls of the first and second gate stacks; An RCS region formed between the first and second gate stacks; A drain region formed on one side of the first and second gate stacks; And a salicide layer formed in the RCS region.

A method of manufacturing a flash memory device according to an embodiment may include forming first and second gate stacks on a semiconductor substrate; Forming an RCS region to be used as a common source line between the first and second gate stacks; Forming preliminary spacers on sidewalls of the first and second gate stacks; Forming a drain region on one side of the first and second gate stacks; Performing a non-salicide process on the semiconductor substrate to form a spacer and a salicide predetermined region and to expose the RCS region; And forming a salicide layer in the RCS region to form a common source line.

According to the flash memory device and the manufacturing method thereof according to the embodiment, the salicide layer is formed on the common source line of the gate stack to lower the contact resistance, thereby reducing power consumption and improving device performance.

In addition, the ion implantation process for the RCS region is omitted when the common source line is formed, and since the RCS region is opened in the non-salicide process, salicide is formed in the RCS region in the salicide process, thereby simplifying the process.

In addition, when the spacer layer of the gate stack is formed, the nitride layer-oxide layer spacer layer is formed and then etched to prevent short channel phenomena of the device, thereby reducing the solution.

In addition, the gap fill margin of the interlayer insulating layer may be improved by forming a spacer using the nitride film oxide layer structure.

A flash memory device and a method of manufacturing the same according to an embodiment will be described in detail with reference to the accompanying drawings.

In the description of the embodiments, where described as being formed "on / over" of each layer, the on / over may be directly or through another layer ( indirectly) includes everything formed.

In the drawings, the thickness or size of each layer is exaggerated, omitted, or schematically illustrated for convenience and clarity of description. In addition, the size of each component does not necessarily reflect the actual size.

9 is a cross-sectional view of a flash memory device according to an embodiment.

In an exemplary embodiment, a flash memory device may include first and second gate stacks 110 and 120 formed on a semiconductor substrate 100; Spacers 191 formed on sidewalls of the first and second gate stacks 110 and 120; An RCS region 140 formed between the first and second gate stacks 110 and 120; Drain regions 155 formed on one side of the first and second gate stacks 110 and 120; And a salicide layer 210 formed in the RCS region 140.

The spacer 191 is formed of the HTO pattern 161 and may be formed to a thickness of about 50 ~ 100Å. Since the spacer 191 is formed to have a thin thickness on the sidewalls of the first and second gate stacks 110 and 120, the interlayer insulating layer 220 is also voided between the first and second gate stacks 110 and 120. It may be gapfilled without insulation to insulate the first and second gate stacks 110 and 120.

The salicide layer 210 may be formed on the surfaces of the first and second gate stacks 110 and 120 and the surfaces of the drain region 155.

In the flash memory device according to the embodiment, since the salicide layer 210 is formed on the common source line of the first and second gate stacks 110 and 120, the contact resistance may be reduced, thereby improving the performance of the device.

Unexplained reference numerals among the reference numerals of FIG. 7 will be described in the following manufacturing method.

Hereinafter, a method of manufacturing a flash memory device according to an embodiment will be described in detail with reference to the accompanying drawings.

1 to 7 are cross-sectional views illustrating a manufacturing process of a flash memory device according to an embodiment. In an embodiment, two first and second gate stacks 110 and 120 forming a unit cell are formed on the semiconductor substrate 100, respectively. Since the first and second gate stacks 110 and 120 have the same shape, the same reference numerals are used for the components of the first and second gate stacks 110 and 120. Since the logic region B is also formed when the cell region A is formed, it is also shown in the drawing.

Referring to FIG. 1, first and second gate stacks 110 and 120 are formed on a semiconductor substrate 100. The first and second gate stacks 110 and 120 function as a floating gate 113 in which data is stored, a tunnel oxide layer 111 formed between the floating gate 113 and the semiconductor substrate 100, and a word line. And a dielectric film 115 formed between the control gate 117 and the control gate 117 and the floating gate 113. Here, the semiconductor substrate 100 is in a state in which the device isolation film 105 is formed, wells are formed, and a channel forming process is completed. In addition, the dielectric layer 115 may be formed of an oxide-nitride-oxide (ONO) structure.

Meanwhile, the polysilicon layer for forming the control gate 117 is formed on the entire surface of the semiconductor substrate 100 and may be deposited on the cell region A and the logic region B together. Thereafter, the polysilicon layer of the cell region A may be patterned to form the control gate 117, and the polysilicon layer of the logic region B may be patterned to form the gate electrode 130 of the transistor.

Next, a recess common source (RCS) region is formed between the first gate stack 110 and the second gate stack 120. The RCS region 140 may be used as a common source line of a unit cell.

Although not shown, the RCS region 140 forms a photoresist pattern on the semiconductor substrate 100 to expose the active region and the device isolation layer between the first and second gate stacks 110 and 120. Thereafter, an oxide film forming the device isolation film may be removed by a RIE (responsive ion etching) process for the device isolation film 105. Thereafter, the photoresist pattern may be generally removed through an asher process and a cleaning process. Therefore, the RCS region 140 may be formed to have a step difference between the active region and the trench T. FIG.

Referring to FIG. 2, LDD regions 150 are formed in both sides of the first and second gate stacks 110 and 120 and in the RCS region 140. The LDD region 150 may be formed by ion implanting low concentration impurities (N-type or P-type impurities) into the semiconductor substrate 100 corresponding to both sides of the first and second gate stacks 110 and 120. .

Meanwhile, the LDD region 150 may be formed at both sides of the gate electrode 130 of the logic region B.

Referring to FIG. 3, a spacer layer 190 is formed on a semiconductor substrate 100 including the first and second gate stacks 110 and 120. In particular, the spacer layer 190 may be formed to fill all of the upper region of the RCS region 140 between the first and second gate stacks 110 and 120. The upper portion of the RCS region 140 corresponding to the first and second gate stacks 110 and 120 has a narrower space than the other regions between the first and second gate stacks 110 and 120. The region may be in a state where all of the spacer layer 190 is covered.

For example, the spacer layer 190 may have a structure in which a high temperature oxide (HTO) layer 160, a nitride layer 170, and an oxide layer 180 (TEOS) are stacked. The HTO layer 180 may have a thickness of 50 to 100 kPa, the nitride film 170 may be 150 to 250 kPa, and the oxide film 180 may have a thickness of 500 to 1000 kPa.

In general, since the deposition temperature of the nitride film is 700 ° C. and the deposition temperature of the oxide film is 650 ° C., when the nitride film 170 is formed in a thin thickness, impurities forming the LDD are less affected by thermal, and thus the short channel ( short channel) can be prevented. In the conventional spacer having an ON structure, since the oxide film is 200 Å and the nitride film is 770 두께 thick, when the high temperature is applied during the formation of the nitride film, impurities may be laterally diffused and the channel may be shortened. 190 is formed in the NO structure and the thickness of the nitride film 170 is formed thin to prevent the soak channel phenomenon to reduce the leakage current (leakage current).

Referring to FIG. 4, spacers 191 are formed on both sidewalls of the first and second gate stacks 110 and 120. The spacer 191 may be formed on both sidewalls of the first and second gate stacks 110 and 120 by performing an entire surface etching process on the spacer layer. The spacer 191 may be formed of the HTO pattern 161, the nitride film pattern 171, and the oxide film pattern 181.

Since the front surface etching process is an anisotropic etching process, spacers 191 may be formed only on sidewalls of the first and second gate stacks 110 and 120. In particular, the spacer layer 190 corresponding to the RCS region 140 is less etched than other regions, so that the RCS region 140 is completely covered by the spacer 191.

That is, the spacer layer 190 on the upper surfaces of the first and second gate stacks 110 and 120 are removed by the etching process, and both sidewalls of the first and second gate stacks 110 and 120 are removed. The spacer layer 190 may remain selectively to form the spacer 191, and the nitride layer pattern 171 may be exposed on the surface of the semiconductor substrate 100.

Since the etch rate varies depending on the density of the devices formed on the semiconductor substrate 100, the first and second gate stacks 110 and 120 may remove the spacer layer 190 on the surfaces of the first and second gate stacks 110 and 120. And the sidewalls of the second gate stacks 110 and 120 and the spacer layer 190 of the semiconductor substrate 100 may optionally remain.

Referring to FIG. 5, source / drain regions 155 are formed in the semiconductor substrate 100 corresponding to both sides of the first and second gate stacks 110 and 120. The source / drain region 155 is formed to be connected to the LDD region 150 by ion implanting high concentration impurities (N-type or P-type impurities) into the semiconductor substrate 100 using the spacer 191 as a mask. can do. In addition, a junction is formed by performing a heat treatment process to activate the dopant implanted into the source / drain region 155. In this case, since the RCS region 140 corresponding to the common source region of the first and second gate stacks 110 and 120 is completely covered by the spacer 191, impurities are not injected or compared with other regions. It may be in a shallow injection state.

Meanwhile, when forming the source / drain region 155 of the cell region A, source / drain regions may be formed on both sides of the gate electrode 130 of the logic region B.

Referring to FIG. 6, a mask pattern 200 for a non-salicide region is formed on the semiconductor substrate 100. The mask pattern 200 may be formed of PE-TEOS. The mask pattern 200 may be formed by selectively etching the PE-TEOS by a photosensitive film to expose only a region for forming a salicide after depositing the PE-TEOS.

In an embodiment, the mask pattern 200 may be formed on the gate electrode 130 of the logic region B. Meanwhile, the region in which the mask pattern 200 is formed is only one embodiment, and the mask pattern 200 may be selectively formed in other regions such as the gate stacks 110 and 120 and the drain region 155.

Referring to FIG. 7, surfaces of the first and second gate stacks 110 and 120, the RCS region 140, and the semiconductor substrate 100 may be selectively exposed by the mask pattern 200. The surface of the RCS region 140 and the contact plan region may be exposed by removing the insulating layers of the regions other than the gate electrode 130 by using the mask pattern 200 as an etching mask.

As described above, the RCS region 140 corresponding to the common source line may be exposed by a non-salicide process.

Referring to FIG. 8, a salicide layer 210 is formed on surfaces of the first and second gate electrodes 110 and 120, the RCS region 140, and the source / drain region 155. The salicide layer 210 formed in the RCS region 140 may serve as a common source line.

The salicide layer 210 may be formed by depositing a metal film such as nickel, tungsten, titanium, or cobalt in an area exposed by the mask pattern 200 by a rapid thermal process. The salicide layer 210 is formed by the reaction between the metal layer and the lower silicon portion, thereby lowering the contact resistance between the device and the wiring.

In an embodiment, after forming the spacer 191, the common source line may be salicided by opening the RCS region 140 in the non-salicide etch process. That is, the ion implantation process for the RCS region for forming the existing common source line is omitted, and the insulating films and the RCS region 140 are simultaneously opened in the non-salicide process to save the common source line without additional processing. Since the side layer 210 is formed, the process can be simplified.

In addition, since the common source line is salicided, the contact resistance of the common source line is lowered, thereby reducing power consumption and improving device performance.

Subsequently, as shown in FIG. 9, after removing the mask pattern 200, an interlayer insulating layer (PMD) 220 is formed on the semiconductor substrate 100 including the first and second gate stacks 110 and 120. This can be formed. Although not shown, a contact plug may be formed through the interlayer insulating layer 220 to be connected to the RCS region 140 and the drain region 155.

Since only the HTO pattern 161 remains as a spacer between the first and second gate stacks 110 and 120, a gap-fill margin of the interlayer insulating layer 220 may be improved.

As described above with reference to the drawings illustrating a flash memory device and a method of manufacturing the same according to the present invention, the present invention is not limited by the embodiments and drawings disclosed herein, but within the technical scope of the present invention Of course, various modifications can be made by those skilled in the art.

1 to 9 are cross-sectional views illustrating a manufacturing process of a flash memory device according to an embodiment.

Claims (10)

delete delete delete delete Forming first and second gate stacks on the semiconductor substrate; Forming an RCS region to be used as a common source line between the first and second gate stacks; Sequentially forming an HTO layer, a nitride film, and an oxide film on the semiconductor substrate including the first and second gate stacks; Performing preliminary etching on the HTO layer, the nitride film, and the oxide film to form preliminary spacers including HTO pattern, nitride film pattern, and oxide film pattern on sidewalls of the first and second gate stacks; Forming a drain region on one side of the first and second gate stacks; Performing a non-salicide process on the semiconductor substrate to form a spacer formed of the HTO pattern, and simultaneously exposing a contact predetermined region and an RCS region; And Forming a salicide layer in the RCS region to form a common source line. The method of claim 5, And the nitride film is formed to a thickness smaller than 1/2 of the thickness of the oxide film. The method of claim 5, Forming a spacer by the non-salicide process, exposing the contact region and the RCS region, Forming a hard mask exposing a salicide region and an RCS region on the semiconductor substrate; And Removing the preliminary spacers exposed by the hard mask to simultaneously expose the surfaces, the drain regions, and the RCS regions of the first and second gate stacks. The method of claim 7, wherein And forming a salicide layer by performing a salicide process on the surfaces of the first and second gate stacks, which are the contact region, and the drain region. The method of claim 8, And a salicide layer of the RCS region is simultaneously formed when the salicide layer is formed. The method of claim 5, The method of claim 1, further comprising forming an interlayer dielectric layer on the semiconductor substrate on which the salicide layer is formed.

Images