JP4072353B2 - Semiconductor memory device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device and a manufacturing method thereof. More particularly, the present invention relates to a semiconductor memory device using a floating gate and a manufacturing method thereof, and more particularly, to a semiconductor memory device having a virtual ground cell and a manufacturing method thereof.
[0002]
[Prior art]
As is well known, an electronic memory device integrated in an EPROM, a flash EPROM and a semiconductor substrate includes a plurality of nonvolatile memory cells arranged in a matrix, that is, a plurality of rows (word lines) and a plurality of columns (bits). Line).
Each nonvolatile memory cell is composed of a MOS transistor, and the gate electrode of the MOS transistor is located above the channel region and is floating, and this electrode is called a floating gate.
The non-volatile memory cell also has a second electrode known as a control gate and is driven by a suitable control voltage. The other electrodes of the MOS transistor are a drain, a source, and a body terminal.
[0003]
In recent years, there has been a considerable effort goal to provide memory devices with increased circuit density, and therefore, contactless, electrically programmable non-volatile memory matrices that do not contact each memory cell. Has been developed. A manufacturing process for this type of matrix is described in Japanese Patent Application Laid-Open No. 2000-332139.
This contactless memory matrix requires a virtual ground circuit for read and programming operations, but the circuit area savings provided by such a structure are significant. In this virtual ground circuit memory cell, as a bit line forming means, a low-concentration impurity ion implantation and a salicide technique (a technique for forming a silicide layer by a self-alignment method) are used together to manufacture a memory cell with a further reduced size. Proposed method.
[0004]
This manufacturing method will be described with reference to FIGS. First, as shown in FIG. 4A, a gate insulating film 103 is formed on a semiconductor substrate 102, and then a gate electrode is formed. The formation of the gate electrode includes a multiple stacking process, in which the first polysilicon layer 105, the intermediate insulating layer 106, the second polysilicon layer 107, and the upper insulating layer 107a are sequentially deposited. Thereafter, the laminated structure is etched into a stripe shape by a lithography technique to form a gate electrode. In FIG. 4A, 4 denotes a gate electrode formation region, and 8 denotes an opening.
Next, as shown in FIGS. 4B and 4C, the bit line 109 is formed by performing ion implantation using arsenic for imparting N-type conductivity to the opening 8. Next, sidewall spacers 110 are formed on the sidewalls of the gate electrode, a transition metal layer (titanium layer) 111 is deposited, and heat treatment is performed to cause the transition metal layer 111 to react to form a silicide compound (titanium silicide) layer 112. Form.
[0005]
Thereafter, as shown in FIG. 4 (d), an insulating layer 113 is deposited in the opening 8, the upper insulating layer 107a on the second polysilicon layer 107 is exposed by etch back, and the upper insulating layer 107a is further removed. As a result, the upper surface of the semiconductor substrate is planarized. Next, multiple layers of a conductive layer 114 such as a polysilicon layer and a second transition metal layer 115 are formed, and then heat treatment is performed to react the second transition metal layer 115 to a silicon compound layer (silicide layer) 116. Form. Finally, the conductive layer 114 and the silicon compound layer 116 are patterned using the resist layer as a mask, and are defined as word lines in a direction crossing the bit lines.
[0006]
[Problems to be solved by the invention]
However, although this conventional technique is effective for simply siliciding the bit line, the memory cells arranged in a matrix cannot be operated efficiently.
That is, in the above-described prior art, since the two layers of polysilicon, which are part of the floating gate and the control gate, are simultaneously etched away, the gate capacitance coupling ratio cannot be increased, and the memory cell speed is increased. Or disadvantageous for lowering the voltage.
[0007]
Further, two layers of polysilicon that will become part of the floating gate and the control gate are formed by etching away simultaneously. Therefore, the peripheral circuit formation cannot be performed simultaneously with the memory cell formation, resulting in a very complicated process flow in which it is necessary to form the peripheral circuit and the memory cell separately.
Further, the second heat treatment is indispensable for the deposition of the conductive layer to be the word line and its silicidation. For this reason, even if a silicon compound layer is formed on the bit line in order to reduce resistance, damage to the silicon compound layer on the bit line cannot be completely eliminated by the second heat treatment.
Furthermore, in this prior art, there is no isolation method as a countermeasure against leakage between bits between word lines, and operation as a memory array is difficult when the element isolation is not sufficiently performed.
[0008]
[Means for Solving the Problems]
In order to solve the above problems, the present invention proposes a device having a reduced size by reducing the resistance of the bit line and the word line of the virtual ground semiconductor memory device and a method for manufacturing the same.
Thus, according to the present invention, a floating gate is provided on a semiconductor substrate via a gate insulating film, and a control gate comprising a polysilicon layer covering the upper surface of the floating gate and a part of the side wall in the channel length direction starting from the upper surface is provided. A silicide layer having diffusion bit lines on both sides in the channel length direction of the floating gate and formed in a self-aligned manner on the control gate and the diffusion bit line in a state where the surfaces of the polysilicon layer and the diffusion bit line are exposed. With at least two stacks composed of floating gates and control gates in the channel width direction, and the two stacks share a diffusion bit line extending in the channel width direction and separate the stacks in the channel width direction virtual ground type semiconductor note that comprising the trenches for Apparatus is provided.
[0009]
Furthermore, according to the present invention, there is provided a method of manufacturing the virtual ground type semiconductor memory device,
Forming at least one layer for forming a floating gate extending in a channel width direction on a semiconductor substrate via a gate insulating film;
A step of introducing a dopant into the semiconductor substrate using the floating gate forming layer as a mask to form diffusion bit lines on both sides in the channel length direction of the floating gate forming layer ;
Burying the diffusion bit line region with a first insulating layer;
Removing the first insulating layer leaving a certain thickness;
Forming a polysilicon layer so as to cover the floating gate forming layer and be insulated from the floating gate forming layer ;
Forming a resist layer covering at least the polysilicon layer corresponding to the upper surface of the floating gate desired to be formed, and removing the floating gate forming layer, the polysilicon layer and the first insulating layer using the resist layer as a mask; And a control gate made of a polysilicon layer covering a part of the side wall in the channel length direction starting from the upper surface of the floating gate, and a layered body sharing a diffusion bit line extending in the channel width direction with a channel width. Forming at least two in the direction, and then removing the resist layer;
Oxidizing the surface of the control gate, removing the oxide film on the upper surface of the control gate and the gate insulating film on the diffusion bit line, and forming a silicide layer on the removal surface by salicide ;
A method of manufacturing a virtual ground type semiconductor memory device, comprising: forming a trench for separating a stacked body in a semiconductor substrate between stacked bodies using a silicide layer on a diffusion bit line as a mask. .
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a method of manufacturing a virtual ground type semiconductor memory device of the present invention will be described with reference to FIGS. 3 is a schematic plan view of the virtual ground type semiconductor memory device of the present invention, and FIGS. 2A and 2B are schematic perspective views as seen from the extending direction of the bit line and the extending direction of the word line, respectively. 1 (a) to 1 (m) show schematic process cross-sectional views. Further, the left diagram of FIG. 1 shows the word line direction, the central diagram shows the bit line direction, and the right diagram shows a schematic sectional view of the peripheral circuit.
In the embodiments of the present invention described below, only the normally used process steps and the memory cell portion necessary for understanding the present invention will be described.
[0011]
First, as shown in FIG. 1A, a gate insulating film 12 (also known as a tunnel insulating film) is formed on a semiconductor substrate 11. Although it does not specifically limit as a semiconductor substrate, A silicon substrate, a silicon germanium substrate, etc. are mentioned, Furthermore, you may have either P type or N type conductivity type. The gate insulating film 12 is desirably a high-quality thermal oxide film (for example, a silicon oxide film) having a thickness of about 80 to 120 mm. This thickness is a typical value when applied to a flash memory device, and different values may be adopted for other device structures or applications.
[0012]
Before the gate insulating film 12 is grown, implantation for adjusting the voltage threshold may be optionally performed. The implantation for adjusting the threshold value may be a combination of low energy boron ion implantation of 30 keV to 60 keV and high energy boron ion implantation of 100 keV or more when the semiconductor substrate is P-type.
After forming the gate insulating film 12, a material layer (for example, the first polysilicon layer 13) for forming a floating gate is deposited on the semiconductor substrate. The thickness of the first polysilicon layer 13 is about 3500 mm in this embodiment, but a thicker polysilicon layer may be used depending on design conditions. In other words, the first polysilicon layer 13 may be made thicker in order to increase the capacitive coupling to the control gate, which is an effect of the present invention, to the process range limit of the process.
[0013]
Next, as shown in FIG. 1B, the photoresist mask layer 14 is patterned using a lithography technique, the first polysilicon layer 13 is removed by etching, and then the photoresist mask layer 14 is peeled off. The first polysilicon layer 13 in this process becomes a floating gate in one cell (memory cell) of the memory device. Further, a dopant (for example, arsenic) is introduced (ion implantation) under conditions of 20 to 50 keV and 2E13 to 2E14 cm ⁻² to form a bit line 15 having low to medium concentration impurities and a shallow junction depth.
Next, as shown in FIG. 1C, an insulating layer (for example, oxide film 16) is deposited by, eg, CVD, and then etched back to fill the space between the first polysilicon layers 13 with an insulating layer. .
[0014]
Next, as shown in FIG. 1D, the oxide film 16 is further etched back to expose a part of the upper portion and the side surface of the first polysilicon layer 13. At this time, the thickness of the oxide film 16 on the semiconductor substrate 11 is about 1000 mm, but it may be made thicker or thinner depending on design conditions. In other words, the thickness of the oxide film 16 can be adjusted in order to increase the capacitive coupling to the control gate, which is an effect of the present invention, up to the process range limit of the process.
[0015]
Next, as shown in FIG. 1E, for example, a silicon dioxide layer is formed on the first polysilicon layer 13 in order to insulate the first polysilicon layer 13 and the second polysilicon layer. The dielectric layer 17 having a nitride / oxide (ONO) laminated structure can be formed. The dielectric layer 17 preferably has a laminated structure of ONO. The film thickness of the dielectric layer 17 is desirably about 180 mm.
Next, as shown in FIG. 1 (f), a second polysilicon layer 18 is deposited on the dielectric layer 17. The film thickness of the second polysilicon layer 18 is about 3000 mm, and this film thickness can be optimized according to the design conditions and the process range of the process.
[0016]
Next, as shown in FIG. 1G, the photoresist mask layer 19 is patterned by a lithography technique, and the second polysilicon layer 18 / the dielectric layer 17 / the oxide film 16 / the gate insulating film 12 are patterned. Are sequentially removed by etching, and then the photoresist mask layer 19 is peeled off. In this step, the gate insulating film 12 is not necessarily completely removed. The second polysilicon layer 18 in this step becomes a part of the control gate in the memory cell and also becomes the gate electrode 26 of the peripheral circuit.
[0017]
In the present invention, the control gate has a three-dimensional structure that covers the upper surface of the floating gate and part of the side wall in the channel width direction starting from the upper surface. By having such a structure, it is possible to improve the gate capacitance coupling ratio for speeding up the memory cell operation / reducing the voltage.
Next, as shown in FIG. 1H, oxidation is performed to form an oxide film 20 on the surface of the second polysilicon layer 18 and the surface of the bit line 15. The thickness of the oxide film 20 is such that the side surface of the second polysilicon layer 18 is not silicided by a salicide process (self-aligned silicide) in a later process step, and is preferably about 200 mm. The film thickness can be optimized according to the design conditions and the process range of the process.
Next, as shown in FIG. 1I, the bit line between the uppermost surface of the second polysilicon layer 18 and the second polysilicon layer 18 is formed on the oxide film 20 by using anisotropic etching. 15 surfaces are exposed.
[0018]
Next, as shown in FIG. 1 (j), a transition metal layer is deposited. Examples of the transition metal include titanium and cobalt. Heat treatment is performed to form the silicide layer 21 in the portion where the semiconductor layer is exposed and in contact with the transition metal layer. For example, when titanium is used as a transition metal, sputtering is performed at a thickness of 200 mm, for example, and then a heat treatment is performed at 600 ° C. for about 10 seconds to form a silicide film of C49 which is a high resistance phase. Further, unreacted titanium is removed with sulfuric acid and hydrogen peroxide water, and a low resistance phase silicide layer 21 of C54 is obtained by heat treatment at 800 ° C. for about 60 seconds.
[0019]
Next, as shown in FIG. 1 (k), after depositing an insulating layer (for example, oxide layer 22) by CVD, mechanical chemical polishing is performed by etch back or CMP (Chemical Mechanical Polishing), An oxide layer 22 is embedded between the second polysilicon layers 18. At this time, generally, the CMP method is used to polish the oxide layer 22 to the surface of the silicide layer 21 on the second polysilicon layer 18, and as a polishing stopper during the CMP process, a silicide made of the metal transition layer is used. Layer 21 is used. At this time, the silicide layer 18 on the second polysilicon layer 18 is not completely removed but remains on the second polysilicon layer even after polishing.
Next, as shown in FIG. 1L, with the silicide layer 21 on the second polysilicon layer 20 exposed, a metal conductive layer 23 made of, for example, a TiN / AlCu / TiN laminated film is sputtered. Form. At this time, the silicide layer 21 remaining on the second polysilicon layer prevents the contact with the metal conductive layer 23 from being a Schottky connection or the like.
[0020]
Next, as shown in FIG. 1 (m), a photoresist mask layer 24 is patterned on the metal conductive layer 23 so as to cross the bit line 15 by lithography, and the metal conductive layer 23 / silicide layer 21 / second layer is patterned. The second polysilicon layer 18 / dielectric layer 17 / first polysilicon layer 13 / gate insulating film 12 are removed by etching. Further, after etching the semiconductor substrate under the floating gate between the word lines, the photoresist mask layer 24 is peeled off. Thereby, a word line is formed. At this time, in order to prevent memory cells adjacent in the bit line direction from leaking, in the bit line region between the word lines, the silicide film 21 in contact with the diffusion bit line 15 is used as an etching barrier film, and a non-silicide region (bit line and word The region surrounded by the line is taken as a countermeasure against leakage by separating the trench element by etching the semiconductor substrate. That is, by using trench isolation without implanting element isolation, the impurity layer activation annealing process by ion implantation becomes unnecessary, and damage to the silicide can be suppressed. Thus, element isolation can be performed without causing thermal damage to the silicide layer 21 on the diffusion bit line 15 and the upper surface of the second polysilicon 18. Thereafter, the word lines are filled with an insulating film, element isolation is completed, and the semiconductor memory device of the present invention is provided by forming an interlayer insulating layer, forming a contact hole, forming an aluminum electrode, and the like according to a normal process.
[0021]
The present invention is not limited to the above-described embodiment, and it is possible to simultaneously form a peripheral circuit during the process of the above-described embodiment.
For example, referring to FIG. 1, the gate insulating film 25 for the peripheral circuit is formed between FIGS. 1E and 1F, and the second polysilicon layer 18 for the memory cell is further formed in FIG. Is used to form the gate electrode 26 of the peripheral circuit.
The source / drain region 27 is formed by source / drain implantation and activation annealing after polysilicon oxidation in FIG.
Further, as shown in FIGS. 1H and 1I, the gate side spacer for preventing the gate electrode 26 and the source / drain region 27 of the peripheral circuit from being short-circuited by the silicide process in the later step is oxidized and anisotropic as in the memory cell. It is formed by etch back.
Thereafter, a silicide layer 28 is formed on the surfaces of the gate electrode 26 and the source / drain regions 27 as shown in FIG. Thereby, a peripheral circuit can be formed simultaneously with the memory cell formation process.
[0022]
【The invention's effect】
Thus, according to the present invention, it is possible to increase the capacitive coupling to the control gate using the side surface of the floating gate, and the memory cell array area can be reduced. Further, according to the present invention, the high temperature treatment by the final polysilicon deposition and the heat treatment for forming the final silicide film in the prior art causes damage to the silicide layer on the bit line, but this can be completely avoided. Further, according to the present invention, it is possible to form a peripheral circuit simultaneously with the formation of the memory array, and further, it is possible to form isolation between the bits between the word lines without damage to the silicide.
[Brief description of the drawings]
FIG. 1 is a schematic process cross-sectional view of an embodiment of the present invention.
FIG. 2 is a schematic perspective view of the apparatus of the present invention.
FIG. 3 is a schematic plan view of the apparatus of the present invention.
FIG. 4 is a schematic process cross-sectional view of a conventional apparatus.
[Explanation of symbols]
4 Gate electrode formation region 8 Opening 11, 102 Semiconductor substrate 12, 25, 103 Gate insulating film 13, 105 First polysilicon layer 14, 19, 24 Photoresist mask layer 15, 109 Bit line 16, 20 Oxide film 17 Dielectric layers 18, 107 Second polysilicon layer 21, 28 Silicide layer 22 Oxide layer 23 Metal conductive layer 26 Gate electrode 27 Source / drain region 106 Intermediate insulating layer 107a Upper insulating layer 110 Side wall spacer 111 Transition metal layer 112, 116 Silicide compound layer 113 Insulating layer 114 Conductive layer 115 Second transition metal layer

Claims (6)

Comprising a floating gate via a gate insulating film on a semiconductor substrate, comprising a top surface and a control gate made of the polysilicon layer covering a portion of the channel length direction of the side wall starting from the upper surface of the floating gate, the channel length direction of the floating gate A diffusion bit line on both sides , a control gate and a silicide layer formed in a self-aligned manner on the diffusion bit line with the polysilicon layer and the surface of the diffusion bit line exposed , a floating gate and a control At least two stacked bodies including gates are provided in the channel width direction, the two stacked bodies share a diffusion bit line extending in the channel width direction, and include a trench for separating the stacked bodies in the channel width direction . A virtual ground type semiconductor memory device. 2. The virtual ground type semiconductor memory device according to claim 1, further comprising a word line made of a metal conductive layer extending in the channel length direction in contact with the control gate. A method of manufacturing a virtual ground type semiconductor memory device according to claim 1,
Forming at least one layer for forming a floating gate extending in a channel width direction on a semiconductor substrate via a gate insulating film;
A step of introducing a dopant into the semiconductor substrate using the floating gate forming layer as a mask to form diffusion bit lines on both sides in the channel length direction of the floating gate forming layer ;
Burying the diffusion bit line region with a first insulating layer;
Removing the first insulating layer leaving a certain thickness;
Forming a polysilicon layer so as to cover the floating gate forming layer and be insulated from the floating gate forming layer ;
Forming a resist layer covering at least the polysilicon layer corresponding to the upper surface of the floating gate desired to be formed, and removing the floating gate forming layer, the polysilicon layer and the first insulating layer using the resist layer as a mask; And a control gate made of a polysilicon layer covering a part of the side wall in the channel length direction starting from the upper surface of the floating gate, and a layered body sharing a diffusion bit line extending in the channel width direction with a channel width. Forming at least two in the direction, and then removing the resist layer;
Oxidizing the surface of the control gate, removing the oxide film on the upper surface of the control gate and the gate insulating film on the diffusion bit line, and forming a silicide layer on the removal surface by salicide ;
Forming a trench for separating the stacked bodies in the semiconductor substrate between the stacked bodies using the silicide layer on the diffusion bit line as a mask . A step of filling the diffusion bit line region with a second insulating layer after forming the silicide layer;
Forming a metal conductive layer on the entire surface;
The metal conductive layer extending in the channel length direction, forming a resist layer for processing to the word line contacting the control gate, by exposing the semiconductor substrate using the resist layer as a mask to form the word lines, then The virtual ground type semiconductor according to claim 3 , further comprising: forming a trench for separating the stacked bodies in the semiconductor substrate between the stacked bodies using the silicide layer on the diffusion bit line as a mask, and thereafter removing the resist layer. A method for manufacturing a memory device . 5. The method of manufacturing a virtual ground type semiconductor memory device according to claim 3 , wherein the diffusion bit line is formed with a low concentration injection amount represented by 2E13 to 2E14 cm ⁻² . Method for producing a virtual ground type semiconductor memory device according to any one of claims 3-5 for performing formation of a virtual ground type semiconductor memory device and a peripheral circuit simultaneously.

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