JPH03194967A - Manufacture of semiconductor non-volatile memory - Google Patents

Abstract

PURPOSE:To increase the thickness of a gate insulating film of a high withstand voltage transistor adequately without deteriorating the write and read characteristics of a memory transistor by forming a gate insulating film of a memory transistor and a gate insulating film of a high withstand voltage transistor in different thicknesses. CONSTITUTION:A memory transistor is formed by forming a control gate CG of a conductor film 11 of a second layer on a floating gate FG formed of a conductor film 9 of first layer through an insulating film 10. A peripheral circuit is constituted of a low withstand voltage transistor and a high withstand voltage transistor. When a semiconductor non-volatile memory having the memory transistor and the peripheral circuit is formed, the gate insulating film 8 of the memory transistor and the gate insulating film 8 of the high withstand voltage transistor are formed in different thicknesses. A conductor film 9 of the first layer of a specified configuration is formed in a formation part of the high withstand voltage transistor and the conductor film 11 of the second layer of a specified configuration is formed thereon. The conductor film 9 of the first layer is patterned to nearly the same configuration as the conductor film 11 to form a gate electrode G2 of the high withstand voltage transistor.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor non-volatile memory commonly used in the manufacture of semiconductor non-volatile memories having a memory cell structure in which a control gate is stacked on a floating gate. Regarding the manufacturing method, the present invention is particularly suitable for manufacturing semiconductor nonvolatile memories equipped with high voltage transistors.

[Summary of the Invention] The present invention provides a memory transistor having a structure in which a control gate formed of a second conductive film is stacked on a floating gate formed of a first conductive film with an insulating film interposed therebetween. and a peripheral circuit constituted by a low-voltage transistor and a high-voltage transistor, the gate insulating film of the memory transistor and the gate insulating film of the high-voltage transistor are formed with different thicknesses. , a first layer conductor film having a predetermined shape is formed on the formation portion of the high voltage transistor, a second layer conductor film having a predetermined shape is formed on the first layer conductor film having a predetermined shape, and a second layer conductor film having a predetermined shape is formed on the first layer conductor film having a predetermined shape. By forming the gate electrode of the high-voltage transistor by patterning the first-layer conductor film having a predetermined shape in substantially the same shape as the second-layer conductor film, the write characteristics and The film thickness of the gate insulating film of the high voltage transistor can be made sufficiently large without causing deterioration of the readout characteristics, and the film thickness of the gate insulating film of the memory transistor and the film thickness of the gate insulation film of the high voltage transistor can be made sufficiently large. This allows them to be set separately and to simplify the manufacturing process.

Further, the present invention provides a semiconductor having a memory transistor having a structure in which a control gate formed of a second conductive film is stacked on a floating gate formed of a first conductive film with an insulating film interposed therebetween. In a method for manufacturing a nonvolatile memory, a step of forming a first layer conductor film having a predetermined shape, and a step of forming an insulating film containing at least a silicon nitride film so as to cover the first layer conductor film having a predetermined shape. and a step of forming a control gate on a first layer conductor film having a predetermined shape via an insulating film, it is possible to improve the withstand voltage and data retention characteristics between the floating gate and the control gate. It was made possible.

[Conventional technology]

Conventionally, as this type of semiconductor nonvolatile memory, E P
ROM (Erasable and Program
mable Read Only Memory) and E
E P ROM (t!1 electrically E
rasable and Progra+u+able
Read only Me+wory) and the like are known. In some EPROMs and EEPROMs, the peripheral circuitry is constituted by high breakdown voltage transistors of, for example, 40 to 50 V series and low breakdown voltage transistors of, for example, 5V series.

Conventionally, EFR equipped with such high voltage transistors
There are methods for manufacturing OM as shown in FIGS. 4A to 4. This is an example in which the gate electrode of a high voltage transistor is formed from a second layer of polycrystalline silicon (Si 2 ) film. In this conventional EPROM manufacturing method, as shown in FIG. 4A, first, for example, a p-type St substrate 10 is
After forming a p-well 102 and an n-well 103 in the p-type Si substrate 101, field oxidation [104] for isolation between elements, such as a 5iOt film, is selectively formed on the surface of the p-type Si substrate 101. At the same time, p-type impurities and n-type impurities that had been ion-implanted into this p-type Si substrate 101 in advance
Due to the diffusion of the type impurity, a p-type channel stopper region 1 is formed under the field oxide film 104, for example.
05 and, for example, an n9 type channel stopper region 106 is formed, and a p- type semiconductor region 107 is formed under the field oxide film 104 in the n well 103. For example, SiQ! is deposited on the surface of the active region surrounded by SiQ! using a thermal oxidation method. A gate insulating film 108 like a film is formed.

The gate insulating film lO8 has a thickness required for the memory transistor. Next, for example, a first layer of polycrystalline Si film is formed on the entire surface by CVD method, and after doping this polycrystalline Si film with an impurity such as phosphorus (P) to lower the resistance, this polycrystalline Si film is The Si film is patterned into a predetermined shape by etching. Reference numeral 109 indicates the polycrystalline Si film thus formed in the memory transistor forming area. The width of polycrystalline Si film 109 is the same as that of floating gate FG', which will be described later. After this, this polycrystalline Si film 10
The portion of the gate insulating film 108 not covered by the gate insulating film 9 is removed by etching to expose the surface of the active region.

Next, by performing thermal oxidation, as shown in FIG. The gate insulating film 108 is again formed on the surface of the region. Next, the gate insulating film 108 in the low breakdown voltage transistor formation area is selectively removed by etching, and then thermal oxidation is performed again.

As a result, the gate insulating film 108 is again formed on the surface of the active region of the low breakdown voltage transistor forming part, and
The thickness of the gate insulating film 108 formed on the surface of the active region of the high voltage transistor forming portion increases.

Next, as shown in FIG. 4C, after forming a second layer of polycrystalline Si film 111 on the entire surface by CVD, this polycrystalline Si #111 is doped with an impurity such as P to reduce the Become a resistance. After that, a resist pattern 11 having a predetermined shape is formed on this polycrystal 5iWIIll by lithography.
form 2.

Next, using this resist pattern 112 as a mask, polycrystalline silicon is etched by, for example, reactive ion etching (RIE).
By anisotropically etching the i-film 111 in the direction perpendicular to the substrate surface, as shown in the fourth figure, the gate electrode 01' for the control gate (CG) for the memory transistor and the low breakdown voltage transistor constituting the peripheral circuit is formed. and a gate electrode Gt for a high voltage transistor that constitutes a peripheral circuit.
′ is formed.

Next, as shown in FIG. 4, after covering the surface of the peripheral circuit section with a resist pattern 113, the insulating film 110 is anisotropically etched in a direction perpendicular to the substrate surface by, for example, RIE.

Next, using the resist pattern 112 as a mask again, polycrystalline 5ilil I 09 is anisotropically etched in a direction perpendicular to the substrate surface by, for example, RIE. by this,
As shown in Figure 4F, floating game 1-FG"
is formed in a self-aligned manner with respect to the control game) CG'. After this, the resist patterns 112 and 113 are removed.

Next, as shown in FIG. 4G, the floating gate F
Portions of the gate insulating film 108 other than G' and gate electrodes G+'' and Gz' are removed by etching to expose the surface of the active region.

Next, by performing thermal oxidation, as shown in FIG. An insulating film 114, such as a 5i01 film, is formed on the surface of the p-type Si substrate 101 and the p-type Si substrate 101, using the control gate CG", the floating gate FC", and the gate electrode Gl as masks. An n-type impurity such as arsenic (As) is ion-implanted at a high concentration into the well 102. Similarly, a p-type impurity such as boron (B) is implanted into the n-well 103 using the gate electrode Gt' as a mask. Ion implantation is performed at a high concentration. As a result, for example, an n9 type source region 115 and drain region 116 are formed in a self-aligned manner with respect to the control gate CG' and the floating gate FC'', and the gate electrode G,
For example, an n-type source region 11 is formed in a self-aligned manner with respect to
7 and a drain region 118 are formed. In addition, for example, a p type source region 119 is formed in a self-aligned manner with respect to the gate electrode Gt', and the previously formed p
Low impurity concentration portion 120 consisting of - type semiconductor region 107
A p'-type drain region 120 containing a is formed.

And control gate CG', floating gate FC" source region 115 and drain region ¥4116
A memory transistor is formed. In addition, the gate electrode GI', the source region 117 and the drain region 11
8 forms a low breakdown voltage transistor forming a peripheral circuit, and the gate electrode Gt' source region 119 and drain region 120 form a high breakdown voltage transistor forming a peripheral circuit. Here, the low voltage transistor is an n-channel MO3) transistor, and the high voltage transistor is a so-called LOD (LOCO50ffse) transistor.
t Drain) type p-channel MO3I-transistor. After that, a glabellar insulating film 1 such as a phosphosilicate glass (PSG) film is applied to the entire surface by, for example, a CVD method.
Form 21.

Next, as shown in FIG. 4, a film of, for example, silicon nitride (5isNa) M 122 is formed on the entire surface by low-pressure CVD, and then a film of, for example, arsenic silicate glass (AsSG) is formed on this Si, N, film 122. After forming 123, sSC, film 123, and Si3Na film 12 are formed on these layers.
Contact holes c,',
c, ′, c3 ′, c4 ′.

C5' and c6'' are formed. Next, for example, aluminum-silicon (AI-S) is formed on the entire surface by, for example, a spunter method.
i) After forming the alloy film, pattern the Al-Si alloy film into a predetermined shape by etching to form the wiring 124.
~129 is formed. Thereafter, a passivation film 130 made of, for example, a PSG film formed by a CVD method and a SiN film formed by a plasma CVD method is formed to complete the intended EPROM.

On the other hand, FIGS. 5A to 5H show another conventional method of manufacturing an EFROM in which a high voltage transistor is mounted. This is an example of forming. This conventional EFRO
In the manufacturing method of M, as shown in FIG. 5A, first, a field oxide film 104 for isolation between elements, such as a SiO□ film, is selectively formed on the surface of a p-type Si substrate 101, and For example, a p-type channel stopper region 105 is formed under this field oxide film 104. Next, a gate insulating film 108 such as a Si film is formed on the surface of the active region surrounded by the field oxide film 104 by thermal oxidation. Next, a first layer of polycrystalline Si film is formed on the entire surface by CVD method, and after doping this polycrystalline Si film with an impurity such as P to lower the resistance, this polycrystalline Si film is etched. patterning into a predetermined shape. As a result, a polycrystalline Si film 109 having a predetermined shape is formed in the memory transistor formation area, and a gate electrode 62' for the high voltage transistor is formed.
form. Thereafter, the gate insulating film 108 in the low breakdown voltage transistor formation area is removed by etching to expose the surface of the active region.

Next, by performing thermal oxidation, as shown in FIG. 5B, an insulating film 110 such as a 5ift film is formed on the surface of the polycrystalline Si film 109, and the active region of the low breakdown voltage transistor forming area is A gate insulating film 108 is again formed on the surface. At this time, the insulating film 110 is also formed on the surface of the gate electrode Gz'.

Next, as shown in FIG. 5C, after forming a second layer of polycrystalline Si film 111 on the entire surface by CVD, this polycrystalline Si film 111 is doped with an impurity such as P to reduce the Become a resistance. Thereafter, a resist pattern 112 having a predetermined shape is formed on this polycrystalline Si film 111 by lithography.

Next, using this resist pattern 112 as a mask, the polycrystalline Si film 111 is anisotropically etched in a direction perpendicular to the substrate surface by, for example, RIE, thereby forming a memory transistor control gate (as shown in Figure 5).
CG'' and a gate electrode GI' for a low breakdown voltage transistor constituting a peripheral circuit.

Next, as shown in FIG. 5, after covering the surface of the peripheral circuit section with a resist pattern 113, the insulating film 110 and polycrystalline Si film 109 are anisotropically etched in a direction perpendicular to the substrate surface by, for example, RIE. do.

As a result, the floating gate FC' is formed in self-alignment with the control gate CG'. After this, the resist patterns 112 and 113 are removed. Next, the gate electrode Gz′ and the second portion left on the sidewall thereof are
After covering the surface of the portion excluding the polycrystalline Si film 111 of the layer with a resist pattern (not shown), by performing anisotropic etching by, for example, RIE method using this resist pattern as a mask, the gate electrode Gz'' is etched. The second layer of polycrystalline Si film 111 remaining on the sidewalls is removed by etching.

Next, by performing thermal oxidation, as shown in FIG. 5F, the control gate CG' and the floating gate F
For example, S is applied to the surfaces of G' and the gate electrode Gl''Gz.
An insulating film 114 like a film is formed. Next, control gate CG' and floating gate FG'
Using the gate electrodes G+ and G2' as masks, n-type impurities are ion-implanted into the P-type Si base vi, 101 at a low concentration. As a result, control gate CG'
and floating gate) For example, n-type semiconductor regions 131 and 132 are formed in self-alignment with respect to FC',
For example, n-type semiconductor regions 133 and 134 are formed in a self-aligned manner with respect to the gate electrode G1'.
For example, an n-type semiconductor region 1 is formed in a self-aligned manner with respect to
35,136 are formed.

Next, as shown in FIG. 5G, a portion of the semiconductor region 132 on the floating gate FG' side and a portion of the semiconductor region 136
The portion on the gate electrode Gt' side is covered with, for example, a resist pattern 137.

Next, n-type impurities are ion-implanted into the p-type Si substrate 101 at a high concentration using the resist pattern 137, the control gate cc'', the floating gate FC', and the gate electrodes G,'', G,' as masks. by this,
As shown in FIG. 5H, a low impurity layer consisting of, for example, an n-type source region 115 and a previously formed n-type semiconductor region 132 is self-aligned with respect to the control gate CG' and the floating gate FC'. An n" type drain region 116 having a concentration portion 116a is formed. Also, for example, an n" type drain region 116 is formed in a self-aligned manner with respect to the gate electrode 62'.
A source region 117 and a drain region 118 are formed. Further, the low impurity concentration region 1 consisting of, for example, an n''' type source region 138 and the previously formed n-type semiconductor region 136 is self-aligned with respect to the gate electrode 62'.
An n-type drain region 139 having a diameter of 39a is formed.

Then, the control gate CG', the floating gate FG', the source region 115 and the drain region 116
A memory transistor is formed. Furthermore, the gate electrode 61 ′, the source region 117 and the drain region 11
8 forms a low breakdown voltage transistor constituting the peripheral circuit, and the gate electrode Gz' and the source region 1
38 and the drain region 139 form a high voltage transistor forming a peripheral circuit. Here, both of these low voltage transistors and high voltage transistors are n
Channel MO3) is a transistor.

Thereafter, the steps are carried out in the same manner as the steps after the formation of the glabella insulating film 121 shown in FIG. 4H to complete the intended EPROM.

By the way, the floating gate FG' and control gate cc of the memory transistor of the above-mentioned EFROM
S4 as the insulating film (coupling insulating film) 110 between
An insulating film with a three-layer structure consisting of a 0g film, a 5isN4 film, and a 5ift film (hereinafter referred to as 0NO (Oxide-Ni trid)
It is known that characteristics such as withstand voltage between the floating gate FG' and the control gate CG' can be improved by using an e-Oxide film). A conventional method of manufacturing an EFROM in which an ONO film is used as the insulating film 110 between the floating gate FC' and the control gate CG' will be described with reference to FIG. That is, in this conventional EPROM manufacturing method, as shown in FIG.
After forming a gate insulating film 10B on the surface of the active region surrounded by this field oxide film 104, a first layer of polycrystalline Si film 109 is formed on the entire surface.
The i film 109 is doped with an n-type impurity such as P to lower its resistance. Next, an SiO □ film 140 is formed on this polycrystalline Si film 109 by a thermal oxidation method.
□Si, N, film 141 by CVD method on film 14 film 40
form. Next, these Si 3N 4 films 141
, Si,Oz film 140 and polycrystalline Si film 109 are sequentially patterned into a predetermined shape by etching. As a result, a polycrystalline Si film 109 having a predetermined shape is formed in the memory transistor formation area, and this polycrystalline Si film 109 is
A Sing film 140 and a Si3N4 film 14 are formed on the t film 109.
1 is left. Next, by thermally oxidizing this 5izN4 film 141, a SiO□ film 142 is formed on this Si3N4 film 14. At this time, the Stow film 142 is also formed on the side surface of the polycrystalline Si #109.

[Problems to be Solved by the Invention] In the conventional EPROM manufacturing method shown in FIGS. 4A to 4 above, the thickness of the gate insulating film 108 of a high voltage transistor that requires a high gate voltage is increased. However, as shown in FIG. 4B, when forming the gate insulating film 108 of this high voltage transistor, the insulating film 110 used as a coupling insulating film between the floating gate FG' and the control gate CG' is also formed at the same time. Therefore, if an attempt is made to increase the thickness of the gate insulating film 108 of the high voltage transistor as described above, the thickness of the insulating film 110 between the floating gate FG' and the control gate CG' will also increase.

Therefore, there is a problem in that the coupling capacitance between the floating gate FC" and the control gate CG' is reduced, making it impossible to obtain desired write and read characteristics.

Furthermore, the conventional EPRO shown in FIGS. 5A to 5H above
In the manufacturing method of M, the gate insulating film 108 of the memory transistor and the gate insulating film l11 of the high voltage transistor
108 have the same film thickness, it is not possible to set the gate insulating film 108 of the memory transistor and the gate insulating film 108 of the high voltage transistor to different film thicknesses.

Therefore, there is a problem in that it is difficult to optimize the thickness of the gate insulating film 108 of the memory transistor and the thickness of the gate insulating film 108 of the high voltage transistor. Furthermore, since a lithography process and an etching process are required to remove the second layer of polycrystal 51M111 remaining on the sidewall of the gate electrode Gz' after the completion of the process shown in FIG. 5E, the manufacturing process is There was also the problem that there were too many.

On the other hand, as shown in FIG.
In the conventional EFROM manufacturing method in which an ONO film is used as the coupling insulating film between the control gate CG' and the control gate CG', 5tyx Ni 14
0 and SixNg W! 141 and a 5iOz film 142, the insulating film 110 on the side surface of this floating gate is made up of a 5iOz film 142.
42, there is a problem in that this tends to cause poor breakdown voltage and deterioration of data retention characteristics.

Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor nonvolatile memory that can sufficiently increase the thickness of a gate insulating film of a high voltage transistor without causing deterioration of the write characteristics and read characteristics of the memory transistor. It is in.

Another object of the present invention is to provide a method for manufacturing a semiconductor nonvolatile memory in which the thickness of the gate insulating film of a memotile transistor and the gate insulating film of a high voltage transistor can be set separately. It is in.

Another object of the present invention is to provide a method for manufacturing a semiconductor nonvolatile memory that can simplify the manufacturing process.

Another object of the present invention is to provide a semiconductor non-volatile film that can improve breakdown voltage and data retention characteristics between the floating gate and the control gate when an ONO film is used as an insulating film between the floating gate and the control gate. An object of the present invention is to provide a method for manufacturing a memory.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a floating gate (FC) formed by a first layer conductor film (9).
), a control gate (CC) formed by a second layer conductor film (11) is stacked on top of the memory transistor with an insulating film (10) interposed therebetween, a low breakdown voltage transistor and a high breakdown voltage transistor. In a method for manufacturing a semiconductor non-volatile memory having a peripheral circuit, a gate insulating film (8) of a memory transistor and a gate insulating film (8) of a high voltage transistor are formed with different thicknesses to form a high voltage transistor. A first layer conductor film (9) of a predetermined shape is formed on the first layer conductor film (9) of a predetermined shape, and a second layer conductor film (11) of a predetermined shape is formed on the first layer conductor film (9) of a predetermined shape. , the gate electrode (G2) of the high voltage transistor is formed by patterning the first layer conductor film (9) in almost the same shape as the second layer conductor film (11) having a predetermined shape. There is.

Furthermore, in order to achieve the above object, the present invention provides a floating gate formed by a first layer conductive film (9).
In a method for manufacturing a semiconductor nonvolatile memory having a memory transistor having a structure in which a control gate (CC) formed by a second layer conductor film (11) is stacked on a (FC) via an insulating film, forming a first layer conductor film (9), and forming at least a silicon nitride film (3) so as to cover the first layer conductor film (9) having a predetermined shape.
2) and a step of forming a control gate (CG) on the first layer conductor film (9) having a predetermined shape via the insulating film.

Here, as the first layer conductor film (9), for example, a polycrystalline Si film doped with impurities can be used. The second layer conductor film (11) may be, for example, a polycrystalline Si film doped with impurities, or a high-density film such as a tungsten silicide (WSiz) film on the polycrystalline Si film doped with impurities. A polycide film formed by overlapping a melting point metal silicide film or the like can be used.

As the insulating film containing at least a silicon nitride film, for example, an insulating film having a three-layer structure consisting of a silicon oxide film, a silicon nitride film, and a silicon oxide film can be used.

[Effect]

According to the method for manufacturing a semiconductor nonvolatile memory of the present invention configured as described above, the gate insulating film (8) of the memory transistor and the gate insulating film (8) of the high voltage transistor are formed with different thicknesses. Therefore, the gate insulating film (8) of the memory transistor and the gate insulating film (8) of the high voltage transistor can be set to different film thicknesses.

As a result, the gate insulating film (8
) and the gate insulating film (8) of the high voltage transistor can be optimized. Further, the insulating film (10) used as a coupling insulating film between the floating gate (FG) and the control gate (CC;) is
Since it can be formed independently of the gate insulating film (8) of the high voltage transistor, this insulating film (8) can be formed independently of the gate insulating film (8) of the high voltage transistor.
10) The film thickness will not become large.

Therefore, reduction in coupling capacitance between the floating gate (FG) and the control gate (CG) can be prevented. Thereby, it is possible to improve the write characteristics and read characteristics of the memory transistor. Furthermore, the gate electrode (G2) of the high voltage transistor is formed by patterning the first layer conductor film (9) having a predetermined shape into almost the same shape as the second layer conductor film (11) having a predetermined shape. Therefore, the lithography process and etching process for etching away the second layer conductor film (11) left on the side wall of the gate electrode (G2), which is required in the conventional method, are not necessary. Thereby, the manufacturing process can be simplified by this amount.

Further, according to the method for manufacturing a semiconductor nonvolatile memory of the present invention configured as described above, at least the silicon nitride film (32
) is formed, and a control gate (
CG), therefore, not only the top surface of the first layer conductor film (9) having a predetermined shape that will eventually become the floating gate (FG), but also the insulating film on the sidewalls. is also an insulating film containing a silicon nitride film (32).Therefore, there is no cause for a decrease in breakdown voltage between floating gates (FC) and between control gates (CC;) and deterioration of data retention characteristics. Between floating gates (FC) and control gates (
CG) and data retention characteristics can be improved.

[Examples] Examples of the present invention will be described below with reference to the drawings. In addition, in all the drawings of the embodiment, the same parts are given the same reference numerals.

FIGS. 1A to 1I show an EFRO according to an embodiment of the present invention.
The manufacturing method of M is shown.

In this embodiment, as shown in FIG. 1A, first, for example, a p-well 2 and an n-well 3 are formed in a p-type Si substrate 1, and then, for example, 5iOz
A field oxide film 4 for isolation between elements, such as a film, is selectively formed. At the same time, p-type Si-based Fi
, 1, by diffusing the p-type impurity and n-type impurity ions implanted into the field oxide film 4, a p-type channel stopper region 5 and an n-type channel stopper region, for example, are formed under the field oxide film 4. At the same time, a P- type semiconductor region 7, for example, is formed under the field oxide film 4 in the n-well 3. Next, a gate insulating film 8 such as a SiOg film is formed on the surface of the active region surrounded by the field oxide film 4 by thermal oxidation. Next, after removing the gate insulating film 8 in the memory transistor formation area by etching, thermal oxidation is performed again. As a result, the gate insulating film 8 having a required thickness of M is formed on the surface of the active region of the memory transistor forming part, and the gate insulating film 8 of the high voltage transistor forming part is set to the required film thickness. Specifically, the thickness of the gate insulating film 8 in the memory transistor forming part is, for example, about 350, and the film thickness of the gate insulating film 8 in the high voltage transistor forming part is, for example, about 600. Next, for example, a first layer of polycrystalline Si film is formed by the CVD method, and this polycrystalline Si film is doped with an impurity such as P to lower the resistance, and then this polycrystalline St film is etched. Patterning into a predetermined shape.

As a result, a polycrystalline Si film 9 of a predetermined shape is formed in the memory transistor forming part and the high voltage transistor forming part, respectively.
is formed.

Next, by performing thermal oxidation, as shown in FIG. 1B, an insulating film (coupling insulating film) 10 such as a 5iOt film is formed on the surface of the polycrystalline St film 9, and
A gate insulating film 8 is formed on the surface of the active region of the low breakdown voltage transistor forming portion. At this time, the insulating film 10 is also formed on the surface of the gate electrode Gt.

Next, as shown in FIG. 1C, a second layer of polycrystalline St film 11, for example, is formed on the entire surface by CVD, and this polycrystalline Si film 11 is doped with an impurity such as P to reduce the After being made into a resistor, a resist pattern 12 of a predetermined shape is formed on this polycrystalline Si film 11 by lithography.

Next, using this resist pattern 12 as a mask, the polycrystalline St film 11 is anisotropically etched in a direction perpendicular to the substrate surface by, for example, RIE, and the control gate CG for the memory transistor and its surroundings are etched as shown in Figure 1. A gate electrode G for a low breakdown voltage MOS transistor constituting the circuit is formed, and a polycrystalline Si film 11 having a predetermined shape is formed on the polycrystalline Si film in the high breakdown voltage transistor formation area.

Next, as shown in FIG. 1E, after covering a part of the surface of the low voltage transistor forming part and the surface of the high voltage transistor forming part in the peripheral circuit section with a resist pattern 13, an insulating film 13 is formed by, for example, RIE method. is anisotropically etched in a direction perpendicular to the substrate surface.

Next, a first layer of polycrystalline Si film 9 is formed by, for example, RIE method.
is anisotropically etched in a direction perpendicular to the substrate surface. As a result, the floating gate FG is formed in a self-aligned manner with respect to the control gate CQ, as shown in FIG. The gate electrode Gt for the high voltage transistor is formed by patterning in the same shape as the second layer polycrystalline Si film 11 formed in the second layer.

During this anisotropic etching, the first layer of polycrystalline Si
The second layer of polycrystalline Si film 11 formed on the side wall of film 9 is also etched away at the same time. After this, the resist patterns 12 and 13 are removed.

Next, as shown in Figure 1G, the floating game)F
Portions of the gate insulating film 8 other than C and gate electrodes G, , G are removed by etching to expose the surface of the active region.

Next, by performing thermal oxidation, as shown in FIG. Next, the p-type Si substrate 1 and the p-type Si substrate 1 are formed using the control gate CG, floating gate FC, and gate electrode G1 as masks.
An n-type impurity such as As is ion-implanted into the well 2 at a high concentration. Similarly, a p-type impurity such as B is ion-implanted into the n-well 3 at a high concentration using the gate electrode G2 as a mask. Thereby, for example, the n-type source region 15 and drain region 16 are self-aligned with respect to the control gate CG and floating gate FG.
At the same time, for example, an n-type source region 17 and drain region 18 are formed in self-alignment with respect to the gate electrode G1. Further, a p-type source region 19, for example, is formed in a self-aligned manner with respect to the gate electrode G2, and a p+-type source region 19 having a low impurity concentration portion 20a made of the previously formed p-type semiconductor region 7 is formed. drain region 2
0 is formed. A memory transistor is formed by the control gate CG, floating gate FC, source region 15, and drain region 16. Further, the gate electrode Gl, the source region 17, and the drain region 18 form a low voltage transistor forming a peripheral circuit, and the gate electrode Gt, the source region 19, and the drain region 20 form a high voltage transistor forming a peripheral circuit. . Here, the low voltage transistor is an n-channel MOS transistor, and the high voltage transistor is an L
It is an OD type p-channel MO3) transistor. Thereafter, a glabellar insulating film 21 such as a PSG film is formed on the entire surface by CVD.

Next, as shown in FIG. 1, a Si, N, film 22, for example, is formed on the entire surface by, for example, a low pressure CVD method, and an As5G film 23, for example, is formed on the Si, N, film 22. Predetermined portions of the As5G film 23.5isN4 film 221, the interlayer 21 film 21, and the gate insulating film 8 are sequentially removed to form contact holes C+, Cm, C3, and C.
4, Cs and Cb are formed. Next, for example, an Al-5t alloy film is formed on the entire surface by sputtering, and then this Al-Si alloy film is patterned into a predetermined shape by etching to form wirings 24 to 29. After this, for example, a PSG film formed by a CVD method and a plasma CVD film are formed.
A passivation film 30 made of a SiN film formed by method D is formed to complete the intended EPROM.

In the EPROM according to this embodiment, the gate electrode of the high voltage transistor G! Wiring contacts are made to each of the second layer polycrystalline Si film 11 formed thereon via the insulating film 10. For example, as shown in FIG.
Each of the one ends is bent to the opposite side so as not to overlap each other, and a wiring contact is made to each of these one ends. That is, this high voltage transistor has a stacked gate structure. C?
, CI indicate contact holes for making this wiring contact.

As described above, according to this embodiment, the film thickness of the gate insulating film 8 of the memory transistor and the film thickness of the gate insulating film 8 of the high voltage transistor can be set to different values. The thickness of the gate insulating film 8 can be set to its optimum thickness, and the thickness of the gate insulating film 8 of the high breakdown voltage transistor can be set to a thickness that provides a sufficient gate breakdown voltage. Also,
This prevents the film thickness of the insulating film 10 between the floating gate FC and the control gate 00 from increasing, so that it is possible to prevent the coupling capacitance between the floating gate FG and the control gate 00 from decreasing. Therefore, it is possible to improve the write characteristics and read characteristics of the memory transistor.

Further, the first layer polycrystalline Si film 9 is placed on top of the insulating film 10.
Since the gate electrode G2 of the high voltage transistor is formed by patterning by etching to have the same shape as the second layer polycrystalline Si film 11 having a predetermined shape formed through the etching process, the gate electrode G2 of the high voltage transistor is formed. ~As in the conventional EFROM manufacturing method shown in FIG. No longer needed. Thereby, the manufacturing process can be simplified by this amount.

Next, another embodiment of the present invention will be described with reference to FIGS. 3A to 3D.

In this embodiment, as shown in FIG. 3A, first P
After forming a field oxide film 4 on the surface of the type Si substrate 1 and forming a 23-type channel stopper region 5 under the field oxide film 4, a field oxide film 4 is formed on the surface of the active region surrounded by the field oxide film 4. A gate insulating film 8 is formed by a thermal oxidation method.

Next, a first layer of polycrystalline Si film 9 is formed over the entire surface by CVD.
After doping this polycrystalline Si film 9 with an impurity such as P to lower its resistance, the polycrystalline Si film 9 is patterned into a predetermined shape by etching to form a predetermined shape in a memory transistor formation area. A polycrystalline Si film 9 is formed. Next, the portion of the gate insulating film 8 not covered by the polycrystalline 52 film 9 is removed by etching to expose the surface of the active region.

Next, thermal oxidation is performed to form a Si film 31 on the surface of the polycrystalline Si film 9 and the surface of the exposed active region, as shown in FIG. 3B. Next, a Si x Na film 32 is formed on the entire surface by, for example, a low pressure CVD method. Next, by thermally oxidizing this Si, N, film 32, a Sing film 33 is formed on this Si, N, film 32. These Stag films 31, 5isN432 and Sing film 3
A three-layer 3ONO film is formed. The thickness of this ONO film is selected so that a sufficient gate breakdown voltage can be obtained in a high breakdown voltage transistor.

Specifically, for example, in a 12.5V system high voltage transistor, the Sing film 31.5isN* film 32 and the 5ift
The film thicknesses of wA33 are, for example, about 100, 100, and 40, respectively.

Next, as shown in FIG. 3C, a second layer of polycrystalline Si film 11 is formed on the entire surface by the CVD method, and this polycrystalline Si film 11 is doped with an impurity such as P to lower the resistance. After this, a resist pattern 12 having a predetermined shape is formed on this polycrystalline Si film 11 by lithography.

Next, as shown in the third diagram, this resist pattern 1
2 as a mask, the polycrystalline Si film 11 is etched to form control gates CG for memory transistors and gate electrodes Gl, G! for low voltage transistors and high voltage transistors constituting peripheral circuits. Next, using the resist pattern 12 as a mask, the first layer of polycrystalline 5iJl! By etching 9, the floating gate is formed in self-alignment with the control gate CG.

Next, after removing the resist pattern 12, a source region, a drain region, an insulating film between the eyebrows, contact holes, wiring, etc. are formed to complete the intended EPROM.

As described above, according to this embodiment, it is possible to have a structure in which the ONO film is formed not only on the upper surface of the floating gate FC but also on the side surfaces thereof.
Floating gate FG and control gate 00
It is possible to improve the withstand voltage between the two and the data retention characteristics.

This makes it possible to realize an EPROM with high reliability.

In addition, the insulating film 10 of the memory transistor. Since the gate insulating film M8 of the low voltage transistor and the gate insulating film 8 of the high voltage transistor can be formed simultaneously in the same process, the manufacturing process can be simplified accordingly.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications can be made based on the technical idea of the present invention.

For example, in the two embodiments described above, the present invention is
Although the case where the present invention is applied to the manufacture of ROM has been described, it goes without saying that the present invention can also be applied to the manufacture of EEPROM.

[Effects of the Invention] As described above, according to the present invention, the gate insulating film of the memory transistor and the gate insulating film of the high voltage transistor are formed with different thicknesses, and a predetermined shape is formed in the area where the high voltage transistor is formed. A first layer conductor film is formed, and a second layer conductor film having a predetermined shape is formed on the first layer conductor film having a predetermined shape, and the second layer conductor film having a predetermined shape is approximately the same as the second layer conductor film having a predetermined shape. Since the gate electrode of the high-voltage transistor is formed by patterning the first layer conductor film in the same shape, the gate electrode of the high-voltage transistor is formed without deteriorating the write and read characteristics of the memory transistor. The thickness of the insulating film can be made sufficiently large, and the thickness of the gate insulating film of the memory transistor and the gate insulating film of the high voltage transistor can be set separately, and the manufacturing process is simplified. It is possible to aim for

Further, according to the present invention, a step of forming a first layer conductor film having a predetermined shape, and a step of forming an insulating film containing at least a silicon nitride film so as to cover the first layer conductor film having a predetermined shape. and a step of forming a control gate on the first layer conductor film having a predetermined shape via an insulating film. The insulating film between the floating gate and the control gate can also be an ONO film, thereby improving the breakdown voltage and data retention characteristics between the floating gate and the control gate.

[Brief explanation of drawings]

FIGS. 1A to 1I show an EFRO according to an embodiment of the present invention.
2 is a partial plan view showing the gate electrode portion of a high-voltage transistor of an EFROM manufactured by the manufacturing method shown in FIGS. 1A to 1; 3A to 3D are cross-sectional views for explaining a method for manufacturing an EFROM according to another embodiment of the present invention in the order of steps, and FIGS. Cross-sectional views for explanation, Figures 5A to 5
FIG.
FIG. 3 is a cross-sectional view for explaining a method for manufacturing M. NG gate, GI, Gt: gate electrode.

Claims (1)

[Claims] 1. A memory transistor having a structure in which a control gate formed of a second conductive film is stacked on a floating gate formed of a first conductive film with an insulating film interposed therebetween. , a method for manufacturing a semiconductor nonvolatile memory having a peripheral circuit constituted by a low-voltage transistor and a high-voltage transistor, wherein a gate insulating film of the memory transistor and a gate insulating film of the high-voltage transistor are formed to have different thicknesses from each other. and a predetermined shape of the first
forming a second layer conductor film having a predetermined shape, forming a second layer conductor film having a predetermined shape on the first layer conductor film having the predetermined shape; A method for manufacturing a semiconductor nonvolatile memory, characterized in that the gate electrode of the high voltage transistor is formed by patterning the first layer conductor film having the predetermined shape into substantially the same shape as the above. 2. A semiconductor non-volatile memory having a memory transistor having a structure in which a control gate formed by a second conductive film is stacked on a floating gate formed by a first conductive film with an insulating film interposed therebetween. In the manufacturing method, a step of forming the first layer conductor film having a predetermined shape, and a step of forming the insulating film containing at least a silicon nitride film so as to cover the first layer conductor film having the predetermined shape. A method for manufacturing a semiconductor nonvolatile memory, comprising the steps of: forming the control gate on the first layer conductor film having the predetermined shape through the insulating film.