JP3308727B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device requiring a contact with an element region.

[0002]

2. Description of the Related Art In general, in a semiconductor integrated circuit typified by a memory, a logic, or the like, in order to form a circuit by connecting individual transistors with a wiring material, a technique of connecting a wiring material to a terminal of each transistor. (Contact formation technology) is indispensable.

FIG. 23 is a plan view of a conventional semiconductor device. An element region 51 and an element isolation region 52 are formed on a semiconductor substrate, and a gate electrode 8 and a contact 53 are formed.
Are formed to constitute a transistor.

Hereinafter, a conventional process will be described with reference to FIGS. 24 to 27 in the case where the element isolation is based on a trench isolation method, and problems of the conventional contact forming technique will be described.

First, a 10-50 nm film is formed on a silicon substrate 1.
Buffer oxide film 2 is formed, and 100-500
nm of polycrystalline silicon 3 and 100-500 nm
Is sequentially deposited. The polycrystalline silicon 3 and the CVD silicon oxide film 4 serve as a mask material in a trench etching step for forming a trench 6 described later.

Next, after a resist 30 is applied thereon, a trench pattern is transferred and formed by photolithography (FIG. 24A). Using the patterned resist 30 as a mask, the CVD silicon oxide film 4, the polycrystalline silicon film 3, and the buffer oxide film 2 are
Etching by IE and stripping of resist (FIG. 24)
(B)).

Next, a groove 6 serving as an element isolation is formed on the silicon substrate 1 by RIE (FIG. 25A).
At this time, the CVD silicon oxide film 4 functions as a mask. The depth of the groove 6 formed on the silicon substrate is equal to 0.1.
Desirably, it is 3-0.7 μm.

Next, thermal oxidation of 20 to 50 nm is performed to protect the side wall of the groove 6 and to round off the corner at the entrance of the groove 6 on the surface of the silicon substrate 1. At this time, impurity ions may be implanted through the thermal oxide film to increase the element isolation capability.

Next, after the above thermal oxidation, a CVD silicon oxide film (for example, TEOS) 7 is deposited from the bottom of the groove 6 to above the CVD silicon oxide film 4 (FIG. 25).
(B)). The thickness of the CVD silicon oxide film deposited at this time is, for example, 850 nm.

After that, the CVD silicon oxide 7 is etched back until the polycrystalline silicon 3 is exposed. For this etchback, an etchback technique using a resist may be used, or polishing may be used.

Next, the polycrystalline silicon 3 as a mask material
Is removed by CDE, and the buffer oxide film 2 is
(FIG. 26A). An element isolation region is formed by the above manufacturing steps. In the following steps, an element such as a transistor is formed on the element region.

First, the silicon substrate 1 on the element region is
It is oxidized by about nm, and impurities are implanted through the oxide film for controlling the threshold value of the transistor. Next, the oxide film is once removed, a gate oxide film is formed, and polycrystalline silicon 8 serving as a gate is deposited. Thereafter, when the gate 8 is patterned to form a diffusion layer, the transistor is completed. FIG. 26B shows a cross-sectional view of the process at this time, which is a cross section taken along the line AA ′ in FIG.

Thereafter, a CVD silicon oxide film 10 is deposited to a thickness of 500 to 1000 nm for planarization and insulation, and the surface is planarized by polishing or remelting at a temperature of about 850 ° C. FIG. 27A is a sectional view showing a step at this time. This figure is a cross section taken along line BB 'in FIG.

Next, a contact hole is opened toward the source / drain of the transistor. First, a resist is applied on a CVD silicon oxide film, and the resist is removed only by the photolithographic technique at a portion where the contact hole is to be opened. .

The CVD silicon oxide film 8 has a contact RI
At the time of E, etching is performed according to the resist pattern, and a contact hole reaching the silicon substrate 1 on the element region is formed. FIG. 27B is a process sectional view of a BB ′ section in FIG. 23 at this time.

Next, Al is sputtered to form a wiring layer through steps such as resist coating, photolithography, and RIE. FIG. 28A is a cross-sectional view taken along the line BB 'in FIG. 23 at this time. .

In the above-mentioned manufacturing process, in the process of forming a contact, no problem appears when the size of the element is sufficiently large, but some problems arise as the element is miniaturized.

One of the new problems is a short circuit failure between the transistor diffusion layer and the substrate caused by an alignment error in the photolithography process. A margin is usually provided between the contact hole and the end of the element region, which is called a margin for alignment. This is shown in FIG. 23 and FIG.
Is indicated by the letters The alignment margin is set to be larger than the pattern misalignment normally expected in the photolithography process, so that the contact does not deviate from the element region even if misalignment occurs.

However, if the element region where the contact hole is to be formed is small, a sufficient alignment margin a cannot be obtained between the contact hole and the end of the element region.
Therefore, if a misalignment larger than the alignment margin a occurs, the contact goes out of the element region, and as shown in FIG. 28B, the contact is etched to the element isolation region during RIE.

Such a defect in the processing of the contact is not desirable because it not only causes variation in the size of the contact and causes an increase in transistor element variation, but also causes a short circuit between the diffusion layer of the transistor and the substrate.

Conversely, if a sufficient margin is to be provided between the contact hole and the end of the element region, the size of the contact hole must be reduced. This increases the aspect ratio of the contact hole, making it difficult to form the contact hole and subsequently sputter or deposit the wiring material. Further, as the contact size becomes smaller, the resistance of the contact also increases, which causes the performance of the device to deteriorate.

Therefore, there is a need for a technique that does not cause a short circuit problem even if the margin between the contact hole and the end of the element region is small. In the above description, the case where the element isolation is particularly performed by the trench isolation method is described. However, the same problem occurs when the element isolation is performed by the element isolation region (LOCOS) method.

FIG. 29 shows an example of a defect when element isolation is performed by the LOCOS method. In this example, in the process of transferring the contact pattern to the resist and forming the resist mask for the contact RIE, a shift has occurred toward the right side of the drawing. As a result, the contact between the transistor diffusion layer 63 and the transistor shifts, and a short circuit occurs between the transistor diffusion layer and the substrate.

As described above, according to the conventional contact forming technique, if the matching margin between the diffusion layer of the transistor and the contact is small with respect to the accuracy of the photolithography process, a short circuit failure occurs between the transistor diffusion layer and the substrate. was there.

[0025]

As described above, in the conventional contact formation technology, as the integration degree of the LSI is increased and the element is miniaturized, the margin of contact between the contact and the end of the element region and the contact and the transistor are reduced. However, there is a problem that a short-circuit failure occurs when the matching margin with the diffusion layer becomes smaller and the photolithography process accuracy becomes lower.

Conversely, if one tries to provide sufficient margin,
The size of the contact hole becomes smaller, the aspect ratio of the contact hole also increases, and it becomes difficult to sputter or deposit the wiring material.

As described above, with the miniaturization of elements, various problems occur in the conventional contact formation. The present invention has been made in view of the above circumstances, and has as its object the purpose of preventing short-circuit failure even if the margin of contact between the contact and the element region or the margin of contact between the contact and the transistor diffusion layer is small. An object of the present invention is to provide a contact formation method that can increase the aspect ratio as compared with the related art.

[0028]

SUMMARY OF THE INVENTION The gist of the present invention is to provide an etching selectivity between a device insulating a device and a wiring layer so as to be self-aligned with a device isolation region or a transistor diffusion layer. By forming a pattern of a protective film of a certain substance and forming a contact hole in a self-aligned manner with the protective film, a contact is formed in a self-aligned manner with an element region or a transistor diffusion layer. Accordingly, it is an object of the present invention to provide a means for solving a problem related to contact formation accompanying miniaturization of an element.

[0029]

According to the present invention, a contact hole can be formed in a self-aligned manner with respect to an element isolation region end or a transistor diffusion layer. Therefore, the problem of the short-circuit failure between the transistor diffusion layer and the substrate due to misalignment between the contact and the element isolation region or the diffusion layer of the transistor, which was a conventional problem, can be solved.

Further, since the etching protection layer for the contact formation etching is provided, the region to be RIE (resist opening) at the time of RIE for contact formation can be extended to the element isolation region. Therefore, the size of the contact hole is larger than the actual contact size from the upper end of the interlayer film (silicon oxide film) between the element and the wiring layer to the etching protection layer on the element isolation region, and the aspect ratio of the contact hole Can also be kept smaller than before.

[0031]

FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention. An element region 51 and an element isolation region 52 are formed on a semiconductor substrate, and a gate electrode 8 and a contact 53 are further formed to constitute a transistor.

A manufacturing process according to an embodiment of the present invention will be described below with reference to FIGS. First, a buffer oxide film 2 of a 10-50 nm buffer oxide film 2 is formed on a silicon substrate 1, and a 100-500 nm thick polycrystalline silicon 3 and a 100-500 nm CV are formed thereon.
A D silicon oxide film 4 is sequentially deposited. The polycrystalline silicon 3 and the CVD silicon oxide film 4 serve as a mask material in a trench etching step for forming a trench 6 described later.

Next, after a resist 30 is applied thereon, a trench pattern is transferred and formed by photolithography (FIG. 2A). Using the patterned resist 30 as a mask, the CVD silicon oxide film 4, polycrystalline silicon film 3, and buffer oxide film 2 are etched by RIE (FIG. 2B). In the etching at this time, the CVD silicon oxide film 4, the polycrystalline silicon film 3, and the buffer oxide film 2 may be etched using the resist 30 as a mask, and the resist may be peeled off at the end, or the resist 30 may be used as a mask. After the CVD silicon oxide film 4 is etched by etching, the resist may be stripped, and then the polycrystalline silicon film 3 and the buffer oxide film 2 may be etched using the CVD silicon oxide film as a mask.

Next, a groove 6 serving as an element isolation is formed on the silicon substrate 1 by RIE (FIG. 3A). At this time, the CVD silicon oxide film 4 functions as a mask. The depth of the groove 6 formed on the silicon substrate is 0.3
Desirably, it is -0.7 μm.

Next, thermal oxidation of 20 to 50 nm is performed to protect the side wall of the groove 6 and to round off the corner at the entrance of the groove 6 on the surface of the silicon substrate 1. At this time, impurity ions may be implanted through the thermal oxide film to increase the element isolation capability.

Next, after the above thermal oxidation, a CVD silicon oxide film (for example, TEOS) 7 is deposited from the bottom of the groove 6 to above the CVD silicon oxide film 4 (FIG. 3B).
Next, the polysilicon 3 of the mask material is exposed, and the difference in height between the polysilicon 3 and the CVD silicon oxide film 7 is 10
Etch back until 0-200 nm. For this etchback, an etchback technique using a resist may be used, or polishing may be used.

As shown in FIG. 4A, the CVD silicon oxide film of the trench filling material is etched, the polycrystalline silicon 3 of the mask material is exposed, and the difference in height between the polycrystalline silicon 3 and the CVD silicon oxide film 7 is obtained. Is 100-200 nm, the silicon nitride 8 is then deposited up to above the polycrystalline silicon 3 (FIG. 4 (b)).

Thereafter, the silicon nitride 8 is etched back until the polycrystalline silicon 3 is exposed (FIG. 5).
(A)). Thereby, a layer of silicon nitride 8 is formed on the element isolation region. This silicon nitride layer functions as a protective film for protecting the element isolation region during the subsequent contact RIE. For this etchback, an etchback technique using a resist may be used, or polishing may be used.

Next, the polycrystalline silicon 3 as a mask material
Is removed by CDE, and the buffer oxide film 2 is
(FIG. 5B). Then, a transistor is formed in the element formation region by a known technique. AA ′ in FIG. 1 after the formation of the transistor gate electrode 9
Is shown in FIG. 6 (a).

Thereafter, a CVD silicon oxide film 10 of 500 to 1000 nm is deposited for flattening and insulation, and the surface is flattened by polishing or remelting at a temperature of about 850 ° C. FIG. 6B is a cross-sectional view of the process along AA 'at this time. In this step, a phosphorus glass (BPSG) containing boron may be used instead of the CVD silicon oxide film for planarization and insulation.

Next, a resist is applied on the CVD silicon oxide film, and the resist is removed only by a photolithography technique at a portion where a contact hole is to be formed. At this time, in the case where the width of the element region where the contact is to be made is so small that a sufficient contact size cannot be obtained, the resist is slightly opened. CVD silicon oxide film 1
0 is etched according to the resist pattern at the time of contact RIE, and a contact hole reaching the silicon substrate 1 is formed on the element region by this etching. However, if the conditions of the contact RIE are selected such that the etching rate of the silicon nitride is sufficiently slower than the etching rate of the silicon oxide film, the contact RIE reaches the silicon nitride 8 on the element isolation region. Stuck. Therefore, as shown in FIG. 7A, the contact holes are formed in a self-aligned manner with respect to the element isolation region. This cross section is a BB 'cross section in FIG.

Thereafter, when a wiring layer is formed by sputtering Al and patterned, a wiring between the elements is completed (FIG. 7B). Further, a passivation film is formed thereon, and a pad opening is performed. finish.

As described above, as shown in this embodiment, by using the present invention, a contact can be formed in a self-alignment manner with respect to an element isolation region. Thus, it is possible to open a contact having the same width as the width of the element region even in the element region having a small width. In addition, since the opening of the contact hole (portion indicated by l in FIG. 7A) can be made larger than the actual contact or the width of the element region, the contact becomes smaller as the element becomes smaller than before. The increase in the aspect ratio of the hole can be suppressed. Also, even if misalignment occurs in the process of opening the contact, the element isolation region is protected by the silicon nitride film so that it is not cut by the contact RIE and a short circuit between the diffusion layer of the transistor and the substrate is avoided. Is done.

Next, another embodiment according to the present invention will be described. FIG. 8 is a plan view of a semiconductor device according to another embodiment of the present invention. Device area 51 and LOC on semiconductor substrate
An element isolation region 54 of OS is formed, and a gate electrode 8 and a contact 53 are further formed to constitute a transistor.

A manufacturing process according to another embodiment of the present invention will be described below with reference to FIGS. First, an oxide film 60 for element isolation is formed on the semiconductor substrate 1 by the LOCOS method to isolate element regions (FIG. 9A). Then, a gate oxide film 61 and a gate electrode 8 of the transistor are formed on the element region by a known technique. FIG. 9B is a cross-sectional view taken along the line AA ′ in FIG. 8 at this stage.

Next, silicon nitride 62 is formed to a thickness of 50-100 nm.
Then, a resist 63 is applied, and a pattern for ion implantation of a diffusion layer of the transistor is transferred and formed by photolithography. Thereafter, the silicon nitride 62 is etched by RIE using the resist pattern 63 as a mask. FIG. 9C shows a cross-sectional view taken along the line BB ′ in FIG. 8 at this time. Subsequently, impurities are implanted into the diffusion layer of the transistor using the resist pattern 63 as a mask. In the present embodiment, since it is assumed that an N-channel transistor is formed on a P-type substrate, the impurity implantation performed here is assumed to be an N-type impurity implantation. Thereafter, when the resist is peeled off, the cross section taken along the line BB ′ in FIG. 8 is as shown in FIG.

In the above process, the etching of the silicon nitride film and the implantation of the impurity in the transistor diffusion layer are performed by the same resist mask.
And the pattern of the transistor diffusion layer 63 are formed in a self-aligned manner.

Next, a 500-1000 nm CVD silicon oxide film 64 is deposited for planarization and insulation, and the surface is planarized by polishing or remelting at a temperature of about 850 ° C. FIG. 1 is a cross-sectional view of the process along AA 'at this time.
0 (b). In this step, a phosphorus glass (BPSG) containing boron may be used instead of the CVD silicon oxide film for planarization and insulation.

Next, a resist 65 is applied on the CVD silicon oxide film, and the resist is removed only by a photolithography technique at a portion where a contact hole is to be formed.
At this time, in a place where the width of the element region where the contact is to be made is narrow and a sufficient contact size cannot be obtained,
Open the resist slightly larger. The CVD silicon oxide film 64 forms a resist pattern 65 during contact RIE.
The contact hole reaching the silicon substrate 1 is formed by this etching in a place where the silicon nitride film 62 is not formed. However, contact R
If the condition of the IE is selected such that the etching rate of the silicon nitride is sufficiently slower than the etching rate of the silicon oxide film, in a certain region of the silicon nitride film 62, the contact RIE reaches a point where the silicon RIE reaches the silicon nitride 62. Stuck. FIG. 11A shows a cross-sectional view taken along the line BB ′ in FIG. 8 at this time. As shown in FIG. 11A, the contact hole reaching the substrate is formed only in the region where the silicon nitride film 62 is not provided. And the pattern of the silicon nitride film 62 are self-aligned.

Incidentally, since the pattern of the silicon nitride film 62 and the transistor diffusion layer is also formed in a self-aligned manner as described above, the pattern of the contact hole and the transistor diffusion layer is formed in a self-aligned manner. become.

Thereafter, when a wiring layer is formed by sputtering Al and patterned, a wiring between the elements is completed (FIG. 11B). Further, a passivation film is formed thereon, and a pad opening is performed. finish.

As described above, according to this embodiment, the contact can be formed in a self-aligned manner with respect to the diffusion layer of the transistor by using the present invention. Thus, even if misalignment occurs in the process of opening the contact, the contact between the transistor diffusion layer and the substrate does not shift, and a short circuit between the diffusion layer of the transistor and the substrate is avoided.

In the following, as another embodiment of the present invention, N
Non-volatile memory with an AND type cell structure (NAN
D-type EEPROM). FIG. 12 shows such a NAND.
FIG. 2 is a schematic plan view showing a type EEPROM. The wiring layer made of Al is omitted in the figure. FIGS. 13, 14, and 15 are cross-sectional views of AA ', BB', and CC ', respectively, and FIG. 16 is an equivalent circuit diagram of a cell portion.

In this embodiment, four memory cells M1 to M1
M4 is connected in series to form a NAND cell.
The drain at one end of such a NAND cell is connected to a bit line via a selection gate SG1, and the source at the other end is connected to a common source line (ground line) via a selection gate SG2. Control gates CG1 to CG4 of each memory cell
Are arranged in a direction intersecting the bit lines BL and become the word lines WL.

Further, as shown in FIG. 13, the cell transistor has a floating gate 3 having a thickness of 100-200 nm and a floating gate 3 having a thickness of 10-30 n on a gate oxide film 21 (tunnel oxide film) having a thickness of 8-10 nm.
m insulating film 22, 300-400 nm control gate 24
Are formed by lamination. The selection transistor is
As shown in FIG. 14, a 400-600 nm gate 23 (selection gate) is formed on a 20-25 nm gate oxide film 20 (FIG. 15).

Hereinafter, referring to FIGS. 17 to 22,
A manufacturing process according to an embodiment of the present invention will be described. First, a buffer oxide film 2 having a thickness of 10 to 20 nm is formed on a silicon substrate 1, and ion implantation for adjusting a threshold value of a transistor is performed through the buffer oxide film 2.

Next, the buffer oxide film 2 is peeled off with NH 4 F, and oxidation for forming a gate oxide film of the select gate is performed to form an oxide film 20 of 20 to 25 nm. Then, a resist is applied, and a pattern of a portion where a gate oxide film of a cell transistor is to be formed is transferred and formed by photolithography. Then, the oxide film in this portion is peeled off with NH4F. Subsequently, the resist is peeled off, and 8-10 nm
Of the cell transistor gate oxide film 21 (tunnel oxide film).

Next, a polycrystalline silicon 3 having a thickness of 100 to 200 nm and a CVD silicon oxide film 4 having a thickness of 100 to 500 nm are sequentially deposited thereon. This polycrystalline silicon 3
The CVD silicon oxide film 4 serves as a mask material in a trench etching step for forming a groove (trench) 6 to be described later. Also serves as a gate.

Next, after a resist 30 is applied thereon, a trench pattern is transferred and formed by photolithography (FIG. 17A). Using the patterned resist 30 as a mask, the CVD silicon oxide film 4, polycrystalline silicon film 3, and buffer oxide film 2 are
Etching is performed by E (FIG. 17B). In the etching at this time, the CVD silicon oxide film 4, the polycrystalline silicon film 3, and the buffer oxide film 2 may be etched using the resist 30 as a mask, and the resist may be peeled off at the end, or the resist 30 may be used as a mask. After etching the CVD silicon oxide film 4, the resist is removed,
Thereafter, the polycrystalline silicon film 3 and the buffer oxide film 2 may be etched using the CVD silicon oxide film as a mask.

Next, a groove 6 serving as a device isolation is formed on the silicon substrate 1 by RIE (FIG. 18A).
At this time, the CVD silicon oxide film 4 functions as a mask. The depth of the groove 6 formed on the silicon substrate is equal to 0.1.
Desirably, it is 3-0.7 μm.

Next, thermal oxidation of 20 to 50 nm is performed to protect the side wall of the groove 6 and round the corner at the entrance of the groove 6 on the surface of the silicon substrate 1. At this time, impurity ions may be implanted through the thermal oxide film to increase the element isolation capability.

Next, after the thermal oxidation, a CVD silicon oxide film (for example, TEOS) 7 is deposited in the trench 6 from the bottom to above the CVD silicon oxide film 4 (FIG. 18).
(B)). Next, the polysilicon 3 is exposed, and the difference in height between the polysilicon 3 and the CVD silicon oxide film 7 is 10
Etching is performed until the thickness becomes 0 to 200 nm. For this etchback, an etchback technique using a resist may be used, or polishing may be used.

As shown in FIG. 19A, the CVD silicon oxide film of the resist filling material is etched to expose the polycrystalline silicon 3, and the height difference between the polycrystalline silicon 3 and the CVD silicon oxide film 7 is 100-200 nm. Then, the silicon nitride 8 is deposited up to above the polycrystalline silicon 3 (FIG. 19B).

Thereafter, silicon nitride 8 is etched back until polycrystalline silicon 3 is exposed (FIG. 20).
(A)). Thereby, a layer of silicon nitride 8 is formed on the element isolation region. This silicon nitride layer functions as a protective film for protecting the element isolation region during the subsequent contact RIE. For this etchback, an etchback technique using a resist may be used, or polishing may be used.

Next, 10 .mu.m.
An insulating film 22 of -30 nm is formed. This insulating film 22
May be an ONO film made of a silicon oxide film and a silicon nitride, or may be a single layer film of a silicon oxide. After that, remove the insulating film of the part that becomes the selection transistor,
A polycrystalline silicon film 24 is deposited thereon. FIG. 20B shows a cross section of the cell transistor portion at this time, and FIG. 21A shows a cross section of the selection transistor portion.

Next, a resist is applied, a pattern for selecting a control gate is transferred by photolithography, and the polycrystal 24, the insulating film 22 and the polycrystalline silicon 3 are sequentially etched using the resist as a mask to form a word line and a word line. When the select gate line is formed, a NAND cell is completed. FIG. 21B shows a cross section in a direction orthogonal to the word lines and the selection gate lines at this time.

In this embodiment, a tunnel oxide film is formed before the element isolation region is formed, and the polycrystalline silicon film 3 as a mask material at the time of etching back the trench filling material is used as a floating gate of a cell transistor. Although the steps have been described, a method of forming a cell transistor after forming an element isolation region as in the first embodiment may be used. Further, in this embodiment, a process of forming a transistor for a peripheral circuit is omitted.

Thereafter, a CVD silicon oxide film 10 is deposited to a thickness of 500 to 1000 nm for flattening and insulation, and the surface is flattened by polishing or remelting at a temperature of about 850 ° C. FIG. 22A is a sectional view showing a step taken along the line CC ′ at this time. In this step, a phosphorus glass (BPSG) containing boron may be used instead of the CVD silicon oxide film for planarization and insulation.

Next, a resist is applied on the CVD silicon oxide film, and the resist is removed only by a photolithography technique at a portion where a contact hole is to be formed. Then, using this as a mask, the CVD silicon oxide film is etched to form a contact hole. (A cross-sectional view taken along the line CC ′ is shown in FIG. 22B.) At this time, a silicon nitride film having resistance to etching of the CVD silicon oxide film is formed on the element isolation region. Therefore, even if the contact pattern made of the resist is opened up to the element isolation region, the contact etching on the element isolation region does not proceed any further when the silicon nitride film is reached. Therefore, as shown in FIG. 22B, the contact holes are formed in a self-alignment manner with the element isolation region.

Thereafter, after the resist is stripped off, Al is sputtered to form a wiring layer and patterning completes the wiring between the elements. Further, a passivation film is formed thereon, and a pad opening is performed. finish.
(The cross-sectional view taken along the line CC ′ is the same as FIG. 15 described above.)

As described above, as shown in this embodiment, by using the present invention, a contact can be formed in a self-aligned manner with respect to an element isolation region. Further, even if misalignment occurs in the process of opening the contact, the contact RIE is performed because the element isolation region is protected by the silicon nitride film.
And a short circuit between the diffusion layer of the transistor and the substrate is avoided.

The present invention is not limited to the NAND type EEPROM described in the above embodiment, and is particularly effective for a semiconductor device having a configuration in which a plurality of memory cells are arranged as a unit and arranged in a matrix.

[0073]

According to the present invention, it is possible to form a contact hole in a self-aligned manner with respect to an element isolation region end or a transistor diffusion layer. Therefore, the problem of the short-circuit failure between the transistor diffusion layer and the substrate due to misalignment between the contact and the element isolation region or the diffusion layer of the transistor, which was a conventional problem, can be solved.

Further, since the etching protection layer is provided for the etching for forming the contact, the region to be RIE (resist opening) at the time of RIE for forming the contact can be extended to the element isolation region. Therefore, the size of the contact hole is larger than the actual contact size from the upper end of the interlayer film (silicon oxide film) between the element and the wiring layer to the etching protection layer on the element isolation region, and the aspect ratio of the contact hole Can also be kept smaller than before.

[Brief description of the drawings]

FIG. 1 is a plan view of an embodiment according to the present invention.

FIG. 2 is a process sectional view of an embodiment according to the present invention.

FIG. 3 is a process sectional view showing a continuation of FIG. 2;

FIG. 4 is a process sectional view showing a continuation of FIG. 3;

FIG. 5 is a process sectional view showing a continuation of FIG. 4;

FIG. 6 is a process sectional view showing a continuation of FIG. 5;

FIG. 7 is a process sectional view showing a continuation of FIG. 6;

FIG. 8 is a plan view of another embodiment according to the present invention.

FIG. 9 is a process sectional view of another embodiment according to the present invention.

FIG. 10 is a process sectional view showing a continuation of FIG. 9;

FIG. 11 is a process sectional view showing a continuation of FIG. 10;

FIG. 12 is a plan view of still another embodiment according to the present invention.

FIG. 13 is a sectional view of still another embodiment according to the present invention.

FIG. 14 is a process sectional view showing a continuation of FIG. 13;

FIG. 15 is a process sectional view showing a continuation of FIG. 14;

FIG. 16 is an equivalent circuit diagram of a cell unit according to still another embodiment of the present invention.

FIG. 17 is a sectional view of still another embodiment according to the present invention.

FIG. 18 is a process sectional view showing a continuation of FIG. 17;

FIG. 19 is a process sectional view showing a continuation of FIG. 18;

FIG. 20 is a process sectional view showing a continuation of FIG. 19;

FIG. 21 is a process sectional view showing a continuation of FIG. 20;

FIG. 22 is a process sectional view showing a continuation of FIG. 21;

FIG. 23 is a plan view of a conventional example.

FIG. 24 is a process sectional view of a conventional example.

FIG. 25 is a process sectional view showing a continuation of FIG. 24;

FIG. 26 is a process sectional view showing a continuation of FIG. 25;

FIG. 27 is a process sectional view showing a continuation of FIG. 26;

FIG. 28 is a process sectional view showing a continuation of FIG. 27;

FIG. 29 is a process sectional view showing another example of a defect in the conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2 ... Buffer oxide film 3 ... Polycrystalline silicon oxide film 4 ... CVD silicon oxide film 6 ... Groove (trench) for element isolation 7 ... CVD silicon oxide film 8 ... Silicon nitride film 9 ... Polycrystalline silicon film (Gate of transistor) 10: CVD silicon oxide film for interlayer insulation 11: AI film for wiring 20: Gate oxide film of selection gate 21: Tunnel oxide film 22: Insulating film (ONO film) between floating gate and control gate 23 ... Selection gate (combined 3 and 24) 24. Control gate (polycrystalline silicon) 30. Resist 40. Trench inner wall protection oxide film 51. Element region 52. Element isolation region (trench) 53. Contact 54. Element Isolation region (LOCOS) 60 LOCOS 61 Gate oxide film 62 Silicon nitride 63 Transistor diffusion layer 64 CVD silicon oxide film for interlayer insulation 65 ... Resist

Continuation of the front page (56) References JP-A-3-126266 (JP, A) JP-A-2-105552 (JP, A) JP-A-4-177724 (JP, A) JP-A-2-15650 (JP) JP-A-5-74927 (JP, A) JP-A-62-190847 (JP, A) JP-A-3-142933 (JP, A) JP-A-3-285344 (JP, A) 59-55033 (JP, A) JP-A-61-107739 (JP, A) JP-A-5-299497 (JP, A) JP-A-1-125975 (JP, A) JP-A-5-36710 (JP, A) A) JP-A-2-239671 (JP, A) JP-A-5-190861 (JP, A) JP-A-2-8032 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) ) H01L 21/76 H01L 21/28 H01L 21/768

Claims (1)

(57) [Claims] 1. A step of forming a groove in a semiconductor substrate using a first insulating film patterned on a semiconductor substrate as a mask, and forming the groove to a height lower than an upper surface of the first insulating film. Embedding with an insulating film; forming a silicon nitride film on the second insulating film to the same height as the upper surface of the first insulating film; removing the first insulating film; Forming a film, and removing a silicon oxide film on an element region surrounded by the trench and opening a contact in a self-aligned manner with respect to the silicon nitride film. Device manufacturing method.