JP2000223596A - Semiconductor nonvolatile storage device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a semiconductor nonvolatile storage device, which make possible high integration by shortening the gate length of a selection transistor having a floating gate structure, and a method for manufacturing the storage device. SOLUTION: A selective transistor region of a semiconductor substrate 10, in a floating gate type semiconductor nonvolatile storage device, has a gate insulating film 20 formed in an upper layer of a channel formation region, a first conductive layer 30a formed as separated for each selective transistor in an upper layer of the gate insulating film, a second conductive layer 31b formed in an upper layer of the first conductive layer, an intermediate insulating film 22a formed in an upper layer of the second conductive layer, a third conductive layer 35 formed in an upper layer of the intermediate insulating film, and a source/drain region formed in the semiconductor substrate at both sides of the first conductive layer, as connected to the channel formation region. Then the second and third conductive layers are connected via an opening CBSG made in the intermediate insulating film in a periphery of the selective transistor region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor nonvolatile memory device and a method of manufacturing the same, and more particularly, to a semiconductor nonvolatile memory device which determines information by accumulating charges in a floating gate and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, flash memories, which have been actively developed, have a charge storage mechanism comprising a floating gate buried in a gate insulating film, a carrier trapping level discretized in the gate insulating film, and the like. This is a semiconductor non-volatile memory that determines information based on the amount of charge stored in the memory.
When the charge storage mechanism is a floating gate, the memory cell has a structure in which a tunnel oxide film formed on a semiconductor substrate, a floating gate, an interlayer insulating film, and a control gate are stacked. When a voltage is applied to the control gate, the potential of the floating gate changes due to capacitive coupling between the control gate and the floating gate, whereby writing and reading operations can be performed.

In a memory cell array in which memory cells are arranged in a matrix, writing and reading of information to and from a memory cell are performed in units of a plurality of cells. The unit of this cell is called a block. The selection transistor plays a role of selecting which cell block is activated in the cell array. The gate structure of the select transistor has a stacked structure similar to that of the memory cell due to restrictions on the manufacturing process. However, if the floating gate remains floating in the select transistor,
Since the threshold value may change during the operation of the element, the characteristics of the selection transistor become unstable. In order to prevent this, in a selection transistor, it is widely practiced to connect a floating gate to a selection gate.

In order to improve the degree of integration of memory cells, a trench for element isolation is formed in a semiconductor substrate, and the trench is filled with an insulator to form an element isolation insulating film. Shallow Trench Isolation method)
May be used. In addition, a process has been proposed in which a trench element isolation region is formed at an end of the floating gate in the width direction in a self-aligned manner. When the trench isolation and the floating gate are formed through different exposure processes, misalignment occurs between the trench isolation and the floating gate. Therefore, the floating gate is formed on the trench isolation by an amount corresponding to the misalignment. There must be. In the method of forming the floating gate and the trench element isolation in a self-aligned manner, the misalignment described above is eliminated, and it is not necessary to form the floating gate on the trench element isolation, so that the integration degree can be further improved.

FIG. 14 is a plan view of a semiconductor nonvolatile memory device when a floating gate and a trench element isolation are formed in a self-aligned manner. Active region A of silicon semiconductor substrate separated by trench type element isolation insulating film STI
R and a word line (WL1, W
L2,..., WL16) (in the hatched portion in the drawing), the word lines (WL1, WL2,.
6) and a floating gate FG covered with an insulating film is formed between the channel formation region of the silicon semiconductor substrate. Further, source / drain diffusion layers are formed in the substrate on both sides of the floating gate FG. A plurality of memory transistors MT, which are field effect transistors having a floating gate FG covered with an insulating film, are connected in series between the word lines (WL1, WL2,..., WL16) and the channel formation region in the semiconductor substrate.
An AND column is formed.

Further, a bit line side select MOS transistor BS for selecting the NAND line by a bit line side select gate BSG is provided at an end of the NAND line on the bit line side.
T is formed, and its drain diffusion layer is connected to a bit line (not shown) via a bit contact BC. On the other hand, a source line side select MOS transistor SST is also formed by a source line side select gate SSG at the source line side end of the NAND string, and its source diffusion layer is connected to the source line SL. In the above-mentioned bit line side selection gate BSG and source line side selection gate SSG, regions crossing the active region AR (shaded portions in the figure) in the same manner as the memory transistors due to limitations in the manufacturing process.
, The floating gate FG is left. Therefore, in the selection transistors (bit line side and source line side), means for connecting the selection gate and the floating gate FG for each transistor (bit line side and source line side) is required. In the semiconductor nonvolatile memory device shown in FIG. 14, the floating gate FG of each select transistor is connected to the bit line side select gate connection hole _CBSG and the source line side select gate connection hole _CSSG .

C- which is a select gate portion in FIG.
FIGS. 15A and 15B are cross-sectional views of C ′ and DD ′, respectively. Trench type element isolation insulating film 21
A gate insulating film 20 made of, for example, a thin silicon oxide is formed on the active region of the semiconductor substrate 10 separated by the above process, and a floating gate 30a made of polysilicon or the like is formed on the gate insulating film 20. An intermediate insulating film 22a formed of, for example, an ONO film (laminated insulating film of oxide film-nitride film-oxide film) is formed. A connection hole _CBSG for a bit line side select gate for connecting the bit line side select gate and the floating gate 30a is opened in the intermediate insulating film 22a. Upper layer, for example a polysilicon layer on the intermediate insulating film (32a, 33a) and a tungsten silicide layer 34a bit line side select gate 35 is a laminate of is formed, connecting said bit line side select gate hole C _BSG Through the floating gate 30a. Source / drain diffusion layers (not shown) are formed in the semiconductor substrate 10 on both sides of the floating gate 30a.
A selection transistor in which a is connected to the bit line side selection gate 35 is formed. On the other hand, the source line side select gate also has a structure similar to the above, in which the floating gate is connected to the source line side select gate via the source line side select gate connection hole _CSSG .

A method for manufacturing the above-mentioned semiconductor nonvolatile memory device will be described with reference to the drawings. First, FIG.
((A) corresponds to a cross-sectional view taken along the line CC ′ in FIG. 14, and (b) corresponds to a cross-sectional view taken along the line DD ′ in FIG. 14). An absolute green film 20 is formed. Further, for example, CVD (Chemic
The floating gate layer 30 is formed by depositing polysilicon or amorphous silicon by an Al Vapor Deposition method. Next, a resist film R1 having a pattern for opening a region where a trench element isolation is to be formed is formed by a photolithography process.

Next, FIG. 17 (a) shows a line CC 'in FIG.
14B, and FIG. 14B corresponds to a cross-sectional view taken along line DD ′ in FIG. 14). Etching such as RIE (reactive ion etching) is performed using the resist film R1 as a mask to form a floating gate. The layer 30, the gate insulating film 20, and the semiconductor substrate 10 are sequentially etched to form a trench T for element isolation.

Next, FIG. 18 (a) is a sectional view taken along the line CC 'in FIG.
14B, and FIG. 14B corresponds to a cross-sectional view taken along line DD ′ in FIG. 14). After removing the resist film R1, an insulator such as silicon oxide is deposited on the entire surface by, for example, a CVD method. Then, the element isolation insulating film 21 is formed by etching back by etching such as RIE to leave an insulator only inside the element isolation groove.

Next, FIG. 19 ((a) shows CC ′ in FIG.
As shown in FIG. 14, (b) corresponds to a cross-sectional view taken along line DD ′ in FIG. 14). An insulating film 22 is formed. Next, a polysilicon layer 32 is formed by, for example, a CVD method.

Next, FIG. 20 ((a) shows CC ′ in FIG.
Sectional view of a resist film R3 of (b), as shown in a cross-sectional view) in FIG. 14 D-D ', the pattern of a connection hole C _BSG bit line side select gate by a photolithography process Form.

Next, FIG. 21 ((a) is a sectional view taken along the line CC 'in FIG.
14B, and FIG. 14B corresponds to a cross-sectional view taken along line DD ′ in FIG. 14). Etching such as RIE is performed using the resist film R3 as a mask to form the polysilicon layer 32 and the intermediate insulating film 22. Are sequentially etched to open a bit line side select gate connection hole _CBSG .

Next, FIG. 22 ((a) shows CC ′ in FIG.
14B, and FIG. 14B corresponds to a cross-sectional view taken along line DD ′ in FIG. 14). After the resist film R3 is removed, the inside of the bit line side select gate connection hole _CBSG is removed, for example, by the CVD method. And a polysilicon layer 33 and a tungsten silicide layer 34 are laminated.

Next, a resist film (not shown) having a pattern of a bit line side select gate is formed by a photolithography process.
Is formed, and etching such as RIE is performed to form a tungsten silicide layer 34 and a polysilicon layer (32, 3).
3), the intermediate insulating film 22 and the floating gate layer 30 are sequentially patterned, and as shown in FIG. 15, the bit line side select gate 3 which is a laminate of the polysilicon layers (32a, 33a) and the tungsten silicide layer 34a.
5 and a floating gate 30a connected to the bit line side select gate 35 via the bit line side select gate connection hole _CBSG . In the subsequent steps, for example, an interlayer insulating film such as silicon oxide is formed, and a contact such as a bit contact is opened to form an upper layer wiring such as a bit line, thereby forming a desired semiconductor nonvolatile memory device.

[0016]

However, in the above-described semiconductor nonvolatile memory device, a margin for alignment between the bit line side select gate connection hole _CBSG and the bit line side select gate 35 is increased in forming the select gate. Therefore, there is a problem that high integration of the semiconductor nonvolatile memory device is hindered.

In the above semiconductor nonvolatile memory device,
The case where the photoresist is misaligned when forming the layout pattern of the bit line side selection gate 35 with respect to the bit line side selection gate connection hole _CBSG will be described with reference to the drawings. As shown in FIG. 23A, when the resist film R4 of the bit line side select gate pattern is misaligned, and the end of the resist film R4 is in the bit line side select gate connection hole _CBSG . I do.

In the etching of the bit line side select gate, the intermediate insulating film 22 serves as an etching stopper. But,
The end of the resist R4 has a connection hole C for the bit line side select gate.
_23B , the etching proceeds because there is no intermediate insulating film 22 serving as an etching stopper, as shown in FIG. _23B . In X, even the floating gate 30 is etched.

As shown in FIG. 24, in the memory transistor region, a polysilicon layer (32, 33) and a tungsten silicide layer are formed above the element isolation trench T, that is, above a region sandwiched by the floating gate layer 30. The thickness of the control gate 35 made of
The thickness is, for example, about twice as large as the thickness of the control gate 35 on the floating gate layer 30. In addition, when the floating gate is etched, an over-etch is usually added, so that the depth at which the floating gate is etched becomes greater than the thickness of the control gate.

As described above, the floating gate 30 is located inside the connection hole C _BSG for the bit line side select gate.
From the state etched to, the intermediate insulating film 22
When the floating gate is etched after etching, the floating gate 30 in the inside X of the bit line side select gate connection hole _CBSG becomes thinner than other portions as shown in FIG. Therefore, while the other thick portion is being etched, the etching of the thin portion in the inside X of the bit line side select gate connection hole _CBSG ends. Therefore, the exposed gate insulating film 20 and even the semiconductor substrate 10 are etched.

As described above, even if the resist film R4 of the bit line side select gate pattern is misaligned, the bit line side select gate connection hole C is formed to prevent the semiconductor substrate 10 and the like from being etched. _It is necessary to increase the margin for matching between the _BSG and the bit line side selection gate 35. When the misalignment is set to F / 2 (F is the minimum design size), the gate length of the bit line side select gate is 2F even if the bit line side select gate connection hole _CBSG is formed with the minimum design size. In the NAND-type semiconductor nonvolatile memory device shown in FIG. 14, since the selection transistor is provided on each of the bit line side and the source line side, the size of 4F is required only by the gate of the selection transistor, and the high integration of the cell array is greatly increased. It will be hindered.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a selection transistor of a semiconductor nonvolatile memory device having a floating gate structure memory transistor, in which the floating gate and the selection gate are connected. Accordingly, it is an object of the present invention to provide a semiconductor nonvolatile memory device capable of shortening the gate length of a select transistor and achieving high integration, and a method of manufacturing the same.

[0023]

In order to achieve the above object, a semiconductor nonvolatile memory device according to the present invention comprises a memory transistor having a floating gate and a selection transistor for selecting the memory transistor. In a nonvolatile memory device, in a select transistor region of a semiconductor substrate having a channel formation region,
A gate insulating film formed on the channel forming region, a first conductive layer formed separately on the gate insulating film for each of the select transistors, and formed on the first conductive layer; A second conductive layer, an intermediate insulating film formed on the second conductive layer, a third conductive layer formed on the intermediate insulating film, and the semiconductor substrate on both sides of the first conductive layer And a source / drain region formed in connection with the channel forming region, wherein the second conductive layer and the third conductive layer are connected in a peripheral region of the select transistor region.

In the above-described semiconductor nonvolatile memory device, preferably, an opening is formed in the intermediate insulating film in a peripheral region of the selection transistor region, and the opening is used to form the second conductive layer and the third conductive layer. The conductive layer is connected.

In the above-mentioned semiconductor nonvolatile memory device, preferably, a plurality of the select transistors are formed adjacent to each other, and the second conductive layer is connected between the plurality of the select transistors adjacent to each other. The third conductive layer is connected between a plurality of adjacent select transistors.

In the above-mentioned semiconductor nonvolatile memory device, preferably, an element isolation groove is formed in the semiconductor substrate,
An insulator is buried in the element isolation groove to form an element isolation insulating film. More preferably, the element isolation groove is formed in a self-aligned manner with the first conductive layer.

In the above-mentioned semiconductor nonvolatile memory device, preferably, the thickness of the second conductive layer is smaller than that of the first conductive layer.

According to the above semiconductor nonvolatile memory device,
In a floating gate type semiconductor nonvolatile memory device isolated by a trench element isolation method or the like, in a select transistor region of a semiconductor substrate, a gate insulating film formed over a channel formation region and a select transistor over a gate insulating film A first conductive layer (floating gate) formed separately for each, and a second conductive layer (floating gate connection layer) formed on the first conductive layer
And an intermediate insulating film formed on the second conductive layer, and a third conductive layer (select gate) formed on the intermediate insulating film
And a source / drain region formed in the semiconductor substrate on both sides of the first conductive layer so as to be connected to a channel formation region, and the second conductive layer and the third conductive layer are formed in a peripheral region of the select transistor region. Are connected via an opening formed in the intermediate insulating film.

Therefore, the second conductive layer formed on the first conductive layer separated for each selection transistor is connected to each first conductive layer, and the second conductive layer and the third conductive layer are connected to each other. Since the connection is made through the opening formed in the intermediate insulating film in the peripheral region of the selection transistor region, it is not necessary to individually connect the third conductive layer and the first conductive layer. Third
It is sufficient that the conductive layer and the second conductive layer are connected at a single point in the peripheral region of the select transistor region, so that each select transistor has a structure in which the intermediate insulating film remains. Therefore, even if misalignment of the select gate pattern occurs, the semiconductor substrate is not etched, and the select gate can be designed with a minimum design dimension to shorten the gate length of the select transistor, thereby further increasing the integration. Is possible.

According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor nonvolatile memory device, comprising: a memory transistor having a floating gate; and a selection transistor for selecting the memory transistor. A method of manufacturing a storage device, comprising: forming a gate insulating film on an upper layer of a channel formation region in a selection transistor formation region of a semiconductor substrate having a channel formation region;
Forming a conductive layer, and forming a second layer on the first conductive layer.
Forming a conductive layer, forming an intermediate insulating film on the second conductive layer, and forming a conductive layer in the select transistor forming region so as to connect to the second conductive layer in a peripheral region of the select transistor forming region. Forming a third conductive layer on the intermediate insulating film; and forming source / drain regions in the semiconductor substrate on both sides of the first conductive layer by connecting to the channel formation region. .

In the method of manufacturing a semiconductor nonvolatile memory device, preferably, after the step of forming the intermediate insulating film and before the step of forming the third conductive layer, the periphery of the select transistor formation region is formed. Forming an opening in the intermediate insulating film in the region; and forming the third conductive layer so that the opening connects the second conductive layer and the third conductive layer. Form.

In the method of manufacturing a semiconductor nonvolatile memory device described above, preferably, in the step of forming a plurality of select transistors adjacent to each other and forming a second conductive layer, the plurality of select transistors are adjacent to each other. In the step of forming the third conductive layer so as to be connected between the plurality of select transistors, the third conductive layer is formed so as to be connected between the plurality of adjacent select transistors.

In the method of manufacturing a semiconductor nonvolatile memory device, preferably, after the step of forming the first conductive layer, before the step of forming the second conductive layer, the step of forming the first conductive layer is performed. The method further includes forming a device isolation groove in the semiconductor substrate along the pattern, and forming an element isolation insulating film by filling the device isolation groove with an insulator. More preferably, the step of forming the element isolation insulating film includes:
A step of forming an insulator over the entire surface by burying the element isolation groove; and a step of removing the insulator outside the element isolation groove.

In the method of manufacturing a semiconductor nonvolatile memory device described above, preferably, in the step of forming the second conductive layer, the second conductive layer is formed thinner than the first conductive layer.

The method of manufacturing a semiconductor nonvolatile memory device described above is a method of manufacturing a floating gate type semiconductor nonvolatile memory device separated by a trench element isolation method or the like. Forming a gate insulating film over the channel formation region, forming a first conductive layer over the gate insulating film, forming a second conductive layer over the first conductive layer,
An intermediate insulating film is formed on the second conductive layer. Next, after an opening is formed in the intermediate insulating film in the peripheral region of the selection transistor formation region, a second layer is formed above the intermediate insulation film in the selection transistor formation region so as to be connected to the second conductive layer through the opening. Three conductive layers are formed. Next, source / drain regions are formed in the semiconductor substrate on both sides of the first conductive layer so as to be connected to the channel formation region.

According to the method of manufacturing a semiconductor nonvolatile memory device described above, the second conductive layer formed on the first conductive layer and the third conductive layer formed with the intermediate insulating film interposed therebetween are formed in the select transistor formation region. By connecting via the opening formed in the intermediate insulating film in the peripheral region, it is not necessary to individually connect the third conductive layer and the first conductive layer. For this reason, it is possible to have a structure in which the intermediate insulating film remains in each of the select transistors, and even if misalignment of the select gate pattern occurs, the semiconductor substrate is not etched and the select gate Can be designed with the minimum design size to shorten the gate length of the select transistor, and further higher integration can be achieved.

[0037]

Embodiments of the present invention will be described below with reference to the drawings.

First Embodiment A semiconductor device according to this embodiment will be described with reference to the drawings. FIG. 1 is a plan view of the semiconductor nonvolatile memory device according to the present embodiment. Trench type element isolation insulating film ST
An active region AR of the silicon semiconductor substrate separated by I,
Word lines (WL1, WL2,
, WL16) (the hatched portions in the figure), a floating gate FG covered with an insulating film is formed between the word lines (WL1, WL2,..., WL16) and the channel formation region of the silicon semiconductor substrate. Have been.
Further, source / drain diffusion layers are formed in the substrate on both sides of the floating gate FG. A plurality of memory transistors MT, which are field-effect transistors having a floating gate FG covered with an insulating film, are connected in series between word lines (WL1, WL2,..., WL16) and a channel formation region in a semiconductor substrate.
Make up the columns.

Further, a bit line side select MOS transistor BS for selecting the NAND line by a bit line side select gate BSG is provided at the bit line side end of the NAND line.
T is formed, and its drain diffusion layer is connected to a bit line (not shown) via a bit contact BC. On the other hand, a source line side select MOS transistor SST is also formed by a source line side select gate SSG at the source line side end of the NAND string, and its source diffusion layer is connected to the source line SL. In the above-mentioned bit line side selection gate BSG and source line side selection gate SSG, regions crossing the active region AR (shaded portions in the figure) in the same manner as the memory transistors due to limitations in the manufacturing process.
, The floating gate FG (first conductive layer) is left. Each floating gate FG is connected to a floating gate connection layer (second conductive layer) made of polysilicon or the like above it. Furthermore, an intermediate insulating film made of, for example, an ONO film (a stacked insulating film of an oxide film-nitride film-oxide film) and a stacked electrode having a polycide structure of polysilicon and tungsten silicide (bit line side and source line) are formed on the upper layer. Side) Select gate (third conductive layer) is formed. Here, the floating gate connection layer (second conductive layer) and the selection gate (third conductive layer) on the bit line side and the source line side are connected to the bit line side selection gate connection hole _CBSG and the source line side selection gate. Each connection is made by a connection hole C _SSG . As a result, each floating gate (first conductive layer) FG is connected to the selection gate (third conductive layer) on the bit line side and the source line side.

AA ', which is a selection gate portion in FIG.
FIGS. 2A and 2B are cross-sectional views taken along the line BB ′.
(B). A gate insulating film 20 made of, for example, a thin silicon oxide is formed on the active region of the semiconductor substrate 10 separated by the trench-type element isolation insulating film 21, and a floating gate (the A first conductive layer) 30a is formed, a floating gate connection layer (second conductive layer) 31b made of, for example, polysilicon is formed thereon, and an ONO film (oxide film-nitride film) is further formed thereon. An intermediate insulating film 22a made of a stacked insulating film of an oxide film) is formed. A connection hole _CBSG for a bit line side select gate for connecting the bit line side select gate and the floating gate 30a is opened in the intermediate insulating film 22a. As an upper layer of the intermediate insulating film, for example, a polysilicon layer (32a, 3
3a) and a bit line side select gate (third conductive layer) 35 having a polycide structure, which is a stacked body of the tungsten silicide layer 34a, is formed, and is floating through the bit line side select gate connection hole _CBSG. It is connected to a gate connection layer (second conductive layer) 31b. Further, source / drain diffusion layers (not shown) are formed in the semiconductor substrate 10 on both sides of the floating gate (first conductive layer) 30a, so that the floating gate connection layer (second Conductive layer) 31b
As a result, a select transistor in which the floating gate (first conductive layer) 30a is connected to the bit line side select gate (third conductive layer) 35 is formed. On the other hand, in the source line side select gate, the floating gate is connected to the source line side select gate connection hole C by the same structure as described above.
_It has a structure connected to the source line side select gate via _SSG .

A method for manufacturing the above-described semiconductor nonvolatile memory device will be described with reference to the drawings. First, FIG.
((A) is a cross-sectional view taken along the line AA 'in FIG. 1, and (b) is a cross-sectional view taken along the line BB' in FIG. 1). An absolute green film 20 is formed. Furthermore, for example, CVD (Chemical
Polysilicon or amorphous silicon is deposited by a vapor deposition method, and a floating gate layer 30 is formed with a thickness of 250 nm. Next, a resist film R1 having a pattern for opening a region where a trench element isolation is to be formed is formed by a photolithography process.

Next, as shown in FIG. 4 ((a) is a cross-sectional view taken along the line AA ′ in FIG. 1, and (b) is a cross-sectional view taken along the line BB ′ in FIG. 1). Is used as a mask, etching such as RIE (reactive ion etching) is performed, and the layer 30 for the floating gate, the gate insulating film 20, and the semiconductor substrate 10 are sequentially etched to form the trench T for element isolation.

Next, as shown in FIG. 5 ((a) is a cross-sectional view taken along the line AA 'in FIG. 1, and (b) is a cross-sectional view taken along the line BB' in FIG. 1). Is removed, an insulator such as silicon oxide is deposited on the entire surface by, for example, a CVD method, and etched back by etching such as RIE to leave the insulator only inside the element isolation groove, thereby forming an element isolation insulating film 21. I do.

Next, as shown in FIG. 6 ((a) is a cross-sectional view taken along the line AA 'in FIG. 1, and (b) is a cross-sectional view taken along the line BB' in FIG. 1). To cover the floating gate layer 30 and deposit polysilicon over the entire surface.
It is formed with a thickness of 0 nm. Next, a resist film R2 that protects the pattern P1 region in FIG. 1 is formed by a photolithography process. At this time, it is sufficient that at least a part of the region protected by the resist film R2 overlaps the bit line side select gate and does not cover the memory transistor region, and strict alignment is not necessary. You don't have to.

Next, as shown in FIG. 7 ((a) is a cross-sectional view taken along the line AA 'in FIG. 1, and (b) is a cross-sectional view taken along the line BB' in FIG. 1). Is etched using RIE as a mask, and the pattern P in FIG.
Then, the floating gate connection layer 31a is processed into a single layer.
After that, the resist film R2 is removed.

Next, as shown in FIG. 8 ((a) is a cross-sectional view taken along the line AA 'in FIG. 1, and (b) is a cross-sectional view taken along the line BB' in FIG. 1). To cover the floating gate connecting layer 31a to form an intermediate insulating film 22 made of an ONO film (a stacked insulating film of an oxide film-nitride film-oxide film). Next, a polysilicon layer 32 is formed by, for example, a CVD method.

Next, as shown in FIG. 9 ((a) is a sectional view taken along the line AA 'in FIG. 1, and (b) is a sectional view taken along the line BB' in FIG. 1). Thereby, a resist film R3 having a pattern that opens the bit line side select gate connection hole _CBSG in the peripheral region of the select transistor region is formed. Next, etching such as RIE is performed using the resist film R3 as a mask, and the polysilicon layer 32 and the intermediate insulating film 22 are etched in this order to open the bit line side select gate connection hole _CBSG .

Next, as shown in FIG. 10 ((a) is a cross-sectional view taken along the line AA ′ in FIG. 1, and (b) is a cross-sectional view taken along the line BB ′ in FIG. 1). Then, the polysilicon layer 33 and the tungsten silicide layer 34 are stacked by covering the inside of the bit line side select gate connection hole _CBSG by, for example, the CVD method. Next, a resist film R4 having a bit line side select gate pattern for protecting the pattern P2 region in FIG. 1 is formed by a photolithography process.

Next, RI is performed using the resist film R4 as a mask.
Etching such as E, the tungsten silicide layer 34, the polysilicon layers (32, 33), the intermediate insulating film 2
2. The floating gate connection layer 31a and the floating gate layer 30 are sequentially patterned, and as shown in FIG. 2, a bit line having a polycide structure, which is a laminate of a polysilicon layer (32a, 33a) and a tungsten silicide layer 34a. The floating gate connecting layer 31b and the floating gate 30a are connected to the side selection gate 35 and the bit line side selection gate 35 via the bit line side selection gate connection hole _CBSG . In the subsequent steps, for example, an interlayer insulating film such as silicon oxide is formed,
Opening a contact such as a bit contact to form an upper layer wiring such as a bit line, thereby forming a desired semiconductor nonvolatile memory device.

In the semiconductor nonvolatile memory device of the present embodiment, the second conductive layer formed on the first conductive layer separated for each selection transistor is connected to each first conductive layer. Since the second conductive layer and the third conductive layer are connected through an opening formed in the intermediate insulating film in a peripheral region of the select transistor region, the third conductive layer and the second conductive layer are connected to each other by the select transistor. It is sufficient to make a connection at one point in the peripheral region of the region, and there is no need to individually connect the third conductive layer and the first conductive layer. In the above-described structure, since the intermediate insulating film is left as it is in each of the select transistors, the misalignment may occur even when the resist film of the select gate pattern is formed as shown in FIG. The etching stops once at the intermediate insulating film, and the second conductive layer and the first
The conductive layer is etched. At this time, when misalignment occurs, it is necessary to etch a region having a different thickness of polysilicon by the thickness of the second conductive layer. For example, a first conductive layer (floating gate) having a thickness of 250 nm is required. Since the thickness of the second conductive layer (floating gate connection layer) 31b is formed to be as thin as 100 nm with respect to 30a, the difference in relative film thickness is small. The gate can be designed with the minimum design size to shorten the gate length of the select transistor, and further high integration can be achieved.

Further, in the above embodiment, FIG.
As shown in (1), the pattern of the bit line side select gate may be wider than the floating gate connection layer 31a. The pattern of the floating gate connection layer 31a is not limited as long as it is connected to each floating gate 30a and connected to the bit line side selection gate 35 via the bit line side selection gate connection hole _CBSG .

Second Embodiment A semiconductor device according to this embodiment will be described with reference to the drawings. FIG. 13 is a plan view of the semiconductor nonvolatile memory device according to the present embodiment. The semiconductor nonvolatile memory device according to the present embodiment is almost the same as the semiconductor nonvolatile memory device according to the first embodiment, except that two NAND strings in which a plurality of memory transistors MT are connected in series have one bit. It has a shared bit line structure sharing the contact BC. In order to determine which of the two NAND strings is to be selected, two select transistors (BSGa, BSGb) are connected in series on the bit line side, and one select transistor is connected to one NAND string. It is a depression type transistor DT. By selecting one of the selection transistors (BSGa, BSGb), it is possible to select a NAND string corresponding to each of them.

In the semiconductor non-volatile memory device having the above structure, the floating gate connection layer is patterned along the pattern P1 in FIG. 13, and is changed to the two select transistor patterns (P2a, P2b) in a later step. The first embodiment can be manufactured in the same manner by processing the bit line-side selection gate along.

In the case of the above-mentioned shared bit line structure, in the conventional method of providing a connection hole in the selection gate, each of the three selection transistors on the bit side and the source side has 2F (F is a minimum design). Dimensions) are required, so a length of 6F is required only for the selection transistor. In the present embodiment, the selection gate and the floating gate are connected via the floating gate connection layer. The length is 3F, and higher integration is possible.

The present invention is not limited to the above embodiment. For example, the floating gate (first conductive layer), the floating gate connection layer (second conductive layer), or the select gate (third conductive layer) may have a single-layer structure or a multilayer structure. Further, the storage device is not limited to the NAND type, but can be applied to, for example, a DINOR type. In addition, various changes can be made without departing from the spirit of the present invention.

[0056]

As described above, according to the semiconductor non-volatile memory device of the present invention, it is possible to provide a semiconductor non-volatile memory device in which the gate length of the select transistor can be shortened and higher integration can be achieved. It is.

Further, according to the method of manufacturing a semiconductor nonvolatile memory device of the present invention, the semiconductor nonvolatile memory device of the present invention can be easily manufactured, and the gate length of the select transistor can be shortened to achieve higher integration. It is possible to manufacture a simple semiconductor nonvolatile memory device.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor nonvolatile memory device according to a first embodiment.

FIG. 2A is a cross-sectional view taken along line AA ′ in FIG.
FIG. 2B is a cross-sectional view taken along line BB ′ in FIG.

FIG. 3 is a sectional view up to a step of forming a resist film having a trench element isolation pattern in the method for manufacturing a semiconductor nonvolatile memory device according to the first embodiment;
1 corresponds to a cross-sectional view taken along the line AA ′ in FIG. 1, and FIG.

FIG. 4 is a cross-sectional view up to the step of forming an element isolation groove, which is a continuation step of FIG. 3, and (a) is AA ′ in FIG. 1;
(B) is equivalent to the sectional view in BB '.

FIG. 5 is a cross-sectional view up to the step of forming an element isolation insulating film, which is a continuation step of FIG. 4, and FIG.
A ′ and (b) correspond to a cross-sectional view taken along line BB ′.

6 is a cross-sectional view up to the step of forming a resist film having a pattern of a floating gate connection layer, which is a continuation step of FIG. 5, (a) is AA ′ in FIG. 1, (b) is B-
This corresponds to a cross-sectional view at B ′.

FIG. 7 is a cross-sectional view up to the step of patterning the floating gate connecting layer, which is a continuation step of FIG. 6,
1A corresponds to a cross-sectional view taken along line AA ′ in FIG. 1, and FIG. 1B corresponds to a cross-sectional view taken along line BB ′.

FIG. 8 is a cross-sectional view up to the step of forming a polysilicon layer that is a part of the select gate, which is a continuation step of FIG. 7,
1A corresponds to a cross-sectional view taken along line AA ′ in FIG. 1, and FIG. 1B corresponds to a cross-sectional view taken along line BB ′.

FIG. 9 is a cross-sectional view up to the step of opening a connection hole for a select gate, which is a continuation step of FIG. 8, and FIG.
A ′ and (b) correspond to a cross-sectional view taken along line BB ′.

10 is a cross-sectional view up to a step of forming a select gate, which is a continuation step of FIG. 9, and FIG.
A ′ and (b) correspond to a cross-sectional view taken along line BB ′.

FIG. 11 is a cross-sectional view showing (a) a process of forming a resist film of a select gate pattern and (b) a process of patterning a select gate when a resist film of a select gate pattern is misaligned. is there.

FIG. 12 is a cross-sectional view when the pattern of the selection gate is wider than the floating gate connection layer.

FIG. 13 is a plan view of a semiconductor nonvolatile memory device according to a second embodiment.

FIG. 14 is a plan view of a conventional semiconductor nonvolatile memory device.

15A is a sectional view taken along the line CC ′ in FIG. 14, and FIG. 15B is a sectional view taken along the line DD ′ in FIG.

FIG. 16 is a cross-sectional view up to a step of forming a resist film having a trench element isolation pattern in a method for manufacturing a semiconductor nonvolatile memory device according to a conventional example, and FIG. , (B) correspond to a cross-sectional view along DD ′.

17 is a cross-sectional view up to a step of forming an element isolation groove, which is a continuation step of FIG. 16; FIG.
-C 'and (b) correspond to a cross-sectional view along DD'.

18 is a cross-sectional view up to the step of forming an element isolation insulating film, which is a continuation step of FIG. 17; FIG. 18A is a cross-sectional view taken along the line CC ′ in FIG. FIG.

19 is a cross-sectional view up to the step of forming a polysilicon layer which is a part of a select gate, which is a continuation step of FIG. 18, (a) is CC ′ in FIG. 14, and (b) is This corresponds to a cross-sectional view taken along line DD ′.

20 is a cross-sectional view up to the step of forming a resist film of an opening pattern of a connection hole for a select gate, which is a step subsequent to that of FIG. 19, and (a) is CC ′ in FIG. 14, (b) Is D
This corresponds to a cross-sectional view at -D '.

21 is a cross-sectional view up to the step of opening a connection hole for a select gate, which is a continuation step of FIG. 20, and FIG.
4, CC ′ and (b) correspond to cross-sectional views along DD ′.

FIG. 22 is a cross-sectional view up to the step of forming a select gate, which is a continuation step of FIG. 20, and FIG.
C ′ and (b) correspond to a cross-sectional view taken along line DD ′.

FIGS. 23A and 23B are (a) up to a step of forming a resist film of a select gate pattern and (b) a step of processing a select gate pattern when a resist film of a select gate pattern is misaligned, and (c) floating. FIG. 4 is a cross-sectional view showing up to a gate pattern processing step.

FIG. 24 is a cross-sectional view of a memory transistor region in a plane parallel to CC in FIG. 14;

[Explanation of symbols]

Reference Signs List 10: semiconductor substrate, 20: gate insulating film, 21: element isolation insulating film, 22, 22a: intermediate insulating film, 30: floating gate layer, 30a: floating gate, 3
1, 31a: floating layer, 31b: floating layer, 32, 32a, 33, 33a
... polysilicon layer, 34, 34a ... tungsten silicide layer, 35 ... select gate, C _BSG, C _SSG ... select gate contact hole, BSG, SSG ... select gate, WL1～16
... word line, SL ... source line, AR ... active region, STI
... Trench element isolation region, BC ... Bit contact, B
ST, SST: selection transistor, MT: memory transistor, FG: floating gate, T: trench for element isolation, DT: depletion type transistor.

Claims (12)

[Claims] 1. A semiconductor non-volatile memory device comprising: a memory transistor having a floating gate; and a selection transistor for selecting the memory transistor, wherein the channel is formed in a selection transistor region of a semiconductor substrate having a channel formation region. A gate insulating film formed above the formation region; a first conductive layer formed separately for each of the select transistors above the gate insulating film; and a second conductive layer formed above the first conductive layer A conductive layer; an intermediate insulating film formed on the second conductive layer; a third conductive layer formed on the intermediate insulating film; and a semiconductor substrate on both sides of the first conductive layer. A source / drain region formed so as to be connected to the channel formation region, wherein the second conductive layer and the third conductive layer are formed by the selection. The semiconductor nonvolatile memory device is connected in the peripheral region of the transistor region. 2. The semiconductor device according to claim 1, wherein an opening is formed in the intermediate insulating film in a peripheral region of the selection transistor region, and the opening connects the second conductive layer and the third conductive layer. Semiconductor nonvolatile memory device. 3. The plurality of select transistors are formed adjacent to each other, the second conductive layer is connected between the plurality of select transistors adjacent to each other, and the second conductive layer is connected between the plurality of select transistors adjacent to each other. 2. The semiconductor nonvolatile memory device according to claim 1, wherein three conductive layers are connected. 4. The nonvolatile semiconductor memory according to claim 1, wherein an element isolation groove is formed in said semiconductor substrate, and an element is buried in said element isolation groove to form an element isolation insulating film. apparatus. 5. The semiconductor nonvolatile memory device according to claim 4, wherein said isolation trench is formed in a self-aligned manner with respect to said first conductive layer. 6. The semiconductor nonvolatile memory device according to claim 1, wherein said second conductive layer is formed to be thinner than said first conductive layer. 7. A method for manufacturing a semiconductor non-volatile memory device having a memory transistor having a floating gate and a select transistor for selecting the memory transistor, wherein the select transistor forming region of a semiconductor substrate having a channel forming region A step of forming a gate insulating film over the channel formation region; a step of forming a first conductive layer over the gate insulating film; and forming a second conductive layer over the first conductive layer. Forming an intermediate insulating film on the second conductive layer; and forming a second insulating film on a peripheral region of the select transistor forming region.
Forming a third conductive layer on the intermediate insulating film in the select transistor formation region so as to be connected to the conductive layer; and forming the third conductive layer on both sides of the first conductive layer in the semiconductor substrate in the channel formation region. Forming a source / drain region by connecting to each other. 8. A step of forming an opening in the intermediate insulating film in a peripheral region of the select transistor forming region after the step of forming the intermediate insulating film and before the step of forming the third conductive layer. 8. The method according to claim 7, further comprising: forming the third conductive layer so that the opening connects the second conductive layer and the third conductive layer. Method. 9. A step of forming a plurality of said select transistors adjacent to each other and forming a second conductive layer, wherein said step of forming said second conductive layer includes connecting said plurality of select transistors and forming a third conductive layer. The method for manufacturing a semiconductor nonvolatile memory device according to claim 7, wherein in the forming step, the plurality of select transistors are formed so as to be connected to each other. 10. After the step of forming the first conductive layer and before the step of forming the second conductive layer, an element isolation groove is formed in the semiconductor substrate along the pattern of the first conductive layer. 8. The method for manufacturing a semiconductor nonvolatile memory device according to claim 7, further comprising: a step of forming the element isolation insulating film by filling the element isolation groove with an insulator. 11. The step of forming the element isolation insulating film includes: a step of forming an insulator over the entire surface by burying the element isolation groove; and a step of removing an insulator outside the element isolation groove. The method for manufacturing a semiconductor nonvolatile memory device according to claim 10, comprising: 12. The method according to claim 7, wherein, in the step of forming the second conductive layer, the second conductive layer is formed thinner than the first conductive layer.