JP3139275B2 - Semiconductor memory device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device comprising a floating gate type nonvolatile memory cell and a method of manufacturing the same, and more particularly to a semiconductor memory device having a source line or a drain line formed by a diffusion layer and its manufacture. Pertains to the method.

[0002]

2. Description of the Related Art FIG. 11 shows an example of a conventional semiconductor memory device.
This will be described with reference to FIG. FIG. 11 shows U.S. Pat.
No. 8,466, FIG. 11 (a) is a plan view showing the outline thereof, and FIG. 11 (b), (c),
(D) is a sectional view taken along line aa, line bb, and line cc of the plan view, respectively. In FIG. 11A, reference numeral 10 denotes a nonvolatile memory cell, reference numeral 11 denotes a control gate having a floating gate 19 directly covered with an insulating film, reference numeral 12 denotes a buried source diffusion layer, and reference numeral 13 denotes a buried type. , 14 and 15 are word lines, 16 is a source line made of the same diffusion layer as the source diffusion layer, and 17 is a wiring layer (drain line or bit line) made of the same diffusion layer as the drain diffusion layer.

FIG. 11B shows a nonvolatile memory cell 10.
5 is a cross-sectional view taken along the source / drain of FIG. 5, in which a thin field oxide film 18 is formed on the source diffusion layer 12 and the drain diffusion layer 13, and 19 is a floating gate covered with the oxide film. FIG. 11C is a sectional view of a region adjacent to the nonvolatile memory cell 10, and a thin field oxide film 18 is formed on the source line 16 and the bit line 17. FIG. 11D is a cross-sectional view crossing the floating gate 19 and the control gates 14 and 15. The thin field oxide film 18 is formed on the source diffusion layer 12 and the drain diffusion layer 13. As is clear from the above, the structure does not entirely cover the periphery of the channel region. In the case where the control gates 14 and 15 in FIG. 11D have a laminated structure including a polysilicon layer, at least a part of their side surfaces is generally insulated by an oxide film like the floating gate 19. However, it is not shown here.

As another conventional example, a semiconductor memory device shown in FIG. 12 will be described. FIG. 12A is a plan view for explaining the outline thereof, and FIGS. 12B, 12C, and 12D are taken along lines aa, bb, and cc of the plan view, respectively. FIG. In FIG. 12A, 10 is a memory cell, 1
9 is a floating gate, 14 and 15 are control gates, and a source diffusion layer and a drain diffusion layer are shown in FIG.
As shown in FIG. 2B, it is embedded in a thin field oxide film 18. In order to increase the gate coupling ratio, the floating gate 19 is formed so as to cover the field oxide film 18, the area thereof is set wide, and the source diffusion layer 12 is formed with a low-concentration diffusion layer to form an asymmetric memory cell. Are formed. FIG. 12C shows the memory cell 1
A cross-sectional view of a portion adjacent to 0 is shown. Reference numerals 16 and 17 denote a source line and a drain line (bit line) formed of the same diffusion layers as the source and drain diffusion layers 12 and 13. FIG.
(D) is a cross-sectional view orthogonal to the source / drain direction, and no field oxide film is formed between channel regions of adjacent memory cells 10.

[0005]

The conventional semiconductor memory device has the above-described structure, and the band-to-band tunnel in the memory cell is reduced by reducing the thickness of the gate oxide film corresponding to miniaturization. The current tends to increase.
As described above, the source and drain diffusion layers and the diffusion layers for the source lines or bit lines are diffusion layers formed in the same manufacturing process and have the same impurity concentration. As a result, when the impurity concentration of the source and drain diffusion layers is reduced to suppress the band-to-band tunnel current, the resistance of the diffusion layers forming the entire source lines and bit lines increases, which affects the read speed. Therefore, there is a limit to keeping the impurity concentration of the diffusion layer of the source line or the bit line low. Also, the diffusion layer of low impurity concentration of n-type on one side as in the conventional example of FIG. 12 ^- to form a (n form diffusion layer), the source-drain and the cell transistors of the asymmetric structure, inter-band band tunneling current However, with the miniaturization of the memory cell, there is a possibility that the n ⁻ -type diffusion layer is diffused in the lateral direction and a short channel of the cell transistor is generated. Furthermore, the gate oxide n ⁺ -type diffusion layer to the layer and n ^- increased overlap by direction diffusion in the form of a diffusion layer, results in results in a reduction of the gate coupling ratio, n for miniaturization of the memory cell ^- type diffusion It is not always preferred to form the layers laterally.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and suppresses the band-to-band tunnel current of a nonvolatile memory cell and reduces the resistance value of a source line or a drain line by a diffusion layer to increase the speed. It is an object of the present invention to provide a semiconductor memory device capable of performing the following. Further, the present invention suppresses the band-to-band tunnel current of the nonvolatile memory cell, suppresses the increase in the resistance of the source line and the drain line, and also prevents the short channel phenomenon of the memory cell by the self-alignment manufacturing process. It is an object of the present invention to provide a method for manufacturing a semiconductor memory device that can be used.

[0007]

In order to achieve the above object, a first semiconductor memory device of the present invention is a semiconductor memory device in which a plurality of nonvolatile memory cells are arranged, and the nonvolatile memory cells adjacent to each other are arranged. A region that insulates between the channel regions of the cell, and a diffusion layer that electrically connects between the source region and the drain region of the adjacent nonvolatile memory cell, wherein the impurity concentration of the diffusion layer is the source region and The impurity concentration is higher than the impurity concentration of the drain region. In the first semiconductor memory device, an insulating layer is provided between the adjacent diffusion layers.

Further, according to a first method of manufacturing a semiconductor memory device of the present invention, a step of forming first insulating regions spaced apart from each other on a surface of a semiconductor substrate, and a step of forming a gate between the first insulating regions. A step of forming an insulating film, and a step of forming a laminated region, which intersects the first insulating region and is separated from the gate insulating film and is formed by sequentially depositing a first conductive film and an insulating film. Forming an impurity, introducing impurities between the stacked regions to form first and second diffusion layers serving as a source region and a drain region, and forming a second diffusion layer on the first and second diffusion layers. Forming an insulating region, and forming a second conductive film extending in the first and second diffusion layer directions so as to intersect with the stacked region where the second conductive film is formed and to be separated from each other. The step and before the adjacent first diffusion layer and the adjacent second diffusion layer. Forming a diffusion window by removing the first insulating region; and implanting an impurity into the semiconductor substrate from the diffusion window to form a third window having a higher impurity concentration than the first or second diffusion layer. Forming a diffusion layer, and electrically connecting the first diffusion layer and the second diffusion layer, respectively. The first method for manufacturing a semiconductor memory device is characterized in that the first insulating region is formed of an oxide film of a relatively thick LTO film. In the first method for manufacturing a semiconductor memory device, the step of forming the diffusion window is performed by self-aligning the diffusion window at a position defined by the insulating film in the stacked region and the second insulating region. It is characterized by the following.

Further, according to a second method of manufacturing a semiconductor memory device of the present invention, there is provided a step of forming first insulating regions spaced apart from each other on a surface of a semiconductor substrate; Forming a second insulating region to be spaced apart from the semiconductor substrate; and forming a gate insulating film in a surface region of the semiconductor substrate defined by the first insulating region and the second insulating region. Forming a stacked region that intersects the second insulating region and is spaced apart on the gate insulating film and is formed by sequentially depositing a first conductive film and an insulating film;
Using the first and second insulating regions and the stacked region as a mask, introducing an impurity to form first and second diffusion layers serving as a source region and a drain region;
Forming a third insulating region on the second diffusion layer, and a second conductive film extending in the direction of the first and second diffusion layers intersecting the stacked region and separated from each other Forming a diffusion window by removing the second insulating region between the adjacent first diffusion layer and second diffusion layer; and forming an impurity from the diffusion window to the semiconductor substrate. To form a third diffusion layer having a higher impurity concentration than the first or second diffusion layer, and to electrically connect the first diffusion layer and the second diffusion layer, respectively. And having the following. Further, in the method of manufacturing the second semiconductor memory device, the step of forming the diffusion window may be performed in a self-aligned manner at a position defined by the first and third insulating regions and the insulating film in the stacked region. It is a step of forming.

According to a third method of manufacturing a semiconductor memory device of the present invention, a source diffusion layer and a drain diffusion layer of a nonvolatile memory cell are formed, and a thin insulating film is formed on the surface thereof. A first conductive layer, which is orthogonal to the direction in which the source diffusion layer and the drain diffusion layer are formed and serves as a floating gate covering the gate insulating film of the nonvolatile memory cell, is disposed and covered by the first insulating layer. A second conductive layer serving as a control gate orthogonal to the conductive layer is disposed, and the portion of the insulating film that is not covered with the first and second conductive layers is removed in a self-aligned manner and is adjacent to the second conductive layer. The method is characterized by including a manufacturing process of forming a diffusion window for connecting a source diffusion layer and a drain diffusion layer of the nonvolatile memory cell with the respective diffusion layers.

[0011]

In the semiconductor memory device of the present invention, a plurality of nonvolatile memory cells of a floating gate type are arranged, and the impurity concentration of the source diffusion layer and the drain diffusion layer of the nonvolatile memory cell depend on the impurity concentration of the source diffusion layer and the drain diffusion layer. By setting the impurity concentration of the diffusion layer between the diffusion layers to be high and suppressing the impurity concentration of the source diffusion layer and the drain diffusion layer to be low, the band-to-band tunnel current is suppressed and the impurity concentration is set to be high. Depending on the layer, the resistance value of the source line and the drain line (bit line) is reduced to achieve high speed, and furthermore, the power consumption is reduced by suppressing the tunnel current. Further, in the manufacturing method, after a source diffusion layer and a drain diffusion layer of a nonvolatile memory cell are formed in a self-aligned manner, an insulating region such as a thin field oxide film or a thick polysilicon layer is removed in a self-aligned manner in advance. The diffusion layers between the source diffusion layer and the drain diffusion layer are formed by the ion implantation method, so that the respective impurity concentrations are set to be optimum.

Next, the operation will be described in detail corresponding to each claim. In the semiconductor memory device according to the present invention, the diffusion layers between the source diffusion layer and the drain diffusion layer have low resistance, the source line and the drain line (bit line) have low resistance values, and high speed and low power consumption are achieved. LOCOS (Local Oxidation of Silicon)
A floating gate is disposed between the (insulating regions), an end of the floating gate is formed so as to ride on the LOCOS region, and a bird's beak (bir) in the LOCOS region is formed.
d's beak) to reduce the area of the channel region,
This contributes to a high coupling ratio and flattening. Further, the periphery of the channel portion is insulated by an insulating film typified by the LOCOS region, and the floating gate end portion is placed thereon, so that the parasitic capacitance is reduced as a whole. For this reason, it is possible to suppress a delay in the operation speed due to the parasitic capacitance. In the semiconductor memory device according to the second aspect, by forming the insulator layer around the channel region, the parasitic capacitance generated between the control gate and the semiconductor substrate is reduced, thereby contributing to higher speed.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device, wherein the semiconductor memory device is manufactured by forming a lattice pattern using a thin field oxide film and a polysilicon layer. After a source diffusion layer and a drain diffusion layer having a relatively low impurity concentration are formed by ion implantation into the gate oxide film exposed from the pattern, the insulating film of the previously formed thin field oxide film is removed to remove the relatively high impurity concentration. By forming a low-resistance diffusion layer having an impurity concentration, the source region and the drain region are electrically connected to each other, and the impurity concentration of the diffusion layer can be easily adjusted. A relatively low impurity concentration can be used to reduce the band-to-band tunnel current. Further, since the diffusion layers between the source diffusion layer and the drain diffusion layer have a relatively high impurity concentration and the resistance of the source line and the bit line can be reduced, low current consumption and high speed can be realized. Also, peripheral circuits (sense amplifier,
Even if high-concentration doping is applied to a logic circuit, a decoder circuit, and the like, the influence on the characteristics of the transistor is small, so that these diffusion layers can be formed in the same manufacturing process. Also, by making the source diffusion layer and the drain diffusion layer lightly doped,
Even if the memory cell is miniaturized, a channel short does not easily occur during activation by thermal diffusion.

According to the fourth aspect, the LTO which is the insulating layer
By forming an oxide film such as a film relatively high, when a floating gate is formed between the oxide films, it can be formed along the side surface of the oxide film, so that the gate coupling ratio can be increased. Can be. In addition, the oxide film is etched in a combination of anisotropic and isotropic etching to be tapered, that is, by narrowing the tip from the substrate side, thereby increasing the step coverage of the conductive layer serving as the floating gate. And the gate coupling ratio can be increased.

According to a fifth aspect of the present invention, a diffusion window region is defined in a self-aligned manner by a preformed insulating film. According to a sixth aspect of the present invention, there is provided a semiconductor memory device manufacturing method comprising:
Using a lattice pattern formed by a thick field oxide film, a thin field oxide film and a polysilicon layer formed by the OCOS process as a mask, ions are implanted into an exposed gate oxide film (thermal oxide film) to form a source diffusion layer and a drain diffusion layer. Is formed by a self-alignment method, and a diffusion layer between a source diffusion layer and a drain diffusion layer is formed in a thin field oxide film. The diffusion layer between the source diffusion layer and the drain diffusion layer and the source diffusion layer and the drain diffusion layer are separated. Since it can be formed in the manufacturing process of
The optimum impurity concentration can be obtained. Further, the diffusion window can be formed in a self-aligned manner. In addition, L which is a thin insulating film
A floating gate is arranged between the OCOS regions (field oxide films), and the end of the floating gate rides on the LOCOS region, and a bird's beak (bird's beak) is formed.
Beak) reduces the area of the channel region, increases the coupling ratio, and contributes to flattening. Furthermore, since the periphery of the channel is insulated by an insulating film typified by LOCOS and the gate end is placed thereon, the parasitic capacitance is reduced as a whole, and the operation speed is delayed due to the parasitic capacitance. Can be suppressed. According to a method of manufacturing a semiconductor memory device according to claim 8, a diffusion window is formed in a self-aligned manner using a conductive layer serving as a floating gate and a conductive layer serving as a control gate covered with an insulating layer as masks. The manufacturing process can be simplified.

[0016]

【Example】

(Embodiment 1) An embodiment of a semiconductor memory device according to the present invention will be described below with reference to FIG. FIG. 1 (a)
FIG. 1B is a plan view showing a schematic arrangement thereof, and FIGS.
(C) and (d) are aa line, bb line, and cc of the plan view.
It is sectional drawing along the line. In FIG. 1A, T is a nonvolatile memory cell, which is arranged in a matrix on the main surface of a semiconductor substrate. A region surrounded by a dotted line is a floating gate (floating gate) FG, and an n ⁻ -type source diffusion layer S in which an impurity element is diffused at a low concentration on both sides thereof.
And a drain diffusion layer D are formed. Between the source diffusion layer S and the drain diffusion layer D of each nonvolatile memory cell, an n ^{++ type} diffusion layer 3 in which an impurity element is diffused at a high concentration.
Are formed and electrically connected to form a source line or a drain line (bit line). WL is a word line, and a region indicated by a dot is LOCOS (Local Oxidation).
The insulating film rows 2 formed of a thin field oxide film formed by the (Silicon) process are arranged in parallel and separated from each other. The area defined by the dotted line is the floating gate FG. The floating gate FG is a polysilicon layer provided with conductivity.

Further, the structure will be described with reference to FIGS. 1 (b), 1 (c) and 1 (d). FIG. 1B is a cross-sectional view along the source diffusion layer S and the drain diffusion layer D of the nonvolatile memory cell T, and shows the surface of the source diffusion layer S and the drain diffusion layer D of the nonvolatile memory cell T, respectively. A thin field oxide film 5 is formed, and 4 is a gate oxide film. On the gate oxide film 4, a floating gate FG covered with an insulating film 6 is formed.
Is formed, and a word line WL having a control gate (control gate) CG immediately above is formed. FIG. 1C is a cross-sectional view of a region adjacent to the nonvolatile memory cell T. As shown in FIG. 1C, the insulating film row 2 made of a thin field oxide film formed in advance by the LOCOS process is removed in a self-aligned manner, and An n ⁺⁺ -type diffusion layer 3 having an impurity concentration higher than that of the S and drain diffusion layers D is formed. The diffusion layer 3 connects the source diffusion layer and the drain diffusion layer of the adjacent nonvolatile memory cell to form a source. A line and a drain line (bit line) are formed. At the same time as the formation of the diffusion layer 3, a thermal oxide film is formed on the surface. FIG. 1D shows a source diffusion layer S and a drain diffusion layer D.
FIG. 3 is a cross-sectional view in a direction orthogonal to FIG. 3, in which a control gate CG is formed on a floating gate FG covered with an insulating film 6 and extends in the direction of the source diffusion layer and the drain diffusion layer. The control gate CG can be patterned by the mask used for the floating gate FG. The side surface of the control gate CG is covered with an insulating film typified by an oxide film formed by thermal oxidation (not shown), like the side surface of the floating gate FG.

As is apparent from FIGS. 1A to 1D, the nonvolatile memory cell T has a buried source diffusion layer S
And a drain diffusion layer D, and the periphery of the channel region is covered with an insulating film row 2 made of a field oxide film and a field oxide film formed on the source diffusion layer S and the drain diffusion layer D. I have. Also, the source diffusion layer S
And the drain diffusion layer D, and the diffusion layer 3 between the source diffusion layer and the drain diffusion layer are formed in different diffusion steps, and it is easy to make the impurity concentrations different from each other. By making the concentration low, the band-to-band tunnel current can be suppressed, and by making the impurity concentration of the diffusion layer between the source diffusion layer S and the drain diffusion layer D high,
The wiring layer of the source line or the drain line (bit line) has low resistance, and high-speed performance can be maintained. The end of the floating gate FG is formed so as to ride on the insulating film row 2 so as to enlarge the area of the floating gate FG, while the channel region is set in consideration of the bird's beak of the LOCOS region, and the area of the channel region is set. Is made as narrow as possible to increase the gate coupling ratio, which is the ratio between the capacitance between the semiconductor substrate and the floating gate FG and the capacitance between the floating gate FG and the control gate.

Next, the manufacturing method will be described with reference to FIG.
This will be described with reference to FIGS. The insulating film sequence 2 shown in FIG. 1A is formed of a field oxide film by a LOCOS process and is positioned parallel to and separated from the surface of the semiconductor substrate 1, and a gate oxide film between the insulating film sequences 2 by heat treatment. 4 are formed. Subsequently, after depositing a polysilicon layer by a CVD method over the entire surface of the semiconductor substrate 1 on which the gate oxide film 4 is formed, conductivity is imparted by an ion implantation method or the like, and an insulating film such as a nitride film is formed on the conductive film. Membrane C
A stacked film is formed by deposition using a VD method or the like. Of course,
The insulating film may be an oxide film formed by heat treatment. The laminated film is etched and patterned so as to be orthogonal to the insulating film row 2 and parallel to each other. This laminated film is finally etched in a self-aligned manner to become a floating gate FG. Impurities are ion-implanted into the semiconductor substrate 1 by means of a lattice-shaped mask of the insulating film row 2 and the laminated film in the gate oxide film portion exposed in the above-described patterning step, and n ⁻ -type source diffusion layers S and drain diffusion layers are formed. D is formed. Subsequently, the source diffusion layers S
A field oxide film (insulating film) 5 is formed on the surface of the drain diffusion layer D by a speed-up oxidation method utilizing an impurity concentration difference or the like. Note that an insulating film 6 of a stacked film such as an ONO film or a nitride film (lower layer) and an oxide film (upper layer) is formed on the surface of the floating gate FG. Subsequently, a conductive film serving as a control gate is deposited on the entire surface, is present on the channel region, extends in the direction of the source diffusion layer and the drain diffusion layer, and is orthogonal to the stacked film for forming the floating gate FG. Then, the conductive films parallel to each other are patterned. The conductive film forms the word line WL as being the control gate CG.

Next, as shown in FIG. 1C, the laminated film forming the floating gate FG and the conductive film serving as the control gate CG form a lattice, and are formed between the buried type source diffusion layer S and the drain. The insulating windows 2 exposed between the diffusion layers D are removed in a self-aligned manner to form diffusion windows 2a. Of course, an etching process may be performed by forming an insulating film such as a nitride film on the stacked film FG or by forming a resist film. Impurities are doped at a high concentration from the diffusion window 2a by ion implantation to form the n ⁺⁺ -type diffusion layer 3 in a self-aligned manner. An insulating film is formed on the surface of the diffusion layer 3 by thermal oxidation. Subsequently, the stacked film is subjected to self-alignment switching using the conductive film serving as the control gate CG as a mask to form a floating gate. By such a manufacturing process, the source diffusion layer S and the drain diffusion layer D are formed, and the diffusion layers 3 are formed between the source diffusion layers S and the drain diffusion layers D of the nonvolatile memory cells, and the adjacent nonvolatile memory cells are formed. Between the source diffusion layer S and the drain diffusion layer D, a source line and a drain line (bit line) are formed, and a floating gate FG is formed. Subsequently, a semiconductor memory device is formed through a reflow process and a passivation process by a known method.

As is apparent from the above manufacturing process, an insulating film (LOCOS region) made of a thin field oxide film is formed in advance in a portion where the diffusion layer 3 is formed. The insulating layer is removed in a self-aligned manner without using a mask, and the diffusion layer 3 is formed by the self-alignment. After the LOCOS region is formed, a gate oxide film and a conductive layer serving as a floating gate are formed. The floating gate is formed so that an end of the floating gate rides on the LOCOS region. And the width are set, and the area of the channel region is reduced to increase the gate coupling ratio.

(Embodiment 2) Next, another embodiment of a method of manufacturing a semiconductor memory device according to the present invention will be described with reference to FIGS.
This will be described with reference to FIG. First, an equivalent circuit of a semiconductor memory device will be described with reference to FIG. 2A. Non-volatile memory cells T _{11 to} T ₁₃ and T _{21 to} T ₂₃ each having a control gate CG, a floating gate FG, and a source / drain electrode are described. They are arranged in a matrix. Word lines WL1 _, WL2 _, WL
₃ are connected to the control gate electrodes CG of the nonvolatile memory cells T ₁₁ , T ₁₂ , T ₁₃ , respectively, and the source or drain electrodes of the nonvolatile memory cells T ₁₁ , T ₂₁ ...
Nonvolatile memory cell _{(T 11, T 12, T} 13 ...), (T 21,
T _22, T ₂₃ ...) source or drain electrode of which is commonly connected to each column. 2 (b) is a plan view showing an outline of the semiconductor memory device, a-a line across the non-volatile memory cell T _11, T ₁₂ ... channel regions of, b-b line source line or Along the drain line (bit line).

Hereinafter, a manufacturing process of the semiconductor memory device according to the present invention will be described with reference to FIGS. FIG.
2A to 2E are cross-sectional views taken along the line aa in FIG. 2B, and show the manufacturing steps. In FIG. 3A, the semiconductor substrate 20 is exposed to an oxygen atmosphere at about 900.degree. C., and a pad oxide film 22 of about 300.degree. Thereafter, SiH is deposited on the entire surface of the pad oxide film 22 at a temperature of about 300 ° C. by low pressure vapor deposition (LPCVD).
₄ (monosilane) / 0 ₂ mixed gas is reacted LTO (Low Temperature Oxide) film 23 (oxygen) about 450
Deposit to a thickness of 0 °. Next, as shown in FIG. 3 (b), a resist film is applied to form a thick oxide film row of the LTO film, and resist masks 24a and 24b are formed. The resist masks 24a and 24b are patterns parallel to each other. Subsequently, as shown in FIG. 3C, the LTO film 23 is subjected to a reactive ion etching (RIE) method by time mode etching so as not to damage the crystal surface of the semiconductor substrate 20. After selective etching, the remaining pad oxide film 22 is made of hydrofluoric acid (HF) or a mixture of hydrofluoric acid (HF) and ammonium fluoride (NH ₄ F). O.
It is removed by wet etching with E (Buffered Oxid Etchant) or the like, and LTO films 23a and 23b are formed. The LTO films 23a and 23b may be tapered by combining isotropic and anisotropic etching.
The width of the LTO films 23a and 23b on the semiconductor substrate side is increased,
The tip may have a narrowed shape.

Next, as shown in FIG. 3 (d), after removing the resist masks 24a, a 24b, of about 800 ° C. O ₂
Substrate 2 exposed between the thick oxide film rows by oxidizing the exposed surface of semiconductor substrate 20 using a mixed gas of / H ₂ / HCl.
The surface of the gate oxide film 2 having a thickness of about 90 ° is exposed to an N ₂ / O ₂ mixed gas having a temperature of about 900 ° C.
5 are formed. Thereafter, as shown in FIG.
Polysilicon layer 26 is deposited by PCVD at about 630 ° C. to a thickness of about 1500 °. P (phosphorus) dopant is ion-implanted (acceleration energy: 30 KeV, dose: 7E14 atoms / cm ² ) to form a polysilicon layer 2.
6 is given conductivity. Subsequently, about 80% by LPCVD.
At 0 ° C, an HTO (High Temperature Oxide) film
堆積 is deposited at about 900 ° C. in an atmosphere of a mixed gas of N ₂ / O ₂ , and finally an oxide film is formed on the polysilicon layer to a thickness of about 60 °. Next, LPC
SiH ₂ Cl ₂ / NH at a temperature of 750 ° C. by VD method
_A silicon nitride (SiN) film is deposited at about 80 ° in a mixed gas of ₃ and an HTO film is deposited again at about 80 ° to form an ONO film 27 having a laminated structure.

Subsequently, a resist film 28 is formed.
The pattern of the strike film 28 corresponds to the LTO films 23a and 23b.
And orthogonal to each other. Using this mask
The ONO film 27 and the underlying polysilicon layer 26 are etched.
And the oxide film rows 23a and 23b formed by the LTO film.
The orthogonal ONO film 27 and the underlying polysilicon layer 26
Is formed as shown in FIG.
You. Subsequently, the LTO films 23a and 23b and the ONO film 27
Area A that is masked and exposed₁(Areas indicated by dots)
Thermal oxide film that is continuous with the metal oxide film, ₁To
Arsenic (As) ion implantation (acceleration energy: 50 Ke
V, dose amount: 5E14 atoms / cm^Two) Low impure
A source diffusion layer and a drain diffusion layer with
H at a temperature of about 900 ° C_Two/ O_Two/ HCl mixed gas
Oxidation in the source diffusion layer and drain diffusion layer
A thin field oxide film (insulating film) of 1200 mm is formed.
It is.

Next, the manufacturing process will be described with reference to FIG. FIG. 4A is a sectional view taken along line aa of FIG. 2B, and FIG. 4B is a sectional view taken along line bb of FIG. 2B. As shown in FIGS. 4A and 4B, L
After depositing a polysilicon layer to a thickness of about 2000 ° at a temperature of about 630 ° C. by PCD, a diffusion source such as PCl ₃ is doped at about 875 ° C. to impart conductivity to the polysilicon layer. After removing the oxide film formed at the time of diffusion on the polysilicon layer, WF ₆ is formed by a CVD method or the like.
/ SiH ₂ Cl ₂ mixed gas at a temperature of about 470 ° C. to form a tungsten silicide layer (W _x Si _Z, WSi _Z ) of about 1
Deposit to a thickness of 500 °. A poly / WSi layer 29 in which a polysilicon layer and a tungsten silicide layer are stacked is formed. The poly / WSi layer 29 finally becomes a control gate electrode. Reference numeral 32 denotes an n ⁺⁺ -type source diffusion layer (or a drain diffusion layer) formed in the previous manufacturing process.

Next, the manufacturing process will be described with reference to FIG. FIG. 5A is a sectional view taken along the line aa of FIG. 2B, and FIG. 4B is a sectional view taken along the line bb of FIG. 2B. As shown in FIG. 5 (a), poly / WS
In order to form a control gate composed of the i-layer 29, a resist mask layer 31 having a diffusion window 31a is formed. The subsequent manufacturing process will be described with reference to FIG.
FIG. 6A is a cross-sectional view taken along line aa of FIG. 2B, and FIG. 6B is a cross-sectional view taken along line bb of FIG. 2B. As shown in FIG. 6A, the poly / WSi 29 exposed in the diffusion window 31a and the ONO film 27 thereunder are removed by the RIE method to expose the LTO films 23a and 23b, and the control gate 29a by the poly / WSi 29 And a floating gate 26a therebelow is defined, and as shown in FIG. 6B, the LTO films 23a and 23b where the ONO film 27 is not formed are removed, and the diffusion window 3 is formed.
1a is formed. The control gate 29a made of the poly / WSi layer 29 and the floating gate 26a immediately below the control gate 29a are shown in FIG.
As can be seen from (a), both ends extend on the LTO films 23a and 23b, which are thick oxide films, and are formed so as to run parallel to the LTO films 23a and 23b.

This etching step is performed by the RIE method, and the tungsten silicide layer (poly / WSi layer 2
9) using a mixed gas of SF ₆ / HBr, the polysilicon layers (LTO films 23a and 23b) using a mixed gas of Cl ₂ / HBr, and the ONO film 27 is sequentially removed using a C ₂ F ₆ gas. . By appropriately selecting the etching time of the ONO film 27, the thick LTO films 23a and 23b between the source diffusion layer (or the drain diffusion layer) and where the floating gate is not formed are removed. In the etching step using the diffusion window 31a, the selectivity between the oxide film (LTO film) and the polysilicon layer is 20: 1, and the thick oxide film (LTO films 23a, 23b) is formed in the ONO film 27 etching step. 4
The polysilicon layer 26 of the floating gate 26
Is less than 200 °, so there is almost no damage to the gate oxide film.

FIG. 7 is a sectional view taken along the line bb of FIG. 2B. As shown in FIG. 7, the resist mask layer 31 and the remaining thick LTO films 23a and 23b are removed. Using arsenic (As) as a mask as a dopant, ion implantation (conditions: acceleration energy: 80 KeV, dose: 5E)
15 atoms / cm ² ) to form an n ⁺⁺ -type diffusion layer 33. The source or drain diffusion layer 32 is a diffusion layer 3
3 to form a source line or a drain line (bit line). After that, passivation is performed through a process such as a planarization process to form a semiconductor memory device. Further, a step of completely insulating the floating gate by thermal oxidation is required, but not shown. This processing step may be performed before the step of implanting ions through the diffusion window or may also be performed as an annealing step.

[0030] In the embodiment shown this way in FIGS. 2 to 7, n ^- the form of the source-drain diffusion layer 32 is an oxide film column a conductive layer made of silicide layers such as the control gate or word line LTO Is formed in a self-aligned manner using the film as a mask, the exposed conductive layer and the ONO underlying the conductive layer.
In removing the film, the LTO film in the region where the ONO film is not formed is also removed by adjusting the enchuring time to expose the oxide film. An n ^{++ type} diffusion layer 33 is formed by ion implantation in the region where the oxide film is exposed, and the source or drain diffusion layer 32 is electrically connected to form a source line or a drain line (bit line). .

(Embodiment 3) Next, another embodiment of a method of manufacturing a semiconductor memory device according to the present invention will be described with reference to FIGS.
Description will be made based on 0. 8 (a), 8 (b),
FIG. 8C is a plan view showing the order of the manufacturing process, and FIG.
FIG. 9 is a sectional view taken along line aa, line bb, and line cc of FIG.
(A), (b) and (c) shown in FIG.
FIG. 10 is a sectional view taken along line bb, and line cc.
(A), (b), and (c). The embodiment of FIG. 8 shows a method of manufacturing a semiconductor memory device having an equivalent circuit different from that of the embodiment of FIG. That is, a thick field oxide film as an element isolation region is formed on both sides of the memory cell. First, a description will be given with reference to FIG. By the LOCOS process, a thick field oxide film 44 of about 7000.degree. After that, LOCOS
By the process, a thin field oxide film 45 is arranged at a position parallel to and separated from the field oxide film 44 so as to be orthogonal to the field oxide film 44. The thickness of the thin field oxide film 45 is about 1200 °.

Subsequently, a gate oxide film 41 is formed on the surface of the semiconductor substrate in a region surrounded by the thick field oxide film 44 and the thin field oxide film 45 by a known method. Thereafter, a polysilicon layer is deposited on the entire surface by a CVD method, and conductivity is imparted to the polysilicon layer through an ion implantation process. On the surface, an insulating film [ONO film or nitride film (lower layer) and oxide film (upper layer)] are formed. And a laminated film with the above) are formed. Next, a description will be given with reference to FIGS. 8B and 9A, 9B, and 9C. In the polysilicon layer provided with conductivity covered with an insulating film such as an ONO film or the like, a polysilicon layer 46 arranged in parallel with each other between the field oxide films 44 is formed through a patterning process. The surface of the polysilicon layer 46 is covered with an insulating film 43 such as an ONO film. Subsequently, using the insulating film on the polysilicon layer 46 and the field oxide film 44 as a mask, a source diffusion layer 47s and a drain diffusion layer 47 having a low impurity concentration (n ⁻ ) are formed through ion implantation.
d is formed, and a thin field oxide film (insulating film) 48 is formed on its surface. 46g is a floating gate,
In this step, an oxide film is formed on the side surface.

Subsequently, a polysilicon layer was deposited on the entire surface.
Later, conductivity is imparted by ion implantation and this policy
By patterning the recon layer, word lines and
A polysilicon layer 49 serving as a control gate is formed. Po
The silicon layer 49 is a floating gate electrode portion covered with an insulating film.
46g and parallel to the thin field oxide 45.
And are spaced apart from each other. Subsequently, FIG.
(C) and description with reference to FIGS. 10 (a), (b) and (c)
I do. Polysilicon layer 49 and thick field oxide film 44
And a polysilicon layer 46 covered with an insulating film 43 are formed in a lattice shape.
Are located. Thin areas not covered by this grid-like area
Field oxide film 45 is removed in a self-aligned
Window 45a is formed, and this lattice-like region is used as a mask.
The impurity is ion-implanted at a high concentration through the diffusion window 45a.
Through an annealing process⁺⁺Shaped diffusion layer 47c is formed.
It is. By such an ion implantation process, the source diffusion
The high impurity concentration (n ⁺⁺) Expansion
A diffusion layer is formed, and the source diffusion layer and the drain diffusion layer are formed.
Are electrically connected to each other. Furthermore, the image of the floating gate 46g
Is self-aligned using the polysilicon layer 49 as a mask.
Done. Of course, the polysilicon layer 49 serving as a word line
It may be defined in a patterning step. Also, polysilicon
The layer 49 has a thickness of 1000 to 1000 in consideration of a decrease in the manufacturing process.
Desirably, it is 1200 mm thick. Further flattening
Apply processing, apply an interlayer insulating layer, etc.
It is completed through a process.

Incidentally, these field oxide films are LOC
The field oxide film is formed by an OS process. The thickness of the field oxide film 44 may be such that the thick field oxide film 44 does not turn on the parasitic transistor, and the thin field oxide film 45 is formed by an etching process for cutting out the control gate. Thin enough to easily form a diffusion window, and
It is desirable that the thickness be large enough not to be exposed to the semiconductor substrate. Although it depends on the energy at the time of ion implantation, the lower limit of the thickness of the generally thin field oxide film 45 is set to such a thickness that the semiconductor substrate is not partially exposed, that is, 1000 .ANG. It is necessary to be above. The upper limit value of the thin field oxide film 45 must be set within a range where the element isolation function of the thick field oxide film 44 does not deteriorate. From this viewpoint, the thickness may be 4500 ° or less. Since the etching process described above causes a large damage, the value is desirably about 1200 °. That is, the thickness of the thin field oxide film 45 is 1000 to 12
It is desirable to be in the range of 00 °.

The structure will be further clarified based on FIGS. 10 (a), 10 (b) and 10 (c). FIG. 10A is a cross-sectional view in the direction of the source diffusion layer 47s and the drain diffusion layer 47d.
d is covered with an insulating film 48 of a field oxide film, and a buried source diffusion layer 47s and a drain diffusion layer 47d are formed. The surface of the polysilicon layer (gate electrode) 46g provided with conductivity is covered with an insulating film (ONO film, oxide film, nitride film, or the like) 43, and its side surface is also covered with the insulating film. It is formed on the floating gate 46g covered by 43 and extends in the direction of the source diffusion layer 47s and the drain diffusion layer 47d. The edge of the floating gate 46g extends on the field oxide film 48. FIG.
(B) is a cross-sectional view taken along a diffusion layer 47c between a source diffusion layer and a drain diffusion layer adjacent to a nonvolatile memory cell. The source diffusion layer and the drain diffusion layer are electrically connected by the diffusion layer 47c. A source line or a drain line (bit line) is formed. FIG. 10C is a cross-sectional view in a direction orthogonal to the source / drain direction, and the floating gate 46g is formed using the control gate 49 as a mask.
Is defined. The edge of the control gate 49 is formed so as to ride on the field oxide film 45, the channel region is made as narrow as possible, and the edge of the floating gate 46g extends on these field oxide films 45.

As is apparent from these sectional views, the periphery of the channel region of the nonvolatile memory cell is surrounded on all sides by field oxide films 45 and 48, and the bird's beak of field oxide films 45 and 48 minimizes the channel region. The floating gate 46g is set to have a limited area, and the edge of the floating gate 46g is placed on these field oxide films to enlarge the area. Furthermore, by setting the impurity concentration of the diffusion layer 47c forming the source line or the drain line (bit line) higher than the impurity concentration of the source diffusion layer 47s and the drain diffusion layer 47d, the band-to-band tunnel current is suppressed. The resistance value of the source line or the drain line (bit line) can be reduced by increasing the impurity concentration of the diffusion layer between the source diffusion layers (or the drain diffusion layers).

In the first to third embodiments, the ion implantation for forming the source diffusion layer and the drain diffusion layer is performed at a dose of 1 × 10 ¹⁴ to 1 × 10 ¹⁵ atoms / cm 2.
And the ^second range, ion implantation when forming the diffusion layer of the source diffusion layer and drain diffusion layers, a dose of 5
It is set within the range of × 10 ^{14 to} 7 × 10 ¹⁵ atoms / cm ² . Of course, the impurity concentration of the diffusion layer between the source diffusion layer and the drain diffusion layer is set higher than the impurity concentration of the source diffusion layer and the drain diffusion layer. Further, in the first to third embodiments, arsenic can be selected as an impurity of the source diffusion layer and the drain diffusion layer and the diffusion layer between the source diffusion layer and the drain diffusion layer. The leakage current based on the band-to-band tunneling current between the two can be suppressed.

Further, it goes without saying that the present invention can be applied to not only cells of a virtual ground (virtual ground) type having a common source as in the above-described embodiment but also cells of other types. Further, it is needless to say that the structure of the nonvolatile memory cell can be made to be an LDD structure by applying a sidewall or a spacer oxide film in the manufacturing process of the present invention. Further, if a step of depositing a thin silicon nitride film (SiN) after depositing a pad oxide film is used, LT
The end point determination of the O film etching and the end point determination of the diffusion window etching are facilitated, and the control of the manufacturing process is facilitated.
In the claims, such additional manufacturing steps are omitted. However, even if such a well-known technique is added, it does not depart from the scope of the present invention.

Furthermore, the manufacturing conditions described in the examples are merely examples, and the present invention is not limited to these.
It is obvious that the arrangement of the insulating film and the like takes slightly different forms depending on the equivalent circuit of the semiconductor memory device. Furthermore,
In the method for manufacturing a semiconductor memory device according to the present invention, a source / drain diffusion layer is formed by a first impurity diffusion step, and a diffusion layer connecting the source diffusion layer and the drain diffusion layer is formed by a second impurity diffusion step. In the second impurity diffusion step, a region covered with a thin oxide film, an LTO film, or the like is removed in advance to form a self-alignment.
Of course, the source / drain diffusion layers are also formed by the self-alignment method.

[0040]

As described above, in the semiconductor memory device according to the present invention, the source diffusion layer and the drain diffusion layer are formed by the self-alignment method, and subsequently formed with a thin field oxide film or a polysilicon layer (LTO film) in advance. A diffusion window is formed in the covered area by using a self-alignment method or a self-alignment method and an etching ratio, and a diffusion layer is formed between a source diffusion layer and a drain diffusion layer. The impurity concentration of the layer can be set to be different from the impurity concentration of the source / drain diffusion layers. Therefore, the resistance value of the drain line (bit line) and the source line can be reduced, so that high-speed operation is possible and the impurity concentration of the source diffusion layer and the drain diffusion layer can be set to a low concentration. There is an advantage that a band-to-band tunnel current can be suppressed and a semiconductor memory device with low current consumption can be provided.
Further, in the semiconductor memory device of the present invention, since the periphery of the channel region is covered with the oxide film, the gate length and the width are set in consideration of the bird's beak of the silicon oxide film by the LOCOS process. Since the area in contact with the semiconductor substrate via the oxide film can be set small, the ratio between the capacitance between the substrate and the floating gate and the capacitance between the floating gate and the control gate, that is, the coupling ratio should be set large. There are advantages that can be. Further, in the method of manufacturing a semiconductor memory device according to the present invention, since the formation of the diffusion layer or the formation of the floating gate is performed in a self-aligned manner, and the source / drain diffusion layers can be formed with a low impurity concentration, a channel short circuit occurs. Therefore, there is an advantage that the number of masks and the manufacturing process can be made relatively simple.

[Supplementary Matters] Hereinafter, other aspects of the constituent elements including the present invention will be described. (1) In the semiconductor device of the present invention, nonvolatile memory cells are arranged in a matrix, and the periphery of a channel region of the nonvolatile memory cell is covered with an insulating film, and the drain diffusion of the adjacent nonvolatile memory cell is performed. A diffusion layer connecting the interlayer and the source diffusion layer, wherein the impurity concentration of the diffusion layer between the drain diffusion layer and the source diffusion layer is higher than the impurity concentration of the drain diffusion layer and the source diffusion layer. is there.

(2) A first method of manufacturing a semiconductor memory device based on the embodiment of FIG. 1 includes a step of forming a row of insulating films parallel to each other on a surface of a semiconductor substrate, and a step of forming a gate oxide film between the rows of insulating films. Forming a stacked film in which a first conductive film and an insulating film are sequentially deposited on the entire surface of the semiconductor substrate on which the gate oxide film is formed, and the stacked film is orthogonal to the insulating film row, A first patterning step for forming the source diffusion layer and the drain diffusion layer by implanting impurities into the gate oxide film portion exposed in the first patterning step; A step of forming a thick oxide film by accelerated oxidation in a region into which impurities have been implanted in the first diffusion step; a step of depositing a second conductive film over the entire surface; A conductive film exists on the channel region A second patterning step of extending in the direction of the source diffusion layer and the drain diffusion layer so as to be orthogonal to the stacked film, and partially removing the insulating film row exposed in the second patterning step Forming a diffusion window, and a second diffusion step of injecting impurities from the diffusion window, wherein the source diffusion layer and the drain diffusion layer formed by the first diffusion step are formed in the second diffusion step. Are connected by a diffusion layer of

(3) Second embodiment based on the embodiment shown in FIGS.
Forming a thick row of insulating films parallel to each other on a surface of a semiconductor substrate, forming a gate oxide film between the rows of insulating films, and forming the gate oxide film. Forming a laminated film in which a first conductive film and an insulating film are sequentially deposited on the entire surface of the semiconductor substrate, patterning the laminated film so as to be orthogonal to the insulating film row, and forming the gate exposed in the patterning step A first diffusion step of forming a source diffusion layer and a drain diffusion layer by injecting impurities into an oxide film portion; and forming a thick oxide film by accelerated oxidation in a region where the impurities are implanted in the first diffusion step. A step of depositing a second conductive film on the entire surface;
A second patterning step of etching the second conductive film so as to cover the thick insulating film row and to be formed on the channel region so as to extend in the direction of the source diffusion layer and the drain diffusion layer; Forming a diffusion window by removing the thin insulating film exposed in the second patterning step in a self-aligned manner; and a second diffusion step of injecting impurities from the diffusion window. The diffusion layer formed by the first diffusion step is connected by the diffusion layer formed by the second diffusion step.

(4) Third Embodiment Based on the Embodiments of FIGS. 8 and 9
Forming a thick row of insulating films arranged in parallel with each other on the surface of a semiconductor substrate, and forming thin rows of insulating films in a direction orthogonal to and parallel to each other on the thick row of insulating films. Forming a gate oxide film on the semiconductor substrate surface not covered with the insulating film row;
Forming a stacked film in which a first conductive layer and an insulating film are sequentially deposited on the entire surface, and a first patterning step of forming a stacked film row by the stacked films arranged in parallel with the thick insulating film row; Impurities are implanted into the semiconductor substrate from the gate oxide film exposed in the first patterning step to form a source
A first diffusion step of forming a drain diffusion layer;
Forming an oxide film on the surface of the diffusion layer formed in the diffusion step by accelerated oxidation, forming a second conductive layer over the entire surface, etching the second conductive film to form the thin insulating film. A second patterning step that is parallel to the film sequence and covers the oxide film on the source / drain diffusion layers, and is defined by the thick insulating film, the stacked film sequence, and the second conductive layer A step of removing the thin insulating film row, and a second diffusion step of injecting impurities into a semiconductor substrate from a region where the thin insulating film row has been removed to form a diffusion layer; Are connected by a diffusion layer formed by the second diffusion step.

(5) In the first to third methods for manufacturing a semiconductor memory device, the impurity concentration of the source diffusion layer and the drain diffusion layer is lightly doped in the first diffusion step. In the diffusion step, a diffusion layer doped with a high impurity concentration is formed between the source diffusion layer and the drain diffusion layer. (6) In the first to third methods for manufacturing a semiconductor memory device, the ion implantation condition in the first diffusion step is 1
Within the range of × 10 ¹⁴ to 1 × 10 ¹⁵ atoms / cm ² ,
The ion implantation condition in the second diffusion step is 5 × 10 ¹⁴
７7 × 10 ¹⁵ atoms / cm ² .

[Brief description of the drawings]

1A is a plan view showing an embodiment of a semiconductor memory device according to the present invention, FIG. 1B is a sectional view taken along line aa of the plan view, and FIG. 1C is bb of the plan view; Sectional view along the line, (d)
Is a cross-sectional view along the line cc in the plan view.

FIG. 2A is an equivalent circuit diagram showing another embodiment of the present invention, and FIG. 2B is a plan view showing an outline thereof.

3 (a) to 3 (f) are views showing a manufacturing process of the semiconductor memory device of the present invention, and FIGS. 3 (a) to 3 (e) are views of FIG.
FIG. 4 is a cross-sectional view taken along line −a, and FIG.

FIG. 4 shows a manufacturing process subsequent to FIG.
2B is a cross-sectional view taken along line aa and line bb in FIG. 2B, respectively.

5 shows a manufacturing process subsequent to FIG. 4, and (a) and (b) are cross-sectional views taken along lines aa and bb in FIG. 2 (b), respectively.

FIG. 6 shows a manufacturing process subsequent to FIG. 5, and (a) and (b) are cross-sectional views taken along line aa and line bb in FIG. 2 (b), respectively.

FIG. 7 shows a manufacturing process subsequent to FIG. 6, and FIG.
It is sectional drawing which followed the b line.

FIGS. 8A to 8C are plan views showing the steps of manufacturing the semiconductor memory device according to the present invention.

9 (a), 9 (b) and 9 (c) respectively show a of FIG. 8 (b).
It is sectional drawing along the -a line, the bb line, and the cc line.

FIGS. 10A, 10B, and 10C are cross-sectional views taken along lines aa, bb, and cc of FIG. 8C, respectively.

11A is a plan view illustrating an example of a conventional semiconductor memory device, FIG. 11B is a cross-sectional view taken along line aa, and FIG.
FIG. 3D is a cross-sectional view along the line b, and FIG. 4D is a cross-sectional view along the line cc.

12A is a plan view showing another example of the conventional semiconductor memory device, FIG. 12B is a cross-sectional view along line aa, FIG. 12C is a cross-sectional view along line bb, (D) is a cross-sectional view along the line cc.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Insulating film row 3 Diffusion layer 4 Gate oxide film 5 Field oxide film 6 Insulation film T Non-volatile memory cell S Source diffusion layer D Drain diffusion layer WL Word line FG Floating gate CG Control gate

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/115 H01L 21/8247 H01L 29/788 H01L 29/792

Claims (8)

(57) [Claims] In a semiconductor memory device in which a plurality of nonvolatile memory cells are arranged, a region for insulating between channel regions of adjacent nonvolatile memory cells, a source region of adjacent nonvolatile memory cells, and A diffusion layer that electrically connects the drain regions, wherein an impurity concentration of the diffusion layer is higher than an impurity concentration of the source region and the drain region. 2. The semiconductor memory device according to claim 1, further comprising an insulator layer between the adjacent diffusion layers. 3. A method of manufacturing a semiconductor memory device, comprising: forming a first insulating region which is spaced apart from a surface of a semiconductor substrate; and forming a gate insulating film between the first insulating regions. Forming a stacked region, which intersects the first insulating region and is separated from the gate insulating film and is formed by sequentially depositing a first conductive film and an insulating film. Implanting impurities between the stacked regions to form first and second diffusion layers serving as a source region and a drain region; and forming a second insulating region on the first and second diffusion layers. Forming a second conductive film extending in the direction of the first and second diffusion layers so as to intersect with the stacked region and to be separated from each other; The first insulating region between the adjacent second diffusion layers is removed and expanded. Forming a use windows, impurities are implanted from the diffusion window on the semiconductor substrate,
A third impurity having a higher impurity concentration than the first or second diffusion layer;
Forming a diffusion layer, and electrically connecting the first diffusion layer and the second diffusion layer, respectively. 4. An LTO wherein said first insulating region is relatively thick
4. The method according to claim 3, wherein the film is formed of an oxide film. 5. The step of forming the diffusion window includes the first step.
4. The method according to claim 3, wherein the semiconductor memory device is formed in a self-aligned manner at a position defined by the insulating region and the insulating film in the stacked region. 6. A method of manufacturing a semiconductor memory device, comprising: forming a first insulating region spaced apart from each other on a surface of a semiconductor substrate; and intersecting with the first insulating region and separating the first insulating region. Forming a second insulating region to be arranged by disposing; forming a gate insulating film in a surface region of a semiconductor substrate defined by the first insulating region and the second insulating region; Forming a stacked region, which intersects the insulating region and is spaced apart on the gate insulating film and is formed by sequentially depositing a first conductive film and an insulating film; Implanting impurities using the insulating region and the stacked region as masks to form first and second diffusion layers serving as source and drain regions, and forming an impurity on the first and second diffusion layers. Forming an insulating region of No. 3 and intersecting the stacked region Forming a second conductive film extending in the direction of the first and second diffusion layers and separated from each other; and forming the second conductive film between the adjacent first diffusion layer and second diffusion layer. Removing the insulating region to form a diffusion window, implanting impurities into the semiconductor substrate from the diffusion window,
A third impurity having a higher impurity concentration than the first or second diffusion layer;
Forming a diffusion layer, and electrically connecting the first diffusion layer and the second diffusion layer, respectively. 7. The method according to claim 7, wherein the step of forming the diffusion window is performed by the first step.
7. The method according to claim 6, wherein the semiconductor memory device is self-aligned to a position defined by the third insulating region and the insulating film in the stacked region. 8. A method for manufacturing a semiconductor memory device, comprising: forming a source diffusion layer and a drain diffusion layer of a nonvolatile memory cell; forming a thin insulating film on a surface thereof; A first conductive layer, which is orthogonal to the direction in which the drain diffusion layer is formed and serves as a floating gate that covers the gate insulating film of the nonvolatile memory cell, is provided, and a first conductive layer covered with an insulating layer is provided. And a second conductive layer serving as a control gate which is orthogonal to the first conductive layer is disposed.
And a part of the insulating film which is not covered with the second conductive layer is removed in a self-aligned manner, and a diffusion layer for connecting a source diffusion layer and a drain diffusion layer of an adjacent nonvolatile memory cell with a diffusion layer. A method for manufacturing a semiconductor memory device, comprising a manufacturing step of forming a window.