JP3397972B2 - Nonvolatile semiconductor memory device and method of manufacturing the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a non-volatile semiconductor memory device, and more specifically, to miniaturize the cell size of a split type flash memory and to reduce the source line resistance. Regarding technology.

[0002]

2. Description of the Related Art A conventional nonvolatile semiconductor memory device of this type will be described with reference to FIGS. FIG. 19 is a sectional view of a nonvolatile semiconductor memory device (split type flash memory).

First, reference numeral 91 shown in the figure is a semiconductor substrate of one conductivity type, for example, a P type semiconductor substrate, and a floating gate 93 is formed on the substrate 91 via a first gate oxide film 92. A control gate 95 is formed from the upper portion to the side portion via a second gate oxide film 94, and a drain diffusion layer 96 and a source diffusion layer 97 are formed on a semiconductor substrate 91 on both sides of the floating gate 93 and the control gate 95. What has been formed is proposed.

[0004]

However, as can be seen from the drawing, the split type flash memory is formed by superimposing the control gate 95 from the upper part to the side part of the floating gate 93. At the time of this superposition, the degree of overlap of the control gates 95A arranged on the floating gates 93 becomes large, and FIG.
As shown in 0, when the area of the lower surface of the control gate 95A becomes small, the generation of leak current increases due to the short channel effect, and the device characteristics change. Therefore, an extra space is required in order to allow an extra degree of overlap, which has been a factor of increasing the cell size.

There is also a problem that the resistance of the source line due to the source diffusion layer 97 is high. Therefore, an object of the present invention is to miniaturize a split type flash memory and to reduce the resistance of a source line.

[0006]

Therefore, the nonvolatile semiconductor memory device of the present invention includes a control gate formed via an oxide film in the vicinity of a side surface of a floating gate formed on a gate oxide film on a semiconductor substrate. A source diffusion layer formed adjacent to the floating gate and a drain diffusion layer formed adjacent to the control gate.

Further, according to the method of manufacturing a nonvolatile semiconductor memory device of the present invention, a conductive polysilicon film is formed on a semiconductor substrate via a gate oxide film, and the oxide film is formed so as to cover the polysilicon film. After the formation, a conductive polysilicon film is formed, and the polysilicon film is patterned through a resist film to form a first control gate. Next, the oxide film is isotropically etched using the resist film and the first control gate as a mask to leave the oxide film on the lower surface of the first control gate eroded, and the resist film is removed. The polysilicon film is anisotropically etched using the mask as a mask to pattern the polysilicon film to form a floating gate. Then, after removing the resist film, thermal oxidation is performed to form a thermal oxide film so as to cover the floating gate and the first control gate, a polysilicon film is formed on the entire surface, and impurities are implanted. Isotropic etching is performed to form a polysilicon film on the side wall portion extending over the first control gate and the floating gate, and one polysilicon film is isotropically etched and removed by using the resist film as a mask to remove one of the first A second control gate is formed on the side wall portion extending over the first control gate and the floating gate. Next, impurity ions are implanted using the resist film as a mask to form a source diffusion layer adjacent to one end of the floating gate, an insulating film is formed on the entire surface, and then anisotropic etching is performed. Of the first control gate and the second control gate are exposed, and a side wall spacer is formed on the side wall portion extending over the control gate and the floating gate and the side wall portion of the second control gate. Impurity ions are implanted as a mask to form a drain diffusion layer adjacent to the second control gate. Then, a metal film is formed on the first and second control gates by a selective CVD method to electrically connect the first and second control gates, and at the same time, the layer resistance of the source / drain diffusion layers. Is to lower.

Further, according to the method of manufacturing a nonvolatile semiconductor memory device of the present invention, a conductive polysilicon film is formed on a semiconductor substrate via a gate oxide film, and a SiO2 film and a SiO2 film are formed so as to cover the polysilicon film. After forming the SiN film, a conductive polysilicon film is formed, and the polysilicon film and the SiN film are patterned through a resist film to form a first control gate. Next, the SiO2 film is isotropically etched using the resist film, the first control gate and the SiN film as a mask to leave the SiO2 film on the lower surface of the SiN film in a corroded state. The polysilicon film is anisotropically etched using the mask as a mask to pattern the polysilicon film to form a floating gate. Then, after removing the resist film, thermal oxidation is performed to form a thermal oxide film so as to cover the floating gate and the first control gate, and a polysilicon film is formed on the entire surface, followed by anisotropic etching. A polysilicon film is formed on a side wall portion extending over the first control gate and the floating gate, and one of the polysilicon films is isotropically etched and removed by using the resist film as a mask to form one of the first control gates. A second control gate is formed on the side wall portion extending over the floating gate. Next, impurity ions are implanted using the resist film as a mask to form a source diffusion layer adjacent to one end of the floating gate, an insulating film is formed on the entire surface, and then anisotropic etching is performed. A sidewall spacer over the control gate and the floating gate, and a sidewall spacer on the sidewall of the second control gate, and the first control gate and the second control gate.
Exposing the head of the control gate, and implanting impurity ions using the resist film as a mask to form a drain diffusion layer adjacent to the second control gate.
Selective CVD on the first and second control gates
A metal film is formed by a method to electrically connect the first and second control gates, and at the same time, reduce the layer resistance of the source / drain diffusion layers.

Further, in the method for manufacturing a nonvolatile semiconductor memory device of the present invention, a metal film is formed by a selective CVD method after forming a silicide film on the first and second control gates. Further, according to the method of manufacturing a nonvolatile semiconductor memory device of the present invention, a titanium film is formed on the entire surface including the first and second control gates, and then rapid thermal annealing is performed to form titanium on the source / drain diffusion layers. After forming the silicide film and the titanium nitride film on the entire surface, AP is formed on the entire surface.
The APCVD SiO2 film is formed by the CVD method, and the AP
The APCVDSiO2 film is left through the resist film formed so as to cover the heads of at least the first control gate and the second control gate on the CVDSiO2 film, and the titanium nitride film is left through the APCVDSiO2 film. By performing the film and rapid thermal annealing, the first and second control gates are electrically connected and at the same time, the resistance of the titanium silicide film on the source / drain diffusion layers is reduced.

In the method for manufacturing a nonvolatile semiconductor memory device of the present invention, an interlayer insulating film is formed so as to cover the first and second control gates, and a contact hole is formed in the interlayer insulating film. To expose the heads of the first and second control gates and form a metal film to fill the contact holes.
And the second control gate are electrically connected.

Further, in the method for manufacturing a nonvolatile semiconductor memory device of the present invention, the contact hole is formed on the first and second control gates extending on the field oxide film.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a nonvolatile semiconductor memory device and a manufacturing method thereof according to the present invention will be described below with reference to the drawings. (1) First Embodiment Hereinafter, a non-volatile semiconductor memory device showing an embodiment of the present invention will be described with reference to FIGS. 1 and 2.

First, in the nonvolatile semiconductor memory device showing one embodiment of the present invention, the LOCOS oxide film 2 as an element isolation film is formed in a region other than the element formation region of the semiconductor substrate 1 as LO.
The gate oxide film 3 is formed by the COS (Local Oxidation Of Silicon) method and has a film thickness of about 100 Å in the element formation region. In addition, approximately 2000 Å from the gate oxide film 3 to the end of the LOCOS oxide film 2.
To form a polysilicon film of, for example, POCl3
By performing phosphorus doping with (phosphoric acid chloride) and patterning, the polysilicon film is left only in the element formation region. Then, a SiO2 film having a thickness of about 6000Å is formed and patterned to form the floating gate 4 made of a polysilicon film and the SiO2 film 5 on the floating gate 4.

Then, about 3 is formed on the entire surface of the substrate by thermal oxidation.
After forming a second gate oxide film having a film thickness of 00Å, a polysilicon film having a film thickness of about 6000Å is formed, phosphorus is doped with POCl 3, for example, and the polysilicon film is anisotropically etched to form a word line. The control gate 7 is formed by self-alignment.

Further, after one side wall polysilicon film is removed by isotropic etching using the resist film as a mask, for example, phosphorus ions (31 P +) are accelerated at an acceleration voltage of 50 KeV and an implantation amount of 5E15 / cm2 (5, 5).
E15 means 5 times 10 to the 15th power. The same applies hereinafter. By implanting under the conditions of (4), an N + type source diffusion layer 8 is formed, and after removing the resist film,
An HTO film having a thickness of about 1500Å is formed on the entire surface, and the HTO film is anisotropically etched to form side surfaces of the floating gate 4 and the SiO2 film 5 and side surfaces of the control gate 7 which are stacked. Sidewall spacers 9 and 10 are formed.

Further, using a resist film (not shown) as a mask, for example, phosphorus ions (31P +) are accelerated to about 50K.
Implantation is performed under the conditions of eV and an implantation dose of 1E14 / cm @ 2, and then, for example, arsenic ions (75 As @ +) are accelerated at an acceleration voltage of about 50.
The N-type drain diffusion layer 11 and the N + type drain diffusion layer 12 are formed by implanting under the conditions of KeV and an implantation amount of 5E15 / cm2 and annealing.

According to such a non-volatile semiconductor memory device, the polysilicon film for forming the control gate can be formed on the substrate by self-alignment, and the area of the lower surface of the control gate is different from that of the floating gate as in the prior art. The size of the bottom surface of the control gate is reduced due to the degree of overlap with the gate, and there is no concern that leakage current will increase due to the short channel effect.In addition, there is no need to provide an extra space in consideration of the amount of shift, and the cell size is reduced. Can be miniaturized.

(2) Second Embodiment Hereinafter, a second embodiment will be described with reference to FIGS. 3 to 12. A LOCOS oxide film 2 as an element isolation film is formed in a region other than the element formation region of the semiconductor substrate 21 shown in FIG.
2 is formed by a LOCOS (Local Oxidation Of Silicon) method, and a gate oxide film 23 having a film thickness of about 100 Å is formed in the element forming region.

Further, from the gate oxide film 23 to the LOCO
After forming a polysilicon film having a film thickness of about 2000 Å over the end portion of the S oxide film 22, for example, phosphorus is doped with POCl 3 to make it conductive. Then, by patterning, the polysilicon film 2 is formed only in the element formation region.
4 is left behind. Next, as shown in FIG. 4, HTO (High Temperature Oxid) having a film thickness of about 1500 Å is formed on the entire surface of the substrate.
e) After forming the film 25, a polysilicon film having a film thickness of about 4000 Å is formed and phosphorus-doped with POCl3, for example. Subsequently, the polysilicon film is anisotropically etched using the resist film 26 as a mask to pattern the polysilicon film to form a first control gate 27 made of the polysilicon film.

Then, with the resist film 26 and the first control gate 27 as a mask, the HTO film 25 is isotropically etched at about 1600 Å with hydrofluoric acid (HF), and the lower surface of the control gate 27 is removed as shown in FIG. At this point, the HTO film 28 is eroded, and the HTO film 28 is thinly constricted toward the upper part of the film. Next, as shown in FIG. 6, the polysilicon film 24 is formed using the resist film 26 as a mask.
Is anisotropically etched to form a floating gate 29 made of a polysilicon film, and then the resist film 2 is formed.
Remove 6.

Then, thermal oxidation is performed to form a thermal oxide film 30 having a film thickness of about 200 Å on the silicon surface as shown in FIG. Next, a polysilicon film having a thickness of about 6000 Å is formed on the entire surface, phosphorus-doped, and then anisotropically etched, so that the floating gate 29 to the first control gate 27 are removed as shown in FIG.
Polysilicon films 31 and 32 are formed on both sides of the polysilicon film. At this time, as shown in FIG. 8, the HTO film 28 formed between the floating gate 29 and the first control gate 27 is isotropically etched as described above, and becomes narrower toward the first control gate 27. Since it is formed in a constricted state, the polysilicon film 3
1, 32 can be formed in such a shape that the tip extends toward the constricted portion, and as will be described later, as shown in FIG. 9, the floating gate 29 and the second control gate 34 are located close to each other. The electric field at the time of tunneling electrons to the second control gate 34 becomes small, so that the electrons can easily escape.

Then, as shown in FIG. 9, a resist film 33 is formed.
The polysilicon film 31 on one side is removed by isotropic etching via the
Only the second control gate 34 consisting of 1 is left as a film. Then, using the resist film 33 as a mask, for example, phosphorus ions (31 P +) are accelerated to about 50 Ke.
Implantation is performed under the conditions of V and an implantation amount of 5E15 / cm @ 2 to form an N @ + -type source diffusion layer 35.

Next, after removing the resist film 33, an HTO film having a thickness of about 1500 Å is formed on the entire surface, and the HTO film is anisotropically etched to form the floating gate as shown in FIG. 29 and 1
Of the side surface extending over the control gate 27 of the
Side wall spacers 36 and 37 are formed on the side surfaces of the control gate 34 of the first control gate 27 and the second control gate 34, respectively.
Expose the surface of the. At the same time, the source diffusion layer 35
Also, the drain diffusion layer forming region described later is exposed.
Then, using a resist film (not shown) as a mask, for example, phosphorus ions (31 P +) are implanted under the conditions of an accelerating voltage of about 50 KeV and an implantation amount of 1E14 / cm 2, and then, for example, arsenic ions (75 As +) are accelerating voltage of about 50 KeV The N @ + -type drain diffusion layer 38 and the N @ + -type drain diffusion layer 39 are formed by implanting under the condition of an implantation amount of 5E15 / cm @ 2 and annealing.

Subsequently, a tungsten film as a selective CVD metal film is grown on the exposed Si by the selective CVD method, so that the first control gate 27 and the second control gate 27 are formed on the substrate as shown in FIG. A selective CVD tungsten film 40 is grown on the control gate 34 of
Since the first control gate 27 and the second control gate 34 are close to each other, the tungsten film 4
0 electrically connects the first control gate 27 and the second control gate 34 .

Then, as shown in FIG. 12, an APCVD SiO 2 film 41 is formed as an interlayer insulating film by the APCVD method on the entire surface of about 10000Å, a contact hole 42 is formed on the tungsten film 40, and the contact hole 42 is formed by the sputtering method. Metal film 43 to fill the inside
(Al film, Al / TiN film, Al-Si-Cu film, etc.) are formed.

As described above, in the present invention, the first control gate 27 and the second control gate 34 are electrically connected by the selective CVD tungsten film 40 by the selective CVD tungsten film 40, so that the control gate as a word line is formed. The resistance of the source line, the resistance of the drain diffusion layer, and the resistance of the contact hole between each diffusion layer and the metal film can be reduced.

Further, as shown in FIG. 8, since the HTO film 28 formed between the floating gate 29 and the first control gate 27 is formed in a narrowed shape toward the first control gate 27, Two
Control gate 34 can be formed in a shape in which the tip extends toward the constricted portion, so that the electric field at the time of tunneling electrons from the floating gate 29 to the second control gate 34 in this portion becomes small, It will be easier to pull out.

The technique for growing a selective CVD tungsten film on such a Si substrate by the selective CVD method is as follows.
IEDM Technical Digest. pp8
29-832, 1992 and the like. (3) Third Embodiment Next, with reference to FIG. 13, a third embodiment that enables further miniaturization with respect to the above-described second embodiment will be described. Note that FIG. 13 is a partially enlarged view corresponding to FIG. 9 of the above-described second embodiment, and for convenience of explanation, the same components as those in the second embodiment will be denoted by the same reference numerals and description will be omitted. Omit it.

In the second embodiment, there is a demand to reduce the capacitance between the polysilicon film which will be the floating gate 29 and the polysilicon film which will be the first control gate 27. However, in order to reduce the capacitance between both polysilicon films, the S formed between both polysilicon films is formed.
If the iO2 film is made thicker, the lateral width of both polysilicon films cannot be reduced to a certain range or less in consideration of lateral etching when the SiO2 film is isotropically etched in the step shown in FIG. There is a problem that there are restrictions and further miniaturization cannot be achieved.

Therefore, in the nonvolatile semiconductor memory device of this embodiment, as shown in FIG. 13, a thin SiO 2 film 2 is formed on the floating gate 29 made of a polysilicon film.
8A is formed and then a thick SiN film 28B is formed in order to reduce the capacitance.
The control gate 27 and the second control gate 34A are formed. That is, the SiO2 film 2
By forming the SiN film 28B on the 8A to prevent an increase in capacitance, and by forming the SiO2 film 28A thinly, the amount of lateral abrasion during isotropic etching can be reduced, and the second embodiment described above can be used. The widths of the floating gate 29 and the first control gate 27 can be made shorter than those of the above embodiment, and the cell size can be miniaturized.

(4) Fourth Embodiment Another embodiment in which the first control gate and the second control gate are connected will be described with reference to FIG. In the present embodiment, for example, after the CoSi2 film (cobalt silicide film) is formed, the selective CVD tungsten film of the first embodiment described above is selectively grown to form the first control gate and the second control gate. Is to connect with.

First, in the state shown in FIG. 10, that is, the first control gate 27 and the second control gate 32.
On the surface of the source diffusion layer 35 and the drain diffusion layer 3
Cobalt film is about 5
00Å Form. Subsequently, rapid thermal annealing (RT) was performed for about 60 seconds in an N2 atmosphere at about 650 ° C.
After performing A), for example, H3PO4 (phosphoric acid) and H2
O2 (hydrogen peroxide), HNO3 (nitric acid) and CH3 COO
After etching with H (acetic acid) or HCI (hydrochloric acid) and H2O2 (hydrogen peroxide), about 600 again.
By performing rapid thermal annealing (RTA) for about 60 seconds in a N 2 atmosphere at ℃, exposed portions of Si, that is, the surfaces of the first control gate 27 and the second control gate 34 as shown in FIG. On the source diffusion layer 35 and the drain diffusion layers 38 and 39.
An oSi2 film 51 is formed. And the CoSi2 film 5
Selective CVD tungsten film 5 on the surface 1 by the selective CVD method
2 is grown, and the first film is formed by the tungsten film 52.
The control gate 27 and the second control gate 34 are electrically connected. As described above, CoS
Instead of growing a selective CVD tungsten film on the i2 film, for example, a selective CV is formed on a TiSi2 film (titanium silicide film) via a TiN film (titanium nitride film).
The D aluminum film may be grown.

(5) Fifth Embodiment Further, as another embodiment in which the first control gate and the second control gate are connected, a Ti film having a thickness of about 500 Å is formed on the entire surface. Later about 6
By performing rapid thermal annealing (RTA) for about 60 seconds in an N2 atmosphere at 00 ° C to 750 ° C, as shown in Fig. 15, an N + type source diffusion layer 35 and an N- type source diffusion layer 35,
A TiSi2 film (titanium silicide film) 61 is formed on the N + type drain diffusion layers 38, 39 and the first and second control gates 27, 34, and a TiN film (titanium nitride film) 62 is formed on the entire surface. Form.

Next, about 500 Å by the APCVD method.
Is formed, and a hydrofluoric acid treatment is performed through the resist film 64 to form APCVD SiO2 film 63 as shown in FIG.
The CVDSiO2 film 63 is removed, and the APCVDSiO2 film 65 is left as a film. Then, the resist film 64 and SiO
The portion of the TiN film 62 not masked with the 2 film is H2S.
It is removed by etching with O4 (sulfuric acid), hydrogen peroxide (H2O2) and water (H2O), and as shown in FIG.
The film 66 is left as a film.

Then, N of about 800 ° C to 850 ° C
Rapid thermal annealing (RTA) is performed for about 60 seconds in the atmosphere to reduce the resistance of the TiSi2 film 61. As described above, the first control gate 2
7 and the second control gate 34 are electrically connected. The silicide film may be formed using not only the Ti film but also a Ni film, a Co film, or the like.

(6) Sixth Embodiment Next, in the second, third, and fourth embodiments described above, the first and second active regions on the activated region are formed by the selectively-grown selective CVD tungsten film. The control gates are electrically connected to each other, but contact holes are formed on the first control gate and the second control gate extending on the field oxide film, and the metal film is formed through the contact holes. Forming a fourth control gate electrically connecting the first control gate and the second control gate to each other.
The embodiment will be described with reference to FIG. Note that in FIG. 18, for convenience of description, the same components as those in the above-described embodiment are designated by the same reference numerals and the description thereof will be omitted.

As shown in FIG. 18, the field oxide film 71 is formed.
After the interlayer insulating film 72 is formed on the first control gate 27 and the second control gate 34 extending above, the contact hole 7 is formed using a resist film (not shown) as a mask.
3 is formed, and the metal film 74 is formed through the contact hole 73.
May be formed to electrically connect the first control gate 27 and the second control gate 34.

When the first and second control gates are connected to each other in this way, as compared with the case where the first and second control gates are connected to each other by growing the selective CVD tungsten film described above, The manufacturing process is simplified. Further, since the contact hole 73 is formed on the first control gate 27 and the second control gate 34 extending on the field oxide film 71, it is assumed that the opening diameter of the contact hole is larger than the gate length. However, since the thick field oxide film is only slightly scraped off, the metal film 74 and the substrate are not connected to each other.
The control gate 27 and the second control gate 34 are securely connected. After forming the first control gate and the second control gate on the semiconductor substrate and forming the interlayer insulating film as described above, a contact hole is formed in the interlayer insulating film and the contact hole is filled. A metal film may be formed on the first and second control gates so as to connect the first and second control gates to each other.

[0039]

As described above, according to the nonvolatile semiconductor memory device of the present invention, the polysilicon film for forming the control gate can be formed on the substrate by self-alignment, and the area of the lower surface of the control gate is the same as in the prior art. There is no risk that the size of the bottom surface of the contact gate will be reduced due to the overlapping of the floating gate and control gate, and the short channel effect will not increase the generation of leakage current. The cell size is eliminated, and the cell size can be reduced.

Further, according to the method for manufacturing a nonvolatile semiconductor memory device of the present invention, by electrically connecting the first control gate and the second control gate with the selective CVD metal film, control as a word line is performed. It is possible to reduce the resistance of the gate, the resistance of the source line, the resistance of the drain diffusion layer, and the resistance of the contact hole between each diffusion layer and the metal film.

Further, since the oxide film formed between the floating gate and the first control gate is formed in a narrowed shape toward the first control gate, the second control gate is formed in the narrowed portion. Since the tip can be formed so as to extend toward the second control gate, the electric field at the time of tunneling electrons from the floating gate to the second control gate becomes small, and the electrons easily escape.

Further, a contact hole is formed in the interlayer insulating film formed on the first and second control gates, and a metal film is buried in the contact hole to connect the first and second control gates to each other. If connected, the first and second selective CVD metal films are grown by selective growth.
The manufacturing process is simpler than that of connecting control gates to each other.

[Brief description of drawings]

FIG. 1 is a sectional view showing a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a plan view showing the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is a first sectional view showing a nonvolatile semiconductor memory device according to a second embodiment of the present invention.

FIG. 4 is a second cross-sectional view showing the nonvolatile semiconductor memory device according to the second embodiment of the present invention.

FIG. 5 is a third cross-sectional view showing the nonvolatile semiconductor memory device according to the second embodiment of the present invention.

FIG. 6 is a fourth cross-sectional view showing the nonvolatile semiconductor memory device according to the second embodiment of the present invention.

FIG. 7 is a fifth cross-sectional view showing the nonvolatile semiconductor memory device according to the second embodiment of the present invention.

FIG. 8 is a sixth sectional view showing the nonvolatile semiconductor memory device according to the second embodiment of the present invention.

FIG. 9 is a seventh cross-sectional view showing the nonvolatile semiconductor memory device according to the second embodiment of the present invention.

FIG. 10 is an eighth cross-sectional view showing the nonvolatile semiconductor memory device according to the second embodiment of the present invention.

FIG. 11 is a ninth cross-sectional view showing the nonvolatile semiconductor memory device according to the second embodiment of the present invention.

FIG. 12 is a tenth sectional view showing a nonvolatile semiconductor memory device according to a second embodiment of the present invention.

FIG. 13 is a sectional view showing a nonvolatile semiconductor memory device according to a third embodiment of the present invention.

FIG. 14 is a sectional view showing a nonvolatile semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 15 is a first sectional view showing a nonvolatile semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 16 is a second cross-sectional view showing the nonvolatile semiconductor memory device according to the fifth embodiment of the present invention.

FIG. 17 is a third cross-sectional view showing the nonvolatile semiconductor memory device according to the fifth embodiment of the present invention.

FIG. 18 is a sectional view showing a nonvolatile semiconductor memory device according to a sixth embodiment of the present invention.

FIG. 19 is a cross-sectional view showing a conventional nonvolatile semiconductor memory device.

FIG. 20 is a cross-sectional view showing a conventional nonvolatile semiconductor memory device.

Claims (10)

(57) [Claims] 1. A floating gate formed on a gate insulating film on a semiconductor substrate, and a thin film formed on the floating gate in an upward direction.
An insulating film formed so as to have a constriction, a control gate formed near the side surface of the floating gate via an insulating film, a first impurity layer formed adjacent to the floating gate, and A non-volatile semiconductor memory device, comprising: a second impurity layer formed so as to be adjacent to the control gate. 2. A process of forming a floating gate on the gate insulating film on a semiconductor substrate, wherein an insulating film on the floating gate, this
As it goes upward, it becomes thinner and has a constriction
A step of forming a control gate near the side surface of the floating gate via an insulating film, and a first impurity layer adjacent to the floating gate and a second impurity layer adjacent to the control gate.
And a step of forming an impurity layer, the method for manufacturing a nonvolatile semiconductor memory device. 3. The step of forming the floating gate comprises forming a conductive film and a thick insulating film on the gate insulating film, and then etching the thick insulating film and the conductive film using a resist film as a mask to form an upper portion thereof. thick insulating film is laminated, further the thick insulating film according to the upward
3. The method for manufacturing a non-volatile semiconductor device according to claim 2, wherein the floating gate is formed in a shape having a constriction so as to become thin . 4. A first conductive film is formed on a semiconductor substrate through a gate insulating film, an insulating film is formed so as to cover the conductive film, and then a second conductive film is formed and a resist film is interposed. And patterning the conductive film to form a first control gate, and isotropically etching the insulating film using the resist film and the first control gate as a mask to form a first control gate lower surface. Forming a floating gate by anisotropically etching the first conductive film using the resist film as a mask; and forming the floating gate, the floating gate and the first control gate A step of forming an insulating film so as to cover the first control gate, and the step of forming a third conductive film on the entire surface and anisotropically etching the conductive film. Side wall portions extending over the floating gate to the residual film of the conductive film and,
Forming a second control gate on one side wall portion that extends over the first control gate and the floating gate by isotropically etching and removing one conductive film using the resist film as a mask; A step of implanting impurity ions into a mask to form a first impurity layer adjacent to one end of the floating gate; and a step of implanting impurity ions using a resist film as a mask
And a step of forming a second impurity layer adjacent to the control gate, the method for manufacturing a nonvolatile semiconductor memory device. 5. A first conductive film is formed on a semiconductor substrate through a gate insulating film, an insulating film is formed so as to cover the conductive film, and then a second conductive film is formed and a resist film is interposed. And patterning the conductive film to form a first control gate, and isotropically etching the insulating film using the resist film and the first control gate as a mask to form a first control gate lower surface. A step of leaving the insulating film in a corroded state; a step of anisotropically etching the first conductive film using the resist film as a mask to form a floating gate; and a step of forming the floating gate and the first control gate. A step of forming an insulating film so as to cover, and a step of forming a third conductive film on the entire surface and then anisotropically etching the conductive film to form the first control gate. A conductive film is left on the side wall portion extending over the floating gate,
Forming a second control gate on one side wall portion that extends over the first control gate and the floating gate by isotropically etching and removing one conductive film using the resist film as a mask; Implanting impurity ions into a mask to form a first impurity layer adjacent to one end of the floating gate; and forming an insulating film over the entire surface and anisotropically etching the first control gate A sidewall space is formed on the sidewall portion extending over the floating gate and the sidewall portion of the second control gate, and the head portions of the first and second control gates, the first impurity layer and the second impurity layer are formed. Step of exposing the impurity layer formation region and implanting impurity ions using the resist film as a mask The Te second
Forming a second impurity layer adjacent to the control gate, and forming a metal on the first and second control gates and on the first impurity layer and the second impurity layer forming region by a selective CVD method. Forming a film to electrically connect the first and second control gates, and at the same time lower the layer resistance of the first and second impurity layers. Device manufacturing method. 6. A first conductive film is formed on a semiconductor substrate via a gate insulating film, and SiO is formed so as to cover the conductive film.
A step of forming a second conductive film after forming the second film and the SiN film, and patterning the conductive film and the SiN film through a resist film to form a first control gate; Control gate and SiN
A step of isotropically etching the SiO2 film using the film as a mask to leave the SiO2 film on the lower surface of the SiN film in a corroded state, and anisotropically etching the first conductive film using the resist film as a mask. A step of forming a floating gate by etching; a step of forming an insulating film so as to cover the floating gate and the first control gate; and a step of forming a third conductive film over the entire surface and then anisotropically transforming the conductive film. Conductive etching is performed to leave a conductive film as a residual film on the side wall portion extending over the first control gate and the floating gate,
Forming a second control gate on one side wall portion that extends over the first control gate and the floating gate by isotropically etching and removing one conductive film using the resist film as a mask; Implanting impurity ions into a mask to form a first impurity layer adjacent to one end of the floating gate; and forming an insulating film over the entire surface and anisotropically etching the first control gate Sidewall spacers are formed on the sidewall portion extending over the floating gate and the sidewall portion of the second control gate, and the head portions of the first control gate and the second control gate, the first impurity layer, and the second impurity layer are formed. Step of exposing the impurity layer formation region and implanting impurity ions using the resist film as a mask The Te second
Forming a second impurity layer adjacent to the control gate, and forming a metal film on the first and second control gates and on the first and second impurity layers by a selective CVD method. A step of electrically connecting the first and second control gates and simultaneously lowering the layer resistance of the first and second impurity layers. 7. A silicide film is formed on the first and second control gates, and then a metal film is formed by a selective CVD method to electrically connect the first and second control gates. 7. The method for manufacturing a non-volatile semiconductor memory device according to claim 5 or claim 6. 8. A titanium silicide film is formed on the first and second impurity layers by forming a titanium film on the entire surface including the first and second control gates and then performing rapid thermal annealing. After a titanium nitride film is formed on the entire surface, an APCVD SiO2 film is formed on the entire surface by the APCVD method.
At least a first control gate and a second on the O2 film
The rapid thermal annealing is performed by leaving the APCVD SiO2 film as a residual film through the resist film formed so as to cover the head of the control gate, and performing the rapid thermal annealing with the titanium nitride film as a residual film through the APCVD SiO2 film. And the second control gate is electrically connected, and at the same time, the resistance of the titanium silicide film on the first and second impurity layers is lowered. A method for manufacturing a nonvolatile semiconductor memory device according to the item. 9. An interlayer insulating film is formed to cover the first and second control gates, and a contact hole is formed in the interlayer insulating film to form the first and second control gates.
6. The head of the control gate is exposed, and a metal film is formed so as to fill the contact hole, whereby the first and second control gates are electrically connected. Alternatively, the method for manufacturing a nonvolatile semiconductor memory device according to claim 6. 10. The method for manufacturing a nonvolatile semiconductor memory device according to claim 9, wherein the contact hole is formed on the first and second control gates extending on the field insulating film. .