JPH0523000B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor integrated circuit technology and a technology that is particularly effective when applied to a semiconductor memory device.
For example, the present invention relates to a technique that is effective when used in the configuration of a word line drive circuit of a micro ROM (read-on memory) in a semiconductor integrated circuit equipped with a micro-program control circuit.

[Background technology]

As a word line drive circuit in a semiconductor memory device (hereinafter referred to as IC memory), a circuit format as shown in FIGS. 1 and 2, for example, has been proposed (Japanese Patent Laid-Open No. 150189/1989).

The circuit in Figure 1 is a CMOS (complementary type) that detects the level of the word line WL at the far end of the word line WL.
MOS) inverter INV and word line
A MOSFET (insulated gate field effect transistor) _Q3 is provided between WL and the power supply voltage Vcc.
As a result, when the potential of the word line WL to be selected exceeds the logic threshold voltage of the CMOS inverter INV, the output of the CMOS inverter INV is changed to low level.
Turn on MOSFETQ ₃ . As a result, the aim is to shorten the time it takes for the word line WL, which is made of polysilicon and has a relatively high resistance value, to reach the final level (Vcc).

However, in the circuit of the type shown in Figure 1, when the potential of the selected word line WL is to be lowered to the non-select level (ground potential), MOSFET Q ₃ is connected to the output of the CMOS inverter INV. It is turned on. Therefore
A through current flows through the word line through MOSFETQ ₃ , and the potential of the word line is difficult to fall.

On the other hand, in the circuit shown in Figure 2, the above
MOSFETs _Q4 and _Q5 for reset are inserted in series with _MOSFETQ3 between the power supply voltage Vcc and between the word line WL and the ground point, respectively. These MOSFETs Q ₄ and Q ₅ are the word line drive circuit
Controlled on and off in synchronization with WD. In other words,
When a word line is selected, MOSFET _Q4 is turned on by the low level of reset signal P;
MOSFETQ ₅ is turned off. As a result, the illustrated circuit operates in the same manner as the circuit shown in FIG. 1 above when selected. When the word line is set to a non-selected level, the reset signal P is changed to a high level. At this time, MOSFETQ ₄ is turned off and
Also, since _Q5 is turned on, the selected word line is quickly changed to a low level.

However, the circuit of the type shown in FIG. 2 has a large number of circuit elements. Also, series connection
Unless the element dimensions of these MOSFETs are made larger than those of MOSFETQ ₃ in the circuit format shown in Figure 1 so as to reduce the combined impedance of MOSFETQ ₃ and Q ₄ , it will be difficult to speed up the rise of the word line. .

However, in an IC memory, the area occupied by the memory array becomes smaller when the spacing between word lines is made as narrow as possible. Therefore, as mentioned above, if the dimensions of the elements that make up the circuit have to be increased or the number of elements has to be increased,
Particularly in an IC memory composed of one-element type memory cells, it is difficult to arrange circuits in accordance with the spacing between each word line. As a result, the chip size becomes larger than necessary. The inventor of the present invention has revealed that there are the above-mentioned problems.

[Purpose of the invention]

An object of the present invention is to provide a word line drive circuit that can shorten the rise and fall times of word lines in a semiconductor memory circuit and improve access time.

Another object of the present invention is to provide a semiconductor memory circuit without significantly increasing the chip size.
An object of the present invention is to provide a word line driving circuit that can drive word lines from both directions.

Still another object of the invention is to provide a low power consumption semiconductor memory circuit.

Still another object of the present invention is to develop a layout technique that allows sufficient arrangement of word line drive circuits as described above between relatively narrow word lines in a memory array consisting of one-element memory cells. It is about providing.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

The outline of typical inventions disclosed in this application is as follows: directly turned on by the potential of the word line;
This is a switch MOSFET that is controlled off.
A switch connected in series between the MOSFET and the power supply voltage on one side of the circuit, and controlled on and off by a signal that controls the operation of the word line driver.
The MOSFET constitutes level detection means for the word line, and is connected between the signal line that supplies the control signal and the far end of the word line to turn on and off depending on the output signal from the level detection means. By providing a controlled switch MOSFET,
Avoid connecting the control MOSFET in series with the MOSFET that charges up or down the word line when the potential of the word line goes above or below a certain level.
To make it possible to reduce the element size of MOSFET and to prevent through current from flowing at the time of word line reset. In addition, the auxiliary drive circuit that detects the level of the word line and charges up or down the word line from the opposite direction (far end) can be configured with three transistors. To efficiently arrange each auxiliary drive circuit between lines.
This achieves the above objectives of shortening the rise and fall times of word lines, improving access time, and reducing power consumption without increasing chip size.

〔Example〕

FIG. 3 is a circuit diagram of a read-only memory (hereinafter referred to as ROM) of the embodiment. As will become clear from the explanation that follows, the ROM of this embodiment is capable of high-speed operation, and is a cathode ray tube controller (hereinafter referred to as a CRT controller) that constitutes a microcomputer system together with a microprocessor (hereinafter referred to as a CPU).
and hard disk controllers and other peripherals
Suitable for configuring micro ROM provided in LSI.

In other words, CRT controllers, hard disk controllers, etc. are subject to
In order to more precisely control various parts such as the CRT display device and hard disk driver in accordance with instructions from the CPU, a micro ROM is provided that stores microprograms for executing such instructions. Such a micro ROM needs to read the corresponding micro instructions as quickly as possible in response to instructions from the CPU, output control signals, and control each part. Therefore, for example
It is desired that the micro ROM be accessible at a high frequency such as 10MHz.

The ROM of the embodiment described below is characterized by being capable of such high-speed operation and occupying a small area. Although not particularly limited, the ROM of this embodiment is used as a micro ROM in an integrated circuit for an advanced CRT controller. The ROM of this embodiment, along with various registers, arithmetic processing circuits, timing control circuits, etc. that constitute this integrated circuit, are formed on one semiconductor substrate by a known complementary MOS integrated circuit manufacturing technique. Note that an advanced CRT controller is different from a normal controller, which receives coded display data and outputs drawing data at a predetermined timing by decoding the display data. In response to a drawing command, drawing data corresponding to the drawing command is formed by calculation.

In FIG. 3, a memory array is designated by the circuit symbol M-ARY, and includes a plurality of memory cells M ₁₁ to Mmn arranged in a matrix. Each memory cell includes a plurality of word lines _WL1 to WLm extending in the row direction,
Multiple data lines extending in the column direction DL ₁ or
placed at each intersection of DLn.

Each of the memory cells M ₁₁ to Mmn constituting the memory array M-ARY is substantially one memory cell.
It can be considered to consist of MOSFETs. “1” of storage information in each memory cell,
“0” corresponds to whether each memory cell is conductive or non-conductive when the respective memory cell is selected. Although not particularly limited, in this embodiment, the storage information "1" and "0" correspond to a state in which the MOSFET is connected and a state in which the MOSFET is not connected between the word line and the data line.

In FIG. 3, memory cells such as M ₁₁ and M ₁₂ are represented by circuit symbols, indicating that the drains of the memory elements constituting each are connected to the corresponding data line. There is. On the other hand, memory cells such as M ₂₁ and M ₂ n without a circuit symbol indicate that the memory elements that should constitute each memory cell are not connected to the corresponding data line. In this embodiment, although not particularly limited, the MOSFET that constitutes the memory cell is of an N-channel type.

In the memory array M-ARY, memory cells M ₁₁ , M ₁₂ , ... ~ _{M 1} n in each row: M ₂₁ , M ₂₂ , ...
Word lines WL ₁ to WL _n are arranged corresponding to M ₂ n; to Mm ₁ , Mm ₂ , . . . Mnm, respectively. In addition, memory cells M ₁₁ , M ₁₂ , . . . in each column
〜M ₁ n: M ₂₁ , M ₂₂ , ...M ₂ n: 〜 Mm ₁ , Mm ₂ ,
...Data lines (or bit lines) DL ₁ to DL _o are arranged corresponding to Mmn.

In the memory array M-ARY, ground lines _GL1 to GLi are provided to which the sources of MOSFETs constituting the memory cells in each row are commonly connected. The grounding lines GL ₁ to GLi are connected to the memory array M-
On one side of ARY, connected to a common ground wire CGL,
A ground potential GND is supplied to it.

In the memory array M-ARY, disconnection of MOSFETs is achieved by not forming MOSFETs that should be used as memory cells, or by forming them in advance.
This can be achieved by methods such as not coupling the drain region of the MOSFET to the data line to which it is associated. In this embodiment, as will be explained later using plan views and cross-sectional views of FIGS. 5 to 7, a method is adopted in which no MOSFET to be used as a memory cell is formed. This method is advantageous in that it allows for a reduction in memory array size.

The MOSFET of this embodiment is designed to be able to reduce its size regardless of the required characteristics and to avoid parasitic capacitances such as those caused by the overlap of the gate electrode with the drain and source regions. It is formed by self-alignment techniques in order to minimize undesired capacitance. In other words, the gate electrode of MOSFET is composed of a polysilicon layer,
The drain region and source region of the MOSFET are formed by an impurity introduction method such as an ion implantation method using the polysilicon as an impurity introduction mask.

Each of the word lines _WL1 to WLm in FIG. 3 is structurally composed of a polysilicon layer integrated with the gate electrode of a MOSFET that constitutes a memory cell. Note that when the word line is coupled to each gate electrode through a contact hole, each contact hole must be made relatively large in size, and as a result, it is difficult to reduce the size of the memory array M-ARY. However, the above-mentioned integrated configuration does not have such difficulties.

The data lines _DL1 to DLn in FIG. 3 can be constructed from semiconductor wiring regions formed simultaneously with the drain and source regions of MOSFETs constituting the memory cell. However, in this case, the semiconductor wiring region occupies a large area in the region constituting the memory array, making it difficult to downsize the memory array.
In this case, the PN junction formed between the semiconductor wiring region and the surrounding semiconductor region also has a relatively large junction capacitance. The large capacitance of the data lines limits the operating speed of the memory.

Therefore, in this embodiment, as shown in FIGS. 5 to 7, each data line is composed of a vapor-deposited aluminum layer formed on a semiconductor substrate with an insulating film interposed therebetween. Configure each data line and memory cell
It is coupled to the drain region of the MOSFET at the contact hole. By configuring the data lines three-dimensionally, it is possible to reduce the size of the memory array. Furthermore, the data line made of an aluminum layer has only a relatively small parasitic capacitance because the insulating film on the semiconductor substrate is relatively thick.

The memory array of this embodiment can be miniaturized as described above. Each word line and each data line has relatively small parasitic capacitance. Each word line constitutes a relatively light capacitive load to its drive circuit.

However, a word line made of a polysilicon layer has a resistivity significantly higher than that of a wiring layer made of an aluminum layer.
The word line itself causes significant signal delay due to its relatively large resistance and parasitic capacitance. This signal delay is sufficiently reduced by auxiliary drive circuits _AWD1 to AWDm, which will be described later.

Auxiliary drive circuit AWD ₁ or
AWDm and word line driver WD ₁ to WDm
The operation of these devices is controlled by the control signal φ. The signal line to which this control signal φ is supplied is not directly related to the reduction in the area occupied by the memory array, and therefore its main portion is formed of an aluminum wiring layer. Aluminum interconnect layers have significantly lower resistance than polysilicon interconnect layers. Therefore, the aluminum interconnect layer causes virtually negligible signal delay. Since the signal delay occurring in the aluminum wiring layer as the signal wiring to which the control signal φ is supplied is sufficiently small, it is possible to determine where on the semiconductor substrate the control circuit (not shown) that forms the control signal φ is placed. Also, the timing of the control signal φ supplied to the auxiliary drive circuit described later can be made appropriate.

In FIG. 3, the circuit designated by the circuit symbol X-DEC is an X decoder circuit that decodes the lower several bits of the address signal to form a row selection signal. With this X-decoder circuit X-DEC,
One of the word line drivers WD ₁ -WDm provided corresponding to each word line WL ₁ -WLm is driven, so that one word line is raised to a high level.

Although not particularly limited, the X decoder circuit
The DEC includes a plurality of gate circuits as decoders that receive address signals A ₀ to A ₇ and an output circuit that receives the output of each gate circuit. Each gate circuit is constructed from a dynamic type circuit rather than a static type circuit. That is, each gate circuit is composed of a P-channel type precharge MOSFET whose switch state is controlled by a control signal, and a plurality of N-channel type input MOSFETs connected in series. The output circuit consists of an even number of series-connected clocked inverters consisting of complementary MOSFETs. One clocked inverter constituting the output circuit holds its output when the corresponding gate circuit is precharged, and when the corresponding gate circuit is operated, that is, the output of the gate circuit is determined according to its input. captures the output of that gate circuit. Another clocked inverter takes in the output of the preceding clocked inverter in synchronization with its operation.

The word line drivers WD ₁ -WDm are constituted by clocked inverters made of complementary MOSFETs, for example, and their operations are controlled by a control signal φ such as a system clock signal.

In this embodiment, the X decoder circuit X-
Since the DEC is also constituted by a dynamic type circuit as described above, the operation of the X decoder circuit and word line driver is as follows. That is, the X-decoder circuit X-DEC outputs a row selection signal corresponding to the input address signal during a half period of the control signal φ (for example, a period in which the signal φ is at a low level). At this time, the word line driver is placed in a non-operating state.

Next, in the next half cycle (high level cycle) of the control signal φ, the word line drivers WD ₁ to WDm are put into an operating state (input capture), and as a result, one word line is selected. At the same time, the gate circuit in the X-decoder circuit X-DEC is placed in a precharge state. In this way, the X decoder circuit X-DEC and the word line drivers WD ₁ to WDm
Power consumption is reduced by operating in synchronization with the control signal (clock) φ.

Discharge MOSFETs Qd ₁ to Qdm are connected to the starting ends (word line driver side) of each of the word lines WL ₁ to WLm and a ground point of the circuit, respectively. For this death charge
The MOSFETs Qd ₁ to Qdm are formed in an N-channel type, and are controlled on and off by a control signal φ having an opposite phase to the control signal φ. When the word line drivers WD ₁ -WDm are in an inactive state, the MOSFETs Qd ₁ -Qdm are in an on state. Accordingly, each word line is set to low level.

On the other hand, auxiliary drive circuits AWD ₁ -AWDm are connected to the far ends of each of the word lines WL ₁ -Wlm. Each auxiliary drive circuit has one of them AWD ₁
As shown in FIG. 3 as a representative example, it consists of three MOSFETs Q ₁₁ to Q ₁₃ . Among these, the N-channel MOSFET Q ₁₁ has its source terminal connected to the ground point of the circuit, and its gate terminal connected to the word line WL.
The P-channel type MOSFETQ ₁₂ , whose source/drain path is connected between the drain terminal of the MOSFETQ ₁₁ and the power supply voltage Vcc, has its gate terminal supplied with the control signal φ.

In addition, the P-channel type MOSFETQ ₁₃ has its source/drain path connected to a signal line and a word line that supply the control signal φ to the gate electrode of the MOSFETQ ₁₂ .
Connected between WL and WL. And this
The gate electrode of MOSFETQ ₁₃ is
MOSFETQ ₁₁ and Q ₁₂ are connected to the connection node n ₁ .

The operation of the auxiliary drive circuits AWD ₁ to AWDm will be explained as follows.

In other words, before the word line is selected, the word line level is low, so
MOSFETQ ₁₁ is turned off. Also, in response to the control signal φ being at low level,
MOSFETQ ₁₂ is turned on. node n ₁ is
By turning on MOSFETQ ₁₂ , it is precharged to the Vcc level. At this time,
MOSFETQ ₁₃ is turned off because its gate voltage is at a high level.

Next, when the control signal φ rises to high level,
Accordingly, the word line drivers WD ₁ -WDm are operated, and the potential of one of the word lines WL ₁ -WLm begins to rise to a high level, as shown in FIG. 4. Furthermore, MOSFETQ ₁₂ is turned off by control signal φ. At this time, node _n1 is held at the precharge level. And the word line WL
The potential at the far end of is the threshold voltage of MOSFETQ ₁₁
When Vthn is exceeded, MOSFET Q ₁₁ is turned on accordingly, so that the charge of node n ₁ is extracted and the level of node n ₁ decreases toward the ground potential (0V). MOSFETQ ₁₃ is turned on due to the decrease in the potential of node _n1 . As a result, charges flow into the word line WL from the signal line to which the high level control signal φ is supplied through _MOSFETQ13 .

Therefore, while the word line selectively driven by the word line driver rises toward the high level, it is also driven from the opposite direction (far end) by the auxiliary drive circuit and rapidly It is raised to the final attained level (Vcc). As a result, the rise of the word line, which would have been gradual as shown by the broken line A' in FIG. 4 without the auxiliary drive circuit AWD, becomes steeper as shown by the solid line A.
The fall time of a word line made of polysilicon having a relatively large resistance value is shortened.

In the auxiliary drive circuit corresponding to the unselected word line, depending on the low level of the word line,
Since MOSFETQ ₁₁ remains off, the charge at node _n1 remains at the pre-charge level (Vcc level). MOSFETQ ₁₃ maintains the cut-off state due to the high level of node _n1 . Therefore, even if a high level control signal φ is supplied to the source (or drain) of MOSFETQ ₁₃ , the level of unselected word lines will not be raised.

After reading of stored information is completed by selecting a word line, when the control signal φ is changed to low level to reset the word line, the operation of the illustrated circuit is as follows. That is, since the control signal with the opposite phase to the control signal φ is changed from low level to high level, MOSFETs Qd ₁ to Qdm are turned on, the charge in the word line is removed, and the potential of the word line that had been set to the selection level is reduced. It starts to go down.

At this time, in the auxiliary drive circuit AWD connected to that word line, as the control signal φ changes to low level, MOSFETQ ₁₂ is turned on, and the potential of node n ₁ rises to high level.
MOSFETQ ₁₃ is transitioned to the off state. here,
The size of MOSFETQ ₁₂ is determined in advance so that the potential rise speed of node n ₁ reaches a desired value. Accordingly, the time lag from when the control signal φ starts to change to low level until the MOSFET Q ₁₃ is completely turned off can be appropriately set. Therefore, immediately after the control signal φ changes to low level, it is turned on instantly.
Charge is extracted from the high level word line side to the control signal φ signal line side through MOSFETQ ₁₃ . As a result, compared to the case where the auxiliary drive circuit AWD is not connected to the far end side of the word line, the falling speed when the word line level starts to fall is increased, and the overall falling time is shortened. .

Having described the configuration of the word line drive circuit and its word line selection operation, the data line selection circuit will now be described.

On one side of the memory array M-ARY, there are switches connected to each data line DL ₁ to DLn.
MOSFET (hereinafter referred to as Y switch) Qy ₁ ~ Qyn
A multiplexer circuit MLP is provided. The multiplexer circuit MLP is a Y decoder circuit Y that decodes the upper bits of the address signal.
- Based on the selection signal from DEC, an appropriate number of data lines are selected from among the n data lines DL ₁ to DLn, and their output signals are supplied to an output circuit DOB consisting of a CMOS inverter.

Specifically, although not particularly limited, micro
In order to be able to read control words consisting of 8-bit data from ROM at once, memory array M
-ARY is provided with 32 data lines, of which 8 data lines are each connected to output signal lines DOL ₁ to DOL ₈ by a multiplexer circuit MLP. In other words, 32 Y switches
Qy ₁ to _{Qy 32} are grouped in groups of four and connected to one output signal line DOL, and in each Y switch group, one of them is connected to the Y decoder circuit Y-DEC.
is turned on by a selection signal from DOL ₁ to output one of the four data lines, respectively.
Connect to DOL ₈ . Each output signal line DOL ₁ ~ DOL ₈
The output circuit consists of a CMOS inverter, etc.
DOB ₁ to DOB ₈ are connected. Also, between each output signal line DOL ₁ to DOL ₈ and the power supply voltage V _CC ,
Precharge MOSFETs Qp ₁ to Qp ₈ are connected so that the same precharge signal φp is applied to their gate terminals.

The reason for having a configuration in which there are 32 data lines and 8 of them are selected by a multiplexer is as follows. In other words, in a micro ROM, a control word consisting of one word of 8 bits is written as, for example,
If it is desired to store 1024 words, it becomes necessary to construct a memory array by arranging memory cells of 8 bits in the word line direction and 1024 bits in the data line direction with 8 data lines. However, in this case, the memory array becomes extremely elongated in the data line direction, making layout within the chip difficult. Therefore, in the above example, 1024 words of control words are replaced with 256 words.
It is stored in a micro ROM with a ×32 bit configuration.

The precharge signal φp is generated before any one of the word lines is raised to high level by the word line drivers _WD1 to WDm, and is used to decode the upper two bits _A8 and _A9 of the address signal. The selection signal from the decoder circuit Y-DEC changes from high level to low level when a total of eight Y switches, one from each Y switch group, are turned on. Accordingly,
MOSFETQP ₁ ~ by precharge signal φp
When QP ₈ is turned on at the same time, the output signal line
The eight data lines corresponding to the Y switch Qy, which are turned on by the selection signals from each of DOL ₁ to DOL ₈ and the Y-decoder circuit Y-DEC, are
Pre-charged.

At this time, although not essential, a voltage drop approximately equal to the threshold voltage of Y switch Qy occurs, so the data line is at a potential lower than Vcc by the threshold voltage of Y switch Qy (Vcc -
Vth). Output signal line
DOL ₁ to _{DOL 8} are precharged almost to the Vcc level.

At the timing when the precharging of the data line is completed as described above, the precharge signal φp is changed to a high level. In response to this, precharge MOSFETs QP ₁ to QP ₈ are turned off.
Next, during the period in which the eight Y switches Qy are turned on by the selection signal from the Y-decoder circuit Y-DEC, one of the eight Y switches Qy is selected by the word line drivers WD ₁ to WDm and the auxiliary drive circuits AWD ₁ to AWDm. The word line of the book is raised to a high level.
As a result, a MOSFET as a storage element is connected to the intersection of one word line WL set to the selection level and the data line DL connected to the eight Y switches turned on. If it is,
The MOSFET is turned on and the charge on the data line is pulled to ground potential. On the other hand, if no storage element is connected to the intersection of the selected word line and data line, the data line is not discharged.

As a result, the selected data line DL is set to either the precharge level or the ground potential. The potential of this data line is the Y switch Qy
Output circuit (inverter) through DOB ₁ ~ _{DOB 8}
supplied to Output circuits DOB ₁ to DOB ₈ output signals corresponding to the potential of the data lines as read data.
Output as D ₀ to _{D 7} .

As explained above, according to the above embodiment, when the potential of the word line reaches a certain level or more at the far end of each word line WL ₁ to WLm, an auxiliary device detects this and drives the word line from the opposite direction. Drive circuit AWD ₁ ~
Since AWDm is provided, the rise time of the word line is shortened. Furthermore, MOSFET _Q13 , which pulls the word line from the far end to the Vcc level when selecting the word line, is turned off by the level detection circuit consisting of MOSFETs _Q11 and _Q12 when resetting the word line. No through current flows.

Furthermore, in the above embodiment, the auxiliary drive circuit AWD ₁
~AWDm are each composed of three MOSFETs _{Q 1} ~Q ₁₃ . Moreover, since no control switch MOSFET is connected in series with MOSFETQ ₁₃ that raises the word line to the Vcc level, the element size of MOSFETQ ₁₃ can be made smaller than in the circuit format shown in FIG. Furthermore, the level detection circuits (Q ₁₁ , Q ₁₂ ) are configured to operate dynamically in synchronization with the control signal φ.
Since _MOSFETQ11 and _Q12 only need to charge up or charge down node _n1 , the element dimensions of _MOSFETQ11 and _Q12 can also be made considerably smaller.

As a result, the area occupied by the auxiliary drive circuits AWD ₁ to AWDm is considerably reduced, and even in a memory array consisting of one-element memory cells as in the embodiment, the area occupied by the auxiliary drive circuits AWD 1 to AWDm is significantly reduced. It is possible to provide the above-mentioned auxiliary drive circuit AWD.

Next, in accordance with the word line pitch, each of the auxiliary drive circuits AWD is connected between each word line.
An example of a layout configuration that allows MOSFETQ ₁₁ to Q ₁₃ to be arranged is shown in the plan view of FIG. 5, and in FIGS. This will be explained using FIG.

Before explaining the layout configuration, the cross-sectional structure of the integrated circuit device will be explained based on FIGS. 6 and 7 in order to facilitate understanding of the configuration.

Integrated circuit devices are formed using known selective oxidation and self-alignment techniques. Various circuit elements include, but are not limited to, N
It is formed on a semiconductor substrate 30 made of type single crystal silicon and having a thickness of about 350 μm.

N-channel MOSFET on semiconductor substrate 30
A P-type well region 20 (FIG. 6) having a depth of about 3 .mu.m is formed in the area where the P-type well region 20 is to be formed. A region on the semiconductor substrate 30 and the P-type well region 20 that should be a non-active region, that is,
A field oxide film with a thickness of about 0.6 μm is formed using selective oxidation technology in areas other than active areas such as the MOSFET drain, source region, channel forming region, and semiconductor wiring region.
31a (FIGS. 6 and 7) is formed.

An insulating film 31b (FIGS. 6 and 7) with a thickness of about 500 Å is formed on the region to be the active region to serve as the gate insulating film of the MOSFET.
On field oxide film 31a and gate insulating film 31
On top of b is a polysilicon layer with a thickness of 3000 Å.
WLb, WLc, WLe (Fig. 6), 6a and 24 (Fig. 7) are formed. The part of the polysilicon layer formed on the gate insulating film is the MOSFET
The portion formed on the field oxide film constitutes a wiring.

A drain region, a source region, and a semiconductor region of the MOSFET are formed in the surface portion of the active region that is not covered by the polysilicon layer. That is, in FIG. 6, on the surface of the P-type well region 20, there are N-type semiconductor regions GL, 32a, 3.
2b etc. are formed. Further, in FIG. 7, a P-type semiconductor region 22 is provided on the surface of the semiconductor substrate 30.
a, 23a, etc. are formed.

The surface of the semiconductor substrate 30 including the surface of the polysilicon layer is made of phosphorus phosphosilicate glass,
Interlayer insulating film 33 having a thickness of about 3000 Å
(Figs. 6 and 7) are formed.

On the interlayer insulating film 33, aluminum layers DLn- ₁ (FIG. 6), 21a (FIG. 7), etc., which are to be used as wiring, are formed. In Figure 6, the aluminum layer
DLn- ₁ is in contact with the N-type semiconductor region 32a at the contact portion 11, that is, the contact hole formed in the interlayer insulating film 33. 7th
In the figure, aluminum layer 21a is in contact with polysilicon layer 6a and P-type semiconductor region 22a at a contact hole formed in interlayer insulating film 33, electrically coupling them together.

In addition, in FIG. 7, 26 is the semiconductor substrate 30.
This is an N ⁺ type semiconductor region with a high impurity concentration to form a contact with the semiconductor.

The structure shown in FIG. 6 and FIG. 7 can be obtained by the following manufacturing method, although it is not particularly limited.

First, a semiconductor substrate 30 is prepared, and a P-type impurity such as boron is introduced into a portion of its surface that is to be a P-type well region by a method such as ion implantation. The introduced P-type impurity is diffused by heat treatment to form a P-type well region.

Of the surface of the semiconductor substrate 30 on which the P-type well region is formed, a film consisting of a thin silicon oxide film and a silicon nitride film formed thereon as an oxidation-resistant mask is selectively applied over the portion to be used as an active region. to form.

A field oxide film 31a is formed by thermally oxidizing the semiconductor substrate on which the oxidation-resistant mask is formed.

After removing the oxidation-resistant mask, the semiconductor substrate is thermally oxidized to form a thin gate insulating film 31b.
form.

A polysilicon layer is formed over the entire main surface of the semiconductor substrate by chemical vapor deposition. Selectively etch the polysilicon layer.

On the active region where an N-type MOSFET is to be formed and
A P-type impurity such as boron is introduced into the surface of the semiconductor substrate by ion implantation while a portion of the polysilicon layer to be used as a type polysilicon wiring is covered with an ion implantation mask such as a photoresist film. In this ion implantation, the field oxide film 31a and the polysilicon layer act as an ion implantation mask. The P-type impurity is introduced into the surface portion of the semiconductor substrate via the gate insulating film 31b. As a result, P-type semiconductor regions 22a, 23a, etc. are formed in self-alignment with the polysilicon layer 24, as shown in FIG. The polysilicon layer 24 is
It is made into a P-type by ion-implanted P-type impurities.

After removing the photoresist coating as the ion implantation mask, a new photoresist coating is formed, and this photoresist coating is used as a mask to form the drain region, source region, semiconductor region 26, etc. of the N-type MOSFET. An N-type impurity such as phosphorus is selectively introduced onto the surface of the semiconductor substrate by ion implantation.

After removing the photoresist film, if necessary, the surface of the polysilicon layer is thermally oxidized in a thin layer. (This thermal oxidation is not shown in FIGS. 6 and 7.) The interlayer insulating film 33 is formed by chemical vapor deposition. A contact hole is formed in the interlayer insulating film 33 by selective etching technology.

An aluminum layer is deposited and then selectively etched.

In FIG. 5, the pattern of the P-type well region is shown by a two-dot chain line, and the pattern of the active region is shown by a broken line. Further, the pattern of the polysilicon layer is shown by a solid line, and the pattern of the aluminum layer is shown by a chain line. Furthermore, the contact portions are indicated by a square pattern combined with crosses. In the same figure, the area where the MOSFET channel will be formed is marked with hatching.

In this embodiment, although not particularly limited, the layout is designed such that four auxiliary drive circuits corresponding to four word lines constitute one unit block. In the upper part of the drawing of FIG. 5, a part of the memory array including one unit block and four word lines connected to it is shown.

A portion of the memory array and auxiliary drive circuit are formed on the P-type well region 20.

Word lines WL made of polysilicon layers are arranged in parallel with each other with a pitch of, for example, 9 μm in the memory array M-ARY. In the direction perpendicular to the word line WL, data lines DL made of aluminum layers are also arranged parallel to each other at equal intervals. On the main surface of the substrate between the word lines WL, every other N-type semiconductor region is formed to serve as a ground line GL. 1 ground wire GL
is a memory cell coupled to one word line, e.g. WLa, and a word line adjacent to that word line.
It is coupled to WLb and forms a common ground line with the memory cells.

Word line where this ground line DL is not formed
A so-called ROM eye is formed depending on whether a semiconductor region serving as a drain region of a memory cell (MOSFET) is formed between the WLs. In this embodiment, the drain region of the memory element (MOSFET) is formed between the word lines, for example, WLb and WLc, at a position sandwiched by each ground line DL. In the following description, for convenience, the region sandwiched between word lines WLb and WLc, that is, the region where the drain region of the memory element is formed, will be referred to as a contact region. At the formation position of each memory cell
When the drain region of the MOSFET is formed, a channel portion of the memory element is formed at a location shown by diagonal lines C in the figure. The drain region of the memory element is coupled to a corresponding data line via a contact hole 11.

Two memory elements belonging to one data line and coupled to mutually adjacent word lines via contact regions, such as memory elements disposed between data line DLn- ₃ and word lines WLb and WLc, , their drain regions are integrated and coupled to each data line DL via a contact hole 11.

Any word lines that are adjacent to each other via a contact region, such as the intersection of data line DLn- ₂ and word lines WLb and WLc, may be connected to each other as a memory element.
If the MOSFET is not coupled, the contact area is covered by field oxide. In this case, no contact hole is required since there is no corresponding drain region.

Further, one end of each of the plurality of ground lines DL made of the N-type semiconductor region is connected to the contact hole 1.
2, a common ground line CDL made of an aluminum layer arranged in parallel with the data line DL in a portion considered to be outside the memory array M-ARY.
are commonly connected to each other. Although not particularly limited, a plurality of common ground lines CDL may be provided not only outside the memory array but also within the memory array at appropriate pitches (for example, every 8 data lines). In this case, each of the plurality of common ground lines is brought into contact with the ground line GL, thereby reducing the resistance of the ground line as a circuit.

The four word lines WLa shown in the drawing
WLd is the gate electrode 1a to 1d of MOSFETQ ₁₁ that constitutes the corresponding auxiliary drive circuit AWD.
are connected to each. 2a and 2c indicate two adjacent MOSFETQ ₁₁
This is a common source area. These common source regions 2a, 2c are connected to contact holes 13a, 13.
It is connected to the aluminum layers 3a and 3c extending from the common ground line CGL through the common ground line CGL, and the ground potential GND is applied thereto.

4a to 4d are the above
This is an N-type semiconductor region that becomes the drain region of _MSFETQ11 . These semiconductor regions 4a-4d are coupled to one ends of aluminum signal lines 5a-5d via contact holes 14a-14d.

The aluminum signal lines 5a and 5d are extended on the field oxide film 31a, and the contact holes 15
It is connected to one end of the polysilicon gate electrodes 6a and 6d of MOSFETQ ₁₃ via a and 15d. Similarly, the aluminum signal lines 5b and 5c connect to the polysilicon gate electrode 6 of the corresponding MOSFETQ ₁₃ via contact holes 15b and 15c, respectively.
b, 6c.

77a to 7d are each
The P-type semiconductor regions 8a and 8c, which become the source (drain) regions of MOSFETQ ₁₃ , are adjacent to each other.
This is the common drain (source) region between _MOSFETQ13 . The semiconductor regions 7a and 7d are connected to word lines extending along the aluminum signal lines 5a and 5d via aluminum connection lines 9a and 9d, respectively.
Connected to one end of WLa and WLd. Similarly,
Semiconductor regions 7b and 7c are connected to aluminum connection lines 9b and 9.
It is connected to one end of the word lines WLb and WLc via c.

Common drain region 8a and 8c of MOSFETQ ₁₃
are coupled to the aluminum signal line 10 via contact holes 16a and 16c. A control signal φ is supplied to the aluminum signal line 10.

Further, the respective gate electrodes 6a to 6d of the MOSFETQ ₁₃ are extended on the field oxide film, and are extended through the aluminum layers 21a to 21b.
It is connected to P-type semiconductor regions 22a to 22d that become the drain regions of MOSFETQ ₁₂ . 23a,
23c is the adjacent
This is a P-type semiconductor region that becomes a common source region between _MOSFETQ12 . The semiconductor regions 22a to 22
Between d and 23a, 23c, there are four
A polysilicon gate electrode 24 formed in common with MOSFETQ ₁₂ is provided.

The gate electrode 24 is coupled to the extending portion 10a of the aluminum signal line 10 via the contact hole 17. Further, a power supply line 25 made of an aluminum layer is extended over the common source regions 23a and 23c via an insulating film. Common source regions 23a and 23c are coupled to power supply line 25 through contact holes 18a and 18c, and are supplied with power supply voltage Vcc.

As described above, an appropriate number of blocks each having a symmetrical layout with four auxiliary drive circuits as one unit are arranged along the data line DL arrangement direction (vertical direction in the drawing). Ru. This makes it possible to arrange each auxiliary drive circuit AWD corresponding to the spacing between the word lines WL, which are arranged with a relatively narrow pitch such as 9 μm.

In FIG. 5, reference numeral 26 denotes an N ⁺ type semiconductor region 19a formed on the main surface of the substrate in order to apply the substrate potential (Vcc) to the semiconductor substrate as described above.
19b is a contact hole for connecting the N ⁺ type semiconductor region 26 and the power supply line 25, and 19b is a contact hole for applying a potential (GND) to the P well region 20.

In the layout of the above embodiment, when the block pattern is repeatedly arranged in the vertical direction,
The common ground line CGL, aluminum signal line 10 and power supply line 25 are formed to be continuous between adjacent blocks. On the other hand, although not particularly limited, the common gate electrode 24 of the MOSFETQ ₁₂ is
It is divided into 4 pieces. This prevents the aluminum signal lines 10 from becoming electrically connected to each other between blocks via the gate electrodes 24, for example, if the aluminum signal lines 10 are disconnected in the middle. .

In other words, with the broken aluminum signal line 10 connected via the high-resistance polysilicon electrode 24, the circuit will operate as expected, but the desired operating speed will not be obtained. . Therefore, in order to eliminate such incomplete products, in the above embodiment, the polysilicon electrode 24 is deliberately divided into blocks.

In the embodiment of FIG. 3, a word line auxiliary drive circuit for a memory array is shown in which a selected word line is raised to a high level. On the other hand, for a memory array in which the MOSFETs constituting the memory cells are formed in a P-channel type and the selected word line is set to fall to a low level, for example, as shown in FIG. circuit can be used. In the circuit shown, the word line
The MOSFETQ ₁₁ that receives the potential of WL is a P channel type, and there is an N between this MOSFETQ ₁₁ and the power point.
Channel type MOSFETQ ₁₂ is connected in series, and the connection node n ₁ of MOSFETQ ₁₁ and Q ₁₂ is connected in series.
is connected between the word line WL and the signal line that supplies the control signal to the gate of MOSFETQ ₁₂ .
It is supplied to the gate terminal of MOSFETQ ₁₃ .

This makes it possible to shorten the fall time of a selective word line.

Furthermore, in the above embodiment (Fig. 3), a MOSFET Qd is connected to each word line, which is turned on and off by a control signal to extract charge from the word line. can extract charge through the ground-side MOSFET in the driver when resetting the word line. Therefore, in that case, MOSFET Qd in the embodiment of FIG. 3 may be omitted. Alternatively, MOSFET Qd may be connected to the far end of the word line instead of to the starting end. If this is done, the charge of the word line can be extracted from both sides at the time of reset, and the fall will be made faster.

Furthermore, in the above embodiment, the output signal lines DOL ₁ to
The signals read out by the output circuits DOB ₁ to _{DOB 8} connected to DOL ₈ are amplified and output, but once the read signal is received by a clocked inverter, it is sent to the output circuits DOB ₁ to DOB 8 consisting of CMOS inverters.
It may be configured to send it to DOB ₈ and output it.

Furthermore, if you want the selected word line to fall faster than its rise, connect an auxiliary drive circuit with the same configuration as shown in Figure 6 to the far end of the word line, and connect MOSFETQ ₁₃ . It is preferable to add φ to the gate instead of the control signal.
This allows the word line to fall particularly quickly during reset. Also, if you want to make the rise and fall of the word line faster, use the above circuit and the auxiliary drive circuit AWD shown in Figure 3.
It is also possible to use both circuits together and connect both circuits to the far end of the word line.

〔effect〕

(1) A switch MOSFET that is directly controlled on and off by the potential of the word line, and this MOSFET
A switch that is connected in series between the power supply voltage and the power supply voltage of one side of the circuit, and that is controlled on and off by a signal that controls the operation of the word line driver.
The MOSFET constitutes level detection means for the word line, and is connected between the signal line that supplies the control signal and the far end of the word line to turn on and off depending on the output signal from the level detection means. By providing a controlled switch MOSFET, when the potential of the word line becomes above or below a certain level, the MOSFET that charges up or down the word line is automatically turned on, and the word line is also turned on from the opposite direction (far end). The effect of charging up or charging down the line has the effect of shortening the rise and fall times of the word line and improving the access time.

(2) A switch MOSFET that is directly controlled on and off by the potential of the word line, and this MOSFET.
A switch MOSFET connected between the power supply voltage and one side of the circuit, and controlled on and off by a signal that controls the operation of the word line driver.
The level detection means for the word line is configured by the above, and the on/off control is controlled by the output signal from the level detection means between the signal line supplying the control signal and the far end of the word line. By providing a switch MOSFET that charges up or down the word line when the potential of the word line goes above or below a certain level, the control MOSFET is no longer connected in series with the MOSFET that charges up or down the word line. As the dimensions are reduced and the auxiliary drive circuit can be configured with three MOSFETs, each auxiliary drive circuit can be efficiently arranged to accommodate the relatively narrow pitch between word lines. This has the effect of reducing the chip size.

(3) A switch MOSFET that is directly controlled on and off by the potential of the word line, and this MOSFET.
A switch that is connected in series between the power supply voltage and the power supply voltage of one side of the circuit, and that is controlled on and off by a signal that controls the operation of the word line driver.
The MOSFET constitutes level detection means for the word line, and is connected between the signal line that supplies the control signal and the far end of the word line to turn on and off depending on the output signal from the level detection means. By providing a controlled switch MOSFET, the MOSFET that charges up or down the word line will not be connected to the power supply voltage terminal when the potential of the word line goes above or below a certain level. The effect that current no longer flows has the effect of reducing power consumption.

Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above Examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say. For example, the auxiliary drive circuit AWD ₁ or
The control signal φ supplied to AWDm is the control signal φ supplied to word line drivers WD ₁ to WDm.
It does not have to be in the same phase as the If noise that is undesirably applied to unselected word lines during the period until the level of the word line to be selected is changed by the auxiliary drive circuit is a problem, then The supplied control signal φ may be changed from low level to high level after the word line driver is operated. In this case, by delaying the off timing of MOSFETQ ₁₂ in each auxiliary drive circuit, that is, the precharge state stop timing, by an appropriate period, unnecessary potential fluctuations at node _n1 can be better prevented.

The control signal supplied to MOSFETQ ₁₂ in each auxiliary drive circuit is generated separately from the control signal supplied to MOSFETQ ₁₃ , and
The high level may be changed to the low level at a timing delayed from the change of the control signal supplied to the MOSFETQ ₁₃ from the high level to the low level. In this case, the discharge period of the selected word line by the auxiliary drive circuit can be set more clearly.

In the embodiment described above, the source terminal of MOSFETQ ₁₂ is connected to the power supply line that supplies the power supply voltage Vcc, but it may be connected to a signal line that supplies the control signal. By doing so, it takes a longer time to reset the word line.
By turning on MOSFETQ ₁₃ , the charge on the word line can be extracted to the signal line side of the control signal φ, thereby making it possible to accelerate the fall.

The point that the level detection circuit in the auxiliary drive circuit is constituted by a kind of dynamic circuit as in the above embodiment is not essential. If a slight increase in power consumption is acceptable due to circumstances such as a small number of auxiliary circuits to be provided, MOSFETQ ₁₂
This MOSFETQ _{12 can be changed into a substantial load resistance element by, for example, connecting the gate of the MOSFETQ 12} to a ground point. In this case, since the level of the node _n1 is DC determined according to the level of the corresponding word line, the level that has been selected in advance and is to be discharged by the low level of the control signal φ is relatively short. Will be able to drop in time. Also in this case, since the gate of MOSFETQ ₁₂ is not coupled to the signal line to which the control signal φ is supplied, the signal line constitutes a relatively light capacitive load.

[Application field]

The above explanation mainly describes the invention made by the present inventor and the field of application that is its background.
Although the description has been made of an application to a micro ROM used in a CRT controller, the invention is not limited thereto. Dynamic lambdam access memory consists of two switch MOSFETs and a capacitor as an information storage means, and each memory cell consists of a pair of high-resistance load elements made of a polysilicon layer and a pair of gates and drains cross-coupled.
It can be applied to all IC memories such as static random access memories consisting of a MOSFET and a pair of transmission gate MOSFETs.

The invention is particularly useful in memories where word lines are constructed from materials with relatively high resistivity, such as polycide or polysilicon in embodiments, and therefore have relatively large signal delay times. .

[Brief explanation of the drawing]

FIGS. 1 and 2 are circuit configuration diagrams showing an example of the configuration of a word line drive circuit in a conventional IC memory, and FIG. 3 is a circuit configuration showing an example of applying the present invention to a micro ROM. Figure 4 is
The timing chart, FIG. 5 is a plan view showing one embodiment of the layout configuration of the word line auxiliary drive circuit according to the present invention, and FIGS. 6 and 7 are respectively viewed from A-A' in FIG. 8 is a circuit diagram showing another example of the structure of the auxiliary drive circuit. M-ARY...Memory array, WL ₁ to WLm...Word line, DL ₁ to DLn...Gator line, X-DEC...X decoder circuit, Y-DEC...Y decoder circuit, MLP
…Multiplexer circuit, WD ₁ to WDm…Word line driver, ADW ₁ to APWm…Auxiliary drive circuit,
M ₁₁ ~Mmn...Memory cell, Qy ₁ ~Qyn...Y switch, Qd ₁ ~Qdm...Discharge MOSFET,
Qp ₁ ~ Qp ₈ ... MOSFET for pre-charge, 1a ~ 1
d...gate electrode, 2a, 2c...common source region,
3a, 3c...Aluminum layer, 4a-4d...N-type diffusion layer, 5a-5d...Aluminum signal line, 6a-6d
... Polysilicon gate electrode, 7a-7d... P-type diffusion layer, 8a, 8c... Common drain region, 9a-9
d...Aluminum connection wire, 10...Aluminum signal line, 11~
19...Contact hole, 21a-21d...Aluminum layer, 22a-22d...P-type diffusion layer, 23
a, 23c... common source region, 24... polysilicon gate electrode, 25... power supply line.

Claims (1)

[Claims] 1. A word line is formed of the same material as the gate electrode, a data line perpendicular to the word line is formed of an aluminum layer, and the data line is connected between the word line and the data line. A memory consisting of one-element memory cells arranged in a matrix that stores information by selectively connecting MOSFET elements that are made conductive or non-conductive depending on the level of the In a semiconductor memory device in which an array is used as a micro ROM for storing a micro program, its output timing is controlled by a clock control signal, and a selection signal according to an address signal is supplied to the corresponding word line. Complementary MOSFET
an auxiliary drive circuit connected to the end of the word line on the opposite side of the memory array from the drive circuit; a discharge circuit coupled to a word line, and the driving circuit operates the word line when the clock control signal is at a high level, and operates the word line when the clock control signal is at a low level. The auxiliary drive circuit includes a first N-channel MOSFET whose source terminal is connected to a ground point of the circuit and whose gate terminal is connected to the word line;
The source terminal is connected to the power supply voltage of the circuit, and the drain terminal is the first N-channel type.
The first P connected to the drain terminal of the MOSFET
a second P-channel MOSFET whose source/drain path is connected between the word line and the clock control signal supplied to the gate terminal of the first P-channel MOSFET; The discharge circuit is a second N-channel type whose source terminal is connected to the grounding point of the circuit and whose drain terminal is connected to the word line.
MOSFET, and the opposite phase signal of the clock control signal is sent to the second N-channel MOSFET.
What is claimed is: 1. A semiconductor memory device characterized in that the voltage is supplied to a gate terminal of a semiconductor memory device.