JPS60242594A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce the power consumption and to make a latch-up state hard to occur by precharging only a selected data line from an output circuit side. CONSTITUTION:The multiplexer circuit MLP consisting of switch MOSFETs Qy1-Qyn connected to respective data lines DL1-DLn is provided at one side of a memory array M-ARY. The circuit MLP selects a proper number of data lines among data lines DL1-DLn on the basis of a select signal from an Y decoder circuit Y-DEC and supplies their output signals to output circuits DOB1- DOB8. Further, MOSFETs Qp1 and Qp3 for precharging are connected between output signal lines DOL1-DOL8 and a source voltage VCC, and a precharge signal phip turn on FETs Qp1-Qp8 at the same time. Therefore, one of the data lines DL1-DLn which is selected by the circuit Y-DEC is precharged. Thus, the power consumption is reduced and a latch-up state hardly occurs.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to semiconductor integrated circuit technology, and furthermore, to a technology that is particularly effective when applied to semiconductor storage devices. The present invention relates to a technique that is effective when used in the configuration of a precharge circuit for a data line of a ROM (read-only memory).

[Background technology] As a data reading method for a ROM made of MOSFETs (insulated gate field effect transistors), the data line (or bit line) is precharged, and then the word line is set to the selection level. There is a technique for configuring a low power consumption type ROM by extracting charge from a data line through a memory cell. In this way, R
As an example of the structure of OM, for example, Japanese Patent Application No. 57-21130
There are numbers etc.

The present inventor has developed the above-mentioned data line precharge method technology by
A device as shown in FIG. 1 was developed for use in a micro ROM used in a hard disk controller that constitutes a microcomputer system.

That is, one end of each data line DL1 to DLn arranged in memory array M-'ARY and power supply voltage Vcc
MO8FETQp for precharging connected between
1 to QPn are simultaneously turned on by a control signal (TJ charge signal) φp, and all data lines DL1 to DLn are simultaneously precharged to the Vcc level. Furthermore, in a micro ROM, it is necessary to read data (control words) consisting of 8 bits per word simultaneously (in parallel), but if you want to store a microprogram of 512 words, for example, you can use 8 data lines. The word line is 5
12 pieces are required. Therefore, memory array M-ARY
In this case, the memory array has a configuration of 512×8 bits, and becomes extremely elongated in the data line direction, making layout within the chip difficult.

Therefore, in the circuit shown in FIG. 1, there are 16 data lines, and each data line is connected to clocked inverters Nv1 to IN Vn consisting of 0MO8 (complementary MO3) circuits.
This is selectively operated using the upper bits of the address signal, thereby reducing the length of the memory array in the data line direction by half (however, the width in the word line direction is doubled).

However, in the micro ROM configured as described above, all data lines are precharged at the same time, so power consumption increases significantly as the number of data lines increases. In addition, the area occupied by the memory array and its peripheral circuits is determined by setting the pitch (spacing) of data lines to the minimum interval determined by the size of the memory cell, and also setting the Y-decoder circuit Y-DEC or Y-select circuit to the minimum interval determined by the size of the memory cell. The layout can be minimized. However, in the circuit shown in FIG. 1, since the Y-decoder circuit Y-DEC is composed of clocked inverters INV, ~INVn, the multiple MOSFETs constituting each clocked inverter are connected to each data with the minimum pitch. It is extremely difficult to design the circuit so that it is arranged in accordance with the line spacing, and the area occupied by the entire circuit increases.

Furthermore, when the memory cells in the memory array M-ARY are configured with N-channel MOSFETs, the diffusion layer N+ of the MOSFET serving as the storage element is formed on the main surface of the N-type semiconductor substrate SUB, as shown in FIG. It is formed on the formed P-type well region P-WELL. Therefore, if all the data lines are precharged at the same time as described above, the diffusion layer (drain region) N+ and P well region P- of the MOSFET that constitutes the memory cell connected to the data line DL. All of the parasitic junction capacitances Cs between WELL and WELL are charged up at the same time during precharging. As a result, it has been found that the potential of the P-well region P-WELL in which the memory cell is formed is greatly fluctuated through this junction capacitance Cs, which is disadvantageous in that latch-up is likely to occur.

[Object of the Invention] An object of the invention is to provide a low power consumption semiconductor memory device.

Another object of the present invention is to provide a technique that can reduce the area occupied by a semiconductor memory device.

Still another object of the present invention is to provide a precharge circuit type that is less likely to cause latch-up when a semiconductor memory device is configured with a 0M08 circuit.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows.

In other words, each data line arranged in the memory array is
By connecting to the output circuit side via a switch MO3FET which is controlled on and off by a selection signal from a decoder, and by connecting a MOSFET for precharging between the switch MO8FET and the output circuit, the selected By precharging only the precharged data lines from the output circuit side, power consumption is reduced, and the parasitic capacitance of memory cells connected to the precharged data lines is reduced to suppress potential fluctuations in the well region. , making latch-up less likely to occur.

In addition, it is possible to minimize the pitch of the data lines by arranging only one MOSFET between the data lines to connect them to the output circuit side, and to reduce the occupation of peripheral circuits.
The area is also reduced, thereby achieving the above objective of reducing the area occupied by the entire device.

[Embodiment] FIG. 3 shows one implementation in which the present invention is applied to a micro ROM used in a hard disk controller, CRT controller, and other peripheral LSIs that constitute a microcomputer system together with a microprocessor (hereinafter referred to as CPU). Give an example.

In hard disk controllers, CRT controllers, etc., in order to control each part of the hard disk driver, CRT display device, etc. to be controlled in more detail according to instructions from the CPU, a microprogram that executes such instructions is stored. A micro ROM is provided. Such a micro ROM needs to read out corresponding micro instructions as quickly as possible in response to instructions from the CPU, output control signals, and control each section. Therefore, it is desired that the micro ROM can be accessed at a high frequency such as IOMH2.

The ROM of the embodiment described below is characterized by being capable of such high-speed operation and occupying a small area.

In FIG. 3, the circuit symbol M-ARY indicates a memory array in which a plurality of memory cells M11 to Mmn are arranged in a matrix. In the memory cells M, 11 to Mmn constituting the memory array M-ARY, one MOSFET is provided corresponding to one bit of memory, and for example, a memory element (a MOSFET constituting a memory cell) is provided.
Depending on the presence or absence of a contact or diffusion layer in the drain part of the ET), current may or may not flow when the gate is set to the selection level, resulting in LL I I+ or 0'''
The information corresponding to the information is retained.

In the same figure, memory cells such as M and 19M1□ represent MOSFET circuit signals.

Indicates that there is a contact or a diffusion layer in the drain portion of the memory element. Furthermore, memory cells such as M21 and M2n in which MOSFET circuit signals are not displayed indicate those that do not have a contact or a diffusion layer in the drain portion of the memory element. In this embodiment, the memory cell is constituted by an N-channel MOSFET, although it is not particularly limited.

In the memory array M-ARY, each row of memory cells M1
1, Ml 2. ”°°−M1 n;'M'21
, M221 0-8M2 n ; -Mmx t M
Word lines WL, . ~WLm is formed integrally with the polysilicon gate electrode of the MOSFET constituting the memory cells of each row.In addition, the memory array M-
In ARY, memory cells Ml 1 + Ml in each column
2. ”””Ml n,”PJ21 + M22, “
b°M2 n ; NMml , Mm2 , □11Mmn
Data lines (or bit lines) DL, to DLn made of aluminum layers are arranged corresponding to the lines.

Further, in the memory array M-ARY, ground lines GL1 to GLi are provided to which the source regions of the MOSFETs constituting the memory cells in each row are commonly connected. These ground lines GL1 to GLi are constituted by a diffusion layer formed continuously with the source region of each storage element, although not particularly limited thereto.

Further, the ground lines GL, -GLi are formed every other memory row, and are connected so that adjacent memory rows share one ground line GL1. The ground lines GL1 to GLi are connected to a common ground line CGL made of an aluminum layer on one side of the memory array M-ARY, and are supplied with the battery potential GND.

The circuit designated by the circuit code X-DEC is an
This is a decoder circuit. Each word line WL is controlled by this X decoder circuit X-DEC.

~Word line driver W provided corresponding to WLm
One of DI to WDm is driven to raise one word line to a high level.

The word line drivers WD1 to WDm are configured, for example, by clocked inverters, and are operated in synchronization with a control signal φ such as a system clock signal. Although not particularly limited, in this embodiment, the X-decoder circuit X-DEC is also composed of a dynamic type circuit that operates in synchronization with the control signal φ, and the X-decoder circuit X-DEC operates in synchronization with the row selection signal. During the half period of the control signal φ forming the word line drivers WD, ~WD
Precharge m. Then, in the next half cycle of the control signal φ, the word line drivers WD1 to WDm are driven to select one word line.

The X decoder circuit X-DEC is precharged. In this way, the X decoder circuit X-D
EC and word line drivers WD1 to WDm receive control signals (
Power consumption is reduced by operating in synchronization with the clock) φ.

On one side of the memory array M-ARY, each data line D
N-channel type switch MO8FET (hereinafter referred to as Y switch) Qy connected to L and ~DLn respectively
A multiplexer circuit MLP consisting of circuits 1 to Qyn is provided. The multiplexer circuit MLP is a Y-decoder circuit Y-DEC that decodes the upper bits of the address signal.
Based on the selection signal from n data lines DL1 to D
An appropriate number of data lines are selected from Ln and their output signals are supplied to an output circuit DOB consisting of a CMOS inverter.

Specifically, although not particularly limited, in order to be able to read a control word consisting of 8-bit data from the micro ROM at once, there are 32
Eight data lines are arranged, and eight of them are output signal lines DOL1 to DOL1 by the multiplexer circuit MLP.
DOL. In other words, 32 Y switches Q
y1 to QY32 are grouped in groups of four and connected to one output signal line DOL, and in each Y switch group, one of them is turned on by the selection signal from the Y decoder circuit Y-DEC, and the four One of the data lines is connected to the output signal lines DOL1 to DOL8, respectively.

Output circuits DOB1 to DOB8, each including a CMOS inverter, are connected to each output signal line DOLi to DOL8. Moreover, between each output signal line DOL1 to DOL8 and the power supply voltage Vcc, MO8FET for precharging is connected.
QPz to QPa are connected so that the same precharge signal φp is applied to their gate terminals.

In this way, the structure of having 32 data lines and selecting 8 of them with a multiplexer is the reason for the micro RO.
In M, for example, a control word consisting of 8 bits per word is 51
If you want to store 2 words, connect the data line to 8.
In the case of a book, a memory array must be constructed by arranging memory cells of 8 bits in the word line direction and 512 bits in the data line direction. However, in this case, the memory array becomes extremely elongated in the data line direction, making layout within the chip difficult. Therefore, in the above embodiment, a control word of 512 words is stored in a micro ROM having a 128x32 bit configuration.

The precharge signal φP is applied to the word line driver WD,
~ Before any one word line is raised to high level by WDm, the upper two bits A of the address signal
A selection signal from the Y-decoder circuit Y-DEC that decodes signals 7 and A8 changes from high level to low level with a total of 8 Y switches turned on, one from each Y switch group. Then, the precharge signal φP causes the MOS FET QP 1 to Qp
a are turned on at the same time, and the output signal lines DOL, ~Do
Through the Y switch Qy turned on by the selection signal from L8 and the Y decoder circuit Y-DEC, eight data lines connected thereto are precharged.

At this time, the output signal lines DOL, ~DOL8 are precharged to the Vcc level, but the data line has a potential lower than Vcc by the threshold voltage of the Y switch Qy (Vc
c-Vth).

When the precharging of the data line is completed as described above, the precharge signal φP is changed to a high level and the precharge MOS FETQ'p1 to Qp8 are turned off. Then, with the eight Y switches Qy kept turned on by the selection signal from the Y-decoder circuit Y-DEC, one word line is raised to a high level by the word line drivers WD, -WDm. As a result, a MOS as a storage element is placed at the intersection of one word line WL set to the selection level and the data line DL connected to the eight Y switches turned on.
If the FET is connected, the MOSFET is turned on and the charge on the data line is extracted to the ground line GL.

On the other hand, if no storage element is connected to the intersection of the selected word line and data line, the charge from the data line is not extracted.

As a result, the selected data line DL is set to either the precharge level or the ground potential. The potential of this data line is a Y switch. Output circuit (inverter) DOBI~D via y.

Since it is supplied to B8, the output circuits DOB1-D.

A signal corresponding to the potential of the data line is output from i8 as read data D o "" D7.

According to the above embodiment, in response to the selection signal from the Y-decoder circuit Y-DEC, only the data lines connected to the turned-on Y switch are supplied from the output circuits DOB1 to DOB8 through the turned-on Y switch Q7. Charging is performed. Therefore, compared to the circuit shown in FIG. 1 in which all data lines are precharged, power consumption is lower.

Further, according to the above embodiment, the selected data line has a threshold voltage Vth of the Y switch Qy that is lower than the power supply voltage Vcc.
Therefore, when the MOSFET as a storage element is turned on by the high level of the word line and the charge of the data line flows to the ground side, the potential of the data line falls quickly. As a result, there is an advantage that access time is shortened.

Moreover, even if the precharge level of the data line drops to Vcc-Vth as described above, the output signal line DOL connecting between the Y switch Qy and the output circuit DOB is
It is precharged to the Vcc level by the precharge MO8FETQp. Therefore, the output circuit DOB
Even if it is configured with an inverter or the like, no through current will flow. That is, when the output circuit DOB is configured with an inverter, if the output signal line DOL is set to a level lower than the power supply voltage Vcc during data line precharging, a through current will flow through the output circuit DOB consisting of the inverter. On the other hand, in the above embodiment, the output signal line DOL is V
Since it is completely precharged to the cc level, no through current flows through the output circuit.

Further, according to the above embodiment, since it is sufficient to arrange the Y switch rows each consisting of one MOSFET on one side of the memory array M-ARY, there is no unreasonable layout, and the Y switch rows can be easily arranged within the spacing between the data lines. can be placed. In other words, in the circuit format shown in Figure 1, a clocked inverter consisting of, for example, four MOSFETs must be provided for each data line interval, which makes layout design difficult, and the data line pitch has to be determined by adjusting the data line pitch between memory cells. It is difficult to achieve the minimum spacing determined by the size of the On the other hand, according to the above embodiment, it is sufficient to arrange one MO8FET between each data line with the minimum pitch, so the layout design is easy and the area occupied by the entire circuit can be reduced.

Furthermore, according to the above embodiment, since the number of data lines to be precharged is small, the MOS forming each memory cell
The parasitic junction capacitances between the drain region of the FET and the P-well region are also not all charged up at the same time. Therefore, the ratio of the parasitic capacitance between the P-well region and the memory cell to the junction capacitance existing between the P-well region and the substrate becomes substantially small. As a result, even if the parasitic capacitance between the P well region and the memory cell is charged up during precharging, the variation in the well potential is reduced, making latch-up less likely to occur.

Further, in the embodiment, the output signal lines DOL1 to DOL8
The output circuits DOB1 to DOB8 connected to the memory array amplify and output the signals read out from the memory array, but once the readout signal is received by a clocked inverter, it is processed by a CMOS inverter as in the embodiment. Output circuit D
It may be configured so that it is sent to OBI~D0B8 and output. Since the precharge MOSFET is connected between the switch MO3FET and the output circuit, only the selected data line is connected to the output circuit side via the switch MO3FET. Due to the effect of precharging,
This has the effect of reducing power consumption.

(2) Each data line arranged in the memory array is connected to the output circuit side via the switch MO8FET, which is controlled on and off by the selection signal from the decoder, and the switch MO3FET and the output circuit are connected to each other. Since the MO3FJT for precharging is connected in between, the number of data lines to be precharged is reduced, and the total parasitic capacitance of the memory cells connected to this is reduced, thereby suppressing potential fluctuations in the well region. This has the effect of making latch-up less likely to occur.

(3) Each data line arranged in the memory array is connected to the output circuit side via a switch MO8FET that is controlled on and off by a selection signal from a decoder, and the switch MO8FET and the output circuit are connected to each other. Since a MOSFET for precharging is connected between the data lines, only one MOSFET needs to be placed between the data lines to connect it to the output circuit side, which minimizes the pitch of the data lines. In addition, the area occupied by the peripheral circuits is also reduced, which has the effect of reducing the area occupied by the entire device.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above example,
Although the MOSFET constituting the memory cell is formed as an N-channel type, it is also possible to form it as a P-channel type and to select by setting the word line to a low level at the time of selection.

[Field of Application] In the above explanation, the invention made by the present inventor was mainly applied to the field of application which is the background of the invention, which is a micro ROM used in hard disk controllers, etc., but the present invention is not limited thereto. Not, but
It can also be used as a ROM or the like as a standalone (IC memory).

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing an example of the configuration of a micro ROM, FIG. 2 is a cross-sectional explanatory diagram of the main part of the memory array section, and FIG. 3 is an embodiment in which the present invention is applied to a micro ROM. FIG. 2 is a circuit configuration diagram showing an example. M-ARY...Memory array, WL1~WLm...
...Selection line (word line) -DL1 to DLn...Signal line (data line)'-X-DEC...X decoder circuit, Y-DEC...Y decoder circuit, MLP...・
Multiplexer, WD1 to WDm” word line driver,
Mti~Mmn...Memory cell, Qy1~Qy
n°゛°゛Y switch゛Qps~Qpa...MO3FET for precharging. Figure 1 Figure 2 Figure h Nogosu B

Claims (1)

[Claims] 1. In a semiconductor memory device comprising a memory array in which storage elements are arranged at the intersections of a plurality of selection lines and signal lines arranged in mutually orthogonal directions within the memory array. ,
A switch MO3FET controlled by a selection signal formed based on an address signal is connected to one end of the signal line, and the signal lines, which have been divided into several groups in advance, are connected to the corresponding selectively connected to the output circuit side, and the switch M
MOS for precharging between O8FET and output circuit
A semiconductor memory device characterized by being provided with a FET. 2. The memory element includes a MOSFET selectively connected between the selection line and the signal line, the output circuit includes an inverter, and the memory array includes:
2. The semiconductor storage device according to claim 1, wherein the semiconductor storage device stores a microprogram and is used as a micro ROM.