JPS63276793A - Word line driving circuit - Google Patents

Abstract

PURPOSE:To speed up the trailing time of a word line even if the word line is extended by providing a word line driving circuit consisting of odd number stages of inverters, a two-input NOR circuit, and an N-type transistor on the end of the word line. CONSTITUTION:The X-decoder 101 of a word line delay short circuit 104 decodes an address signal, and a resulting signal in H-level is inputted to the input 16 of the two-input NOR circuit 12 and a resulting signal in L-level is inputted to the input 17 of the same 12 during a time when the terminal 7 of the word line 2 is in H-status, accordingly, the output 18 of the NOR circuit 12 goes to L-level, and the N-type transistor Tr 11 is turned off. Thereafter, when the terminal 7 starts to shift from the H-status to the L-status, the input 16 goes to L-status, the signal 18 remains as an H-level pulse until an H-level signal is inputted to the input 17 because of the three-staged delay by the inverters 15-13, hence the Tr 11 turns on so that a current flows to the GND. In such a way, the trailing of the voltage of the line 2 is complemented to be shortcircuited.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a read-only semiconductor memory word line drive circuit.

[Conventional technology]

An example of a conventional word line drive circuit is shown in FIG.

In FIG. 4, an X decoder 201 receives an address signal, and the signal resulting from decoding the address signal is input to the tip 19 of the word line 20 of the cell section 200. Each cell in the cell unit 200 is driven by this signal to perform on/off operations, and the data sense circuit 202 detects the current difference.
Output circuit 203 outputs the result.

N-type transistors 21, 22゜23, which constitute the cell.
- 24 can be turned on or off in response to the same drive signal depending on whether it is an enhancement type or a depletion type. The word line 20 is equivalent to having resistance and stray capacitance distributed along its extension direction, and the output of the will be transmitted up to.

[Problem that the invention seeks to solve]

In the conventional word line drive circuit data sense described above, the data sense circuit 202 detects the on/off current of the cell, so the sense level for the signal from the X decoder 201 is near the cell threshold voltage value V75. becomes. Therefore, the delay of the word line that affects the access time is determined by the time DEL1 required for the voltage to change from the power supply voltage to the threshold voltage value V75 as shown in FIG. As the word line length becomes longer, the time required for the voltage to change from the power supply voltage to the threshold voltage value V75 becomes longer, resulting in a problem that the ROM access time becomes longer.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a word line drive circuit that can speed up the fall of a word line and shorten ROM access time.

[Means for solving problems]

The circuit of the present invention is a word line drive circuit that supplies a signal resulting from the decoding of an address signal to a read-only memory cell via a word line to turn the cell on and off. an inverter, a 2-input NOR circuit whose inputs are the output of the final stage of the inverter and the end of the word line, and an N-type transistor whose gate, drain, and source are connected to the output, end, and ground potential of the 2-input NOR circuit, respectively. It is characterized by having the following.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

1 and 2 are one embodiment of the present invention.

This embodiment includes an
．． A cell section 100 including 5...6 cells, a data sense circuit 102 that detects on/off currents of cells in the cell section 100, and receives a detection signal from the data sense circuit 102 and outputs the result. It is composed of an output circuit 103 and a word line delay shortening circuit 104 connected to the end 7 of the word line 2 in the cell section 100.

The N-type transistors 3, 4, 5, . . . , 6 constituting the cell are turned on or off in response to the same drive signal depending on whether they are of an enhancement type or a depletion type. These N-type transistors 3.4.5...6
is also the N-type transistor 21,22 shown in FIG.
．． 23...24, and the sense level for the signal from the X decoder 101 is determined by the data sense circuit 10.
The threshold voltage value V74 is almost the same as the sense level 2.

FIG. 2 shows an equivalent circuit of the cell section 100 receiving the signal from the X decoder 101 of the first section and details of the word line delay shortening circuit 104.

The word line delay shortening circuit 104 includes inverters 15, 14 and 13 connected in three stages from the end 7 of the word line 2, an N-type transistor 11 whose drain is connected to the end 7 of the word line 2, and a gate of the N-type transistor 11. and an output signal 18, one input signal 16 is connected to the end 7 of the word line 2, and the other input signal 17 is connected to the output signal of the inverter 13.
It consists of

The X decoder 101 decodes the address signal and uses the resulting signal as a drive signal to operate the 2-input NOR circuit 1 when the end 7 of the selected word line 2 of the word line 2 is in the "H" state.
2, H'' is input to the input 16 and "L" is input to the input 17, the output 18 becomes °L''', and the N-type transistor 11 is turned off.

Next, when the terminal 7 starts to change from the "H" state to the "L" state, the input 16 of the two-input NOR circuit 12 becomes ``L'''', and due to the three-stage delay caused by the inverters 15, 14 and 13, the input 17 becomes """. Input signal 18 until H” is input.
becomes an "H" pulse shown in FIG. 3, the N-type transistor 11 is turned on, and current flows into GND.

This assists and shortens the voltage fall of the word line 2.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, even if the word line length increases as the cell capacity increases, the word line can fall more quickly, which is the first characteristic of ROM. Access time can be shortened.

[Brief explanation of the drawing]

1 and 2 show an embodiment of the present invention, FIG. 3 shows a waveform diagram of this embodiment, FIG. 4 shows a conventional example, and FIG. 5 shows a waveform diagram of a conventional example. 2.20...word line, 3.4, 5, 6°21.
22, 23.24.11...N-type transistor, 12
...2-input NOR circuit, 13, 14.15... Inverter, 1, 19... Tip, 7, 25... End, 1
00.200...Cell part, 101,201...X decoder, 102.202...Data sense circuit, 10
3,203...Output circuit, 104...Word line delay shortening circuit. 7kei agent patent attorney Susumu Uchihara (1,'kl

Claims (1)

[Scope of Claims] A word line drive circuit that turns on and off a read-only memory cell by supplying a signal resulting from decoding an address signal to a read-only memory cell via a word line, wherein the terminal of the word line is an odd-numbered input circuit. a 2-input NOR circuit whose gate, drain, and source are each connected to the 2-input NOR circuit whose inputs are the output of the final stage of the inverter and the terminal end of the inverter;
1. A word line drive circuit comprising: an output of the circuit, the terminal, and an N-type transistor connected to a ground potential.