JP2509023B2 - Decoder circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoder circuit of an erasable programmable read-only semiconductor memory device capable of erasing data.

[0002]

2. Description of the Related Art An eraseable programmable read only semiconductor memory device (hereinafter referred to as E
In the case of PROM), 20
It is known to use a high voltage V _{P of the} order of V. That is, programming is performed by applying the high voltage V _P to the memory cell, while the normal voltage V _C of 5 V is used when reading data from the memory cell. Therefore, in order to selectively program or read data to a plurality of memory cells, the high voltage V _P or the normal voltage V _C is switched and supplied as a power supply voltage to the decoder that selects the memory cells. There is a need.

FIG. 1 is a circuit diagram of a conventional voltage switching circuit 10 for switching and outputting both of the above voltages. The terminal 11 in FIG. 1 is a voltage terminal to which the high voltage V _P is supplied when data is programmed, and the terminal 12 is a voltage terminal to which the voltage V _C is supplied when data is read. An end of the enhancement type MOS transistor 13 between the source and the drain and a gate are connected to the voltage terminal 11, and the other end between the source and the drain is connected to the voltage output terminal 14. One end between the source and the drain of the depletion type MOS transistor 15 is connected to the voltage terminal 12, and the other end between the source and the drain is the voltage output terminal.
The control signal R // P, which is set to "1" at the time of reading data and "0" at the time of programming, is supplied to the gate of the MOS transistor 15. Both MOS transistors 13 and 15 are N
Of the channel.

In the voltage switching circuit 10, the control signal R // P is set to "0" during programming, and the transistor 15
Is turned off and the high voltage V supplied to the voltage terminal 11
_P is output from the voltage output terminal 14 via the transistor 13. On the other hand, at the time of reading data, the control signal R // P is set to “1”, the transistor 15 is turned on, and the voltage V _C supplied to the voltage terminal 12 is supplied from the voltage output terminal 14 via the transistor 15. Is output.

FIG. 2 shows a conventional address decoding circuit for selecting a memory cell for programming or reading data by using the voltage switched and output from the voltage switching circuit 10. In the figure, 20 is an address decoding unit,
A buffer circuit 30 buffer-amplifies the output signal of the address decoding unit 20.

The address decoding unit 20 includes a load P channel MOS between a voltage terminal 21 and an output terminal 22 to which the voltage V _P or V _C output from the voltage output terminal 14 of the voltage switching circuit 10 is supplied. A transistor 23 is inserted, and a plurality of N-channel MOS transistors 24 for decoding are inserted in series between the output terminal 22 and the ground. The gate of the load MOS transistor 23 is connected to the ground, and a plurality of N-channel MO for decoding is connected.
An address signal is input to each gate of the S transistor 24.

The buffer circuit 30 has a P-channel MOS transistor 33 inserted between the output terminal 32 and the voltage terminal 31 to which the voltage V _P or V _C output from the voltage output terminal 14 of the voltage switching circuit 10 is supplied. In addition, an N-channel MOS transistor 34 is inserted between the output terminal 32 and the ground. The signal of the output terminal 22 of the address decoding section 20 is input to the gates of the P-channel and N-channel MOS transistors 33 and 34.

In the address decoding circuit, when data is programmed, the high voltage V _P is output only from the output terminal 32 of the buffer circuit 30 selected according to the input address, and the row of the memory cell to which this voltage corresponds. Supplied to the wire. When reading data, the read voltage V _C is output only from the output terminal 32 of the buffer circuit 30 selected according to the input address, and this voltage is supplied to the row line of the corresponding memory cell. .

[0009]

In such a decoder circuit, a load MO in the address decoding unit 20 is used.
Since the gate of the S transistor 23 is fixed to the ground voltage, that is, 0V, this MO
The high voltage V _P is applied between the source of the S transistor 23, that is, the voltage terminal 21 side and the gate. Therefore, at this time, a large current flows between the source and drain of the MOS transistor 23, resulting in a large consumption current of the high voltage V _P. Furthermore, such a high voltage V _P is used by an external power source. However, the current capacity is small in the case where it is formed by a means such as boosting the reading voltage V _C without doing so,
The increase in current consumption is a problem. Therefore, in order to reduce this current, the channel length of the MOS transistor 23 must be lengthened. Then, the element size of the MOS transistor 23 becomes large, and the area occupied by the address decoding section 20 increases when integrated into a circuit.

If the channel length of the MOS transistor 23 is increased to make it difficult for the current to flow, the charging speed at the time of charging the output terminal 22 becomes slow, and both the P-channel and N-channel MOS transistors in the buffer circuit 30. 33, 34
The period in which both are on increases. At this time, since V _P is supplied to the buffer circuit 30 as a power supply voltage, an excessive current flows in the buffer circuit 30 and the CMOS
This is not preferable because it causes a latch-up phenomenon peculiar to the configuration.

Further, if the channel length of the MOS transistor 23 is increased to make it difficult for current to flow, the charging speed at the time of charging the output terminal 22 at the time of reading data also becomes slow, and the speed of reading data becomes slow. is there.

The present invention has been made in consideration of the above circumstances, and an object thereof is to reduce the consumption of current when programming data and to prevent the reading speed from decreasing when reading data. It is to provide a circuit.

[0013]

In order to achieve the above object, according to the present invention, when a programming voltage used when performing data programming is output from a voltage switching circuit by switching output, the voltage is changed. By delaying the rising edge of, the potential difference between the voltage at the output terminal of the address decoding circuit that uses this programming voltage as a power supply and the programming voltage is reduced, thereby preventing an excessive current from flowing to the buffer circuit. There is. Further, since there is no delay in switching and outputting the normal voltage from the voltage switching circuit, the reduction of the data reading speed is prevented.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIGS. 3 and 4 are circuit diagrams showing the structure of the decoder circuit according to the present invention. FIG. 1 is a voltage switching circuit, and FIG. 4 is an output voltage of the voltage switching circuit. Address decoding circuits are shown respectively.

The voltage switching circuit 10 shown in FIG. 3 differs from the conventional one shown in FIG. 1 in that the gate of the MOS transistor 13 is not connected to the voltage terminal 11, but is connected to the output terminal 41 of the inverter 40. The point is that they are connected. The inverter 40 includes a load depletion type MOS transistor 43 inserted between a voltage terminal 42 supplied with a high voltage V _P and an output terminal 41, and a drive inserted between the output terminal 41 and ground. And an enhancement-type MOS transistor 44 for And
The gate of the MOS transistor 44 is supplied with a control signal R // P which is set to "1" at the time of reading data and "0" at the time of programming. Further, a capacitor 45 is inserted between the output terminal 41 of the inverter 40 and the ground.

The address decoding circuit shown in FIG. 4 is different from the conventional one shown in FIG. 2 in that an output terminal 22 of the address decoding section 20 and a voltage terminal 16 to which a normal read voltage V _C is supplied. The point is that a load circuit 50 is newly inserted between the two.

This load circuit 50 is an enhancement type P-channel MOS transistor inserted in series between the voltage terminal 16 and the output terminal 22 of the address decoding section 20.
51 and a depletion type N-channel MOS transistor 52. The gate of the MOS transistor 51 has a control signal / R / set to "0" when reading data and "1" when programming.
P is supplied, and the control signal R // P is supplied to the gate of the MOS transistor 52.

In such a configuration, R // P is set to "0" when programming data. Thus, as shown in FIG 3
The MOS transistor 44 in the inverter 40 of the circuit is turned off. When the MOS transistor 44 is turned off, the output terminal 41 of the inverter 40 is charged with a time constant according to the impedance of the load MOS transistor 43 and the value of the capacitance 45. For this reason, the MOS transistor 13 controlled by the voltage of the output terminal 41 does not suddenly turn on as in the conventional case, but sequentially shifts from the off state to the on state. High voltage V
The rising of _P is made gentle. In the address decoding unit 20 of the circuit of FIG. 4 to which the voltage V _P of the voltage output terminal 14 is supplied as a power source, the rising speed of the voltage of the output terminal 22 becomes slow, so that the channel width of the MOS transistor 23 is reduced and the current is reduced. Even if the supply capacity is reduced,
The terminal 22 is charged by the MOS transistor 23 by charging
Can sufficiently follow the voltage rise. At this time, the buffer circuit
The power supply voltage supplied to the terminal 31 of 30 is similar to the voltage rise of the terminal 22, and the potential difference between the terminal 22 and the terminal 31 changes in a substantially constant state.

Therefore, unlike the conventional case, an excessive current does not flow in the buffer circuit 30, and the channel width of the load MOS transistor 23 can be made small, and the current consumption can be greatly reduced. In addition, the prevention of the latch-up phenomenon in the buffer circuit 30 is also achieved.

At this time, the MOS transistor 51 in the load circuit 50 is turned off by the control signal / R / P set to "1", and the depletion type M
The control signal R // P set to “0” is supplied to the gate of the OS transistor 52. Therefore, even if the output terminal 22 of the address decoding unit 20 is set to V _P , the MOS
The potential at the connection point between the transistors 51 and 52 is set to the absolute value of the threshold voltage of the MOS transistor 52, which is at most about 3V, which is lower than V _{C of} 5V. Current is prevented from flowing from the voltage V _P to V _C.

On the other hand, when reading data, the control signal R
// P becomes "1", / R / P becomes "0", and load circuit 50
The MOS transistor 51 therein is turned on, and the terminal 22 is charged to the voltage V _C via the MOS transistors 51 and 52. For this reason, the charging speed of the terminal 22 can be made faster than in the case of using the MOS transistor 23 alone.
It is possible to speed up the selection operation of the memory cell connected to the output terminal 32 of 30.

[0023]

As described above, according to the present invention,
It is possible to provide a decoder circuit in which current consumption can be reduced when programming data and the reading speed is not reduced when reading data.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a voltage switching circuit in a conventional decoder circuit.

FIG. 2 is a circuit diagram showing a configuration of an address decode circuit in a conventional decoder circuit.

FIG. 3 is a circuit diagram showing a configuration of a voltage switching circuit in the decoder circuit of the present invention .

FIG. 4 is a circuit diagram showing a configuration of an address decode circuit in the decoder circuit of the present invention .

[Explanation of symbols]

10 ... Voltage switching circuit, 11 ... Voltage terminal, 12 ... Voltage terminal, 13 ...
MOS transistor, 14 ... Voltage output terminal, 15 ... MOS transistor, 20 ... Address decoding unit, 21 ... Voltage terminal,
22 ... Output terminal, 23 ... P-channel MOS transistor, 24
... N-channel MOS transistor, 30 ... Buffer circuit,
31 ... Voltage terminal, 32 ... Output terminal, 33 ... P-channel MOS transistor, 34 ... N-channel MOS transistor, 40 ...
Inverter, 41 ... Output terminal, 42 ... Voltage terminal, 43 ... Depletion type MOS transistor, 44 ... Enhancement type MOS transistor.

Claims (1)

(57) [Claims] 1. A non-volatile semiconductor memory device having non-volatile memory cells, comprising: a first voltage terminal to which a first voltage used when performing data programming of the memory cells is supplied; A second voltage terminal to which a second voltage used when reading data from the cell is supplied and a voltage supplied to the first and second voltage terminals are switched and output based on a control signal. When outputting the voltage of 1, the voltage switching circuit that delays the rise of the voltage and the load M
Same as OS transistor and this load MOS transistor
Connected to the column and no current flows when programming data
Negative control, which is used when reading data.
A load circuit and a plurality of decoding MOS transistors to which an address signal is input, and an output voltage from the voltage switching circuit is supplied to the load MOS transistor as a power supply voltage; and an address decoding circuit from the voltage switching circuit. A buffer circuit that operates between the output signal of the memory cell and the reference potential and that amplifies the output signal of the address decoding circuit and outputs the amplified signal as a signal for selecting the memory cell. When the voltage is output, the output of the address decoding circuit is output while the difference between the voltage of the output signal of the address decoding circuit and the output voltage of the voltage switching circuit supplied to the buffer circuit is substantially constant. The voltage of the signal and the output voltage from the voltage switching circuit supplied to the buffer circuit are controlled to increase, and Decoder circuit, characterized in that from the first voltage in Ffa circuit is configured to prevent current from flowing to the reference potential.