JPH0245278B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a decoder circuit for an erasable programmable read-only semiconductor memory device in which data can be erased.

[Technical Background of the Invention] Erasable programmable read-only semiconductor memory devices (hereinafter referred to as
EPROM) is known to use a high voltage V _P of about 20V when programming data. That is, programming is performed by applying this high voltage V _P to the memory cell. On the other hand, when reading data from memory cells, the normal
A voltage V _C of 5V is used. Therefore, in order to selectively program or read data to multiple memory cells, the high voltage V _P or the normal voltage V _C must be switched and supplied as the power supply voltage to the decoder that selects the memory cells. There is a need to.

FIG. 3 is a circuit diagram of a conventional voltage switching circuit 10 that switches and outputs the above-mentioned two voltages. Terminal 11 in FIG. 3 is a voltage terminal to which the high voltage V _P is supplied when programming data, and terminal 12 is a voltage terminal to which the voltage V _C is supplied when reading data. One end between the source and drain and the gate of an enhancement type MOS transistor 13 are connected to the voltage terminal 11, and the other end between the source and drain is connected to the voltage output terminal 14. One end between the source and drain of a depletion type MOS transistor 15 is connected to the voltage terminal 12.
The other end between the drains is connected to the voltage output terminal 14, and the gate of this MOS transistor is supplied with a control signal R/ which is set to "1" when reading data and to "0" when programming. be done. Note that both of the above MOS transistors 13,
15 are both of N channel.

In this voltage switching circuit 10, during programming, the control signal R/ is set to "0", the transistor 15 is turned off, and the high voltage V _P supplied to the voltage terminal 11 is passed through the transistor 13 to the voltage output terminal. It is output from 14. On the other hand, when reading data, the control signal R/ is set to "1", the transistor 15 is turned on, and the voltage terminal 1 is turned on.
The voltage V _C supplied to the transistor 2 is outputted from the voltage output terminal 14 via the transistor 13 .

FIG. 4 shows a conventional address decoding circuit that uses the voltages switched and output from the voltage switching circuit 10 to select a memory cell for programming or reading data. In the figure, 20 is an address decoding section, and 30 is a buffer circuit that buffers and amplifies the output signal of this address decoding section 20.

The address decoding section 20 is the voltage switching circuit 1
A P-channel MOS transistor 23 for load is inserted between the output terminal 22 and the voltage terminal 21 to which the voltage V _P or V _C output from the voltage output terminal 14 of 0 is supplied, and the output terminal 22 is connected to the ground. A plurality of N-channel MOS transistors 24 for decoding are inserted in series between them.
The gate of the load MOS transistor 23 is connected to ground, and an address signal is input to each gate of a plurality of decoding N-channel MOS transistors 24.

The buffer circuit 30 is connected to the voltage V _P output from the voltage output terminal 14 of the voltage switching circuit 10 or
A P channel MOS transistor 33 is inserted between a voltage terminal 31 to which V _C is supplied and an output terminal 32, and an N channel MOS transistor 34 is inserted between the output terminal 32 and ground. And the above P channel and N channel
A signal from the output terminal 22 of the address decoding section 20 is input to the gates of the MOS transistors 33 and 34.

In this address decoding circuit, when programming data, a high voltage V _P is output only from the output terminal 32 of the buffer circuit 30 selected according to the input address, and this voltage is supplied to the row line of the corresponding memory cell. be done. Similarly, when reading data, the read voltage V _C is output only from the output terminal 32 of the buffer circuit 30 selected according to the input address, and this voltage is supplied to the row line of the corresponding memory cell. Ru.

[Problems with the Background Art] In such a decoder circuit, the load MOS transistor 23 in the address decoding section 20
Since the gate of the MOS transistor 23 is fixed at the ground voltage, that is, 0V, a high voltage V _P is applied between the source, that is, the voltage terminal 21 side, and the gate of this MOS transistor 23 during data programming. Therefore, at this time, a large current flows between the source and drain of this MOS transistor 23, resulting in a high voltage.
The current consumption of V _P becomes large. Furthermore, if such a high voltage V _P is generated by boosting the normal voltage V _C without using an external power supply, the current capacity is small and the current becomes large, which is a problem. be. Therefore, in order to reduce this current, the channel length of the MOS transistor 23 must be increased. This increases the element size of the transistor 23 and increases the area occupied by the address decoding section 20 when it is integrated into an integrated circuit. Also, MOS transistor 2
If the channel length of 3 is made longer to make it difficult for current to flow, the charging speed when charging the output terminal 22 will be slowed down, and the P channel and N channel in the buffer circuit 30 will be
The period during which both MOS transistors 33 and 34 of the channel are both in the on state increases. At this time, since V _P is supplied to the buffer circuit 30 as the power supply voltage, an excessive current flows through the buffer circuit 30, which causes a latch-up phenomenon peculiar to the CMOS structure, which is undesirable.

Furthermore, if the channel length of the MOS transistor 23 is increased to make it difficult for current to flow, there is a drawback that the speed at which the output terminal 23 is charged is slowed down even when reading data, and the speed at which data is read out is slowed down.

[Object of the invention] This invention was made in consideration of the above-mentioned circumstances, and its purpose is to reduce current consumption when programming data, and to avoid slowing down the reading speed when reading data. The object of the present invention is to provide a decoder circuit.

[Summary of the invention] In order to achieve the above object, this invention has the following features:
When switching and outputting the programming voltage used for data programming from the voltage switching circuit, the voltage at the output terminal of the address decoding circuit that uses this programming voltage as a power supply is delayed by delaying the rise of the voltage. The potential difference between the program voltage and the programming voltage is made small, thereby preventing excessive current from flowing through the buffer circuit. Further, since there is no delay when switching and outputting the normal voltage from the voltage switching circuit, a decrease in data read speed is prevented.

[Embodiment of the Invention] An embodiment of the invention will be described below with reference to the drawings.

1 and 2 are circuit diagrams showing the configuration of a decoder circuit according to the present invention, in which FIG. 1 shows a voltage switching circuit 10, and FIG. 2 shows an output voltage of the voltage switching circuit 10 as a power source. The supplied address decoding circuits are shown respectively.

The voltage switching circuit 10 shown in FIG. 1 is different from the conventional one shown in FIG. This is what we did. The above inverter 40
is a depletion type MOS transistor 43 for load inserted between the voltage terminal 42 to which the high voltage V _P is supplied and the output terminal 41, and the output terminal 41.
and a drive enhancement type MOS transistor 44 inserted between the gate and the ground, and the control signal R/ is supplied to the gate of the MOS transistor 44. Furthermore, there is a capacitance of 4 between the output terminal 41 of the inverter 40 and the ground.
5 has been inserted.

The difference between the address decoding circuit shown in FIG. 2 and the conventional one shown in FIG. 4 is that the output terminal 22 of the address decoding section 20
This is because a new load circuit 50 is inserted between the voltage terminal 16 to which V _C is supplied. This load circuit 5
0 is the voltage terminal 16 and the address decoding section 20
An enhancement type P-channel MOS transistor 5 inserted in series between the output terminal 22 of the
1 and a depletion type N-channel MOS transistor 52. The gate of the transistor 51 is supplied with a control signal /P that is set to "0" when reading data and is set to "1" when programming, and the gate of the transistor 52 is supplied with the control signal R/. .

In such a configuration, the control signal R/ is set to "0" when programming data. As a result, the MOS transistor 44 in the inverter 40 of the circuit of FIG. 1 is turned off. When the transistor 44 is turned off, its output terminal 41 is charged with a time constant depending on the impedance of the load MOS transistor 43 and the value of the capacitor 45. Therefore, the MOS controlled by the voltage of the output terminal 41 is
The transistor 13 does not suddenly turn on as in the conventional case, but gradually transitions from the off state to the on state. Therefore, the rise of the high voltage V _P output from the voltage output terminal 14 is made gentle. In the address decoding section 20 of the circuit shown in FIG. 2, to which the voltage V _P of the voltage output terminal 14 is supplied as a power supply, the rate of rise of the voltage of the output terminal 22 becomes slow, so the channel width of the MOS transistor 23 is made small, and the current Even if the supply capacity is reduced, the terminal 2 due to this MOS transistor 23
2 can sufficiently follow the voltage rise at the terminal 21. At this time, the power supply voltage supplied to the terminal 31 of the buffer circuit 30 is the same as the voltage increase at the terminal 22, and the potential difference between the terminal 22 and the terminal 31 changes in a substantially constant state. Therefore, an excessive current does not flow through the buffer circuit 30 as in the conventional case, and together with the ability to reduce the channel width of the load MOS transistor 23, a significant reduction in current consumption is achieved. Furthermore, the latch-up phenomenon in the buffer circuit 30 can be prevented.

At this time, the MOS transistor 51 in the load circuit 50 receives the control signal / which is set to "1".
The gate of the depletion type MOS transistor 52 is turned off by 0.
A control signal R/ is supplied.
Therefore, the output terminal 22 of the address decoding section 20
Even if V is set to V _P , the potential at the series connection point of MOS transistors 51 and 52 is
2, and this value is at most
Since it is about 3V, which is lower than V _C of 5V, current is prevented from flowing from the high voltage V _P to V _C via the MOS transistor 51 .

On the other hand, when reading data, the control signal R/
is “1”, /P is “0”, and the load circuit 50
The MOS transistor 51 inside is turned on,
The voltage is applied to the terminal 22 through the transistors 51 and 52.
Charged to V _C. Therefore, the charging speed of the terminal 22 can be made faster than when the MOS transistor 23 is used alone, and as a result, the output terminal 3 of the buffer circuit 30
It is possible to speed up the selection operation of the memory cells connected to 2.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a decoder circuit that can reduce current consumption when programming data and does not reduce the read speed when reading data.

[Brief explanation of drawings]

FIGS. 1 and 2 are circuit diagrams showing the configuration of an embodiment of the present invention, and FIGS. 3 and 4 are circuit diagrams of conventional circuits, respectively. 10... Voltage switching circuit, 11, 12... Voltage terminal, 14... Voltage output terminal, 20... Address decoding section, 30... Buffer circuit, 40... Inverter, 45... Capacity, 50... Load circuit .

Claims (1)

[Scope of Claims] 1. In a nonvolatile semiconductor memory device including a nonvolatile memory cell, a first voltage terminal to which a first voltage used when programming data in the memory cell is supplied; A second voltage terminal to which a second voltage used when reading data from the memory cell is supplied, and voltages applied to the first terminal and the second voltage terminal are switched based on a control signal. a voltage switching circuit that delays the rise of the first voltage when outputting the first voltage;
an address decode circuit comprising a load MOS transistor and a plurality of decoding MOS transistors to which an address signal is input, and to which the output voltage from the voltage switching circuit is supplied as a power supply voltage;
A decoder circuit comprising: a buffer circuit to which the output voltage from the voltage switching circuit is supplied as a power supply voltage, and which amplifies the output signal of the address decoding circuit and outputs the amplified signal as a signal for selecting the memory cell. 2. Claim 1, wherein a load circuit whose conduction is controlled when reading data from each memory cell is inserted between the output end of the address decoding circuit and the output end of the voltage switching circuit. The decoder circuit described in .