JPH04182985A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To shorten access time by electrically separating 2nd bit lines to which non-selected memory cells are connected from 1st bit lines. CONSTITUTION:The 1st bit lines to which the non-selected memory cells are connected are disconnected from the 2nd bit lines. Namely, only the bit lines connected to the selected memory cells 10 among the bit lines 23, 24 connected to the respective memory cells 10 are connected to the bit lines 21, 22 and the capacity of the bit lines 21 to 24 connected to the data lines 15, 16 is decreased. Namely, the capacity of the bit lines 21, 22 is larger as the diffused regions and contact parts are increased and, therefore, the capacity is decreased by reducing the number of the transistors to be connected to the bit lines 21, 22. The fluctuation in the potential of the bit lines 21, 22 is speeded up in this way and the access time is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a semiconductor memory device such as a RAM, and particularly to the structure of a signal line connected to a memory cell.

(b) Prior Art FIG. 3 is a circuit diagram schematically showing a static type RAM. In this figure, memory cells arranged in 4 rows and 4 columns are illustrated for the sake of simplification.

A plurality of memory cells (lO) arranged in rows and columns are connected to word lines (11) arranged in the row direction, and further connected to bit lines (12m3) arranged in the column direction. The word line (11) is given selection signals Y, -Y4 from a decoder that receives address data, and this selection signal Y1
~Y, the word line (11) is alternatively specified. A specified potential is applied to the designated word line (11), and the memory cell (11) connected to the word line (11) is
10) are connected to bit lines (12) and (13), respectively.

On the other hand, the bit line (12013) is connected to the data line (15016) via the MOS transistor (14) and to the power supply via the MOS transistor (17), and the specific MOS transistor (17) When turned on, the bit lines (12) (13) are selectively connected to the data lines (15) (16). Selection signals X, . The 6 data lines (15) (16) to be
It is connected to a sense amplifier that determines the data of the memory cell (10) or a write driver that writes data to the memory cell (10), and the MOS transistor (14) is turned on and the focus line (12013
) is connected, the specific memory cell (10) is connected to the sense amplifier or write driver.

MOS transistor (17) and a pair of bit lines (]
2013) MOS transistor (18) connected between
In order to initialize the bit line (12H13), an inverted clock 7;l of the clock φ1 that sets the active period of the bit line (12H13) is applied to the gate of the bit line (12H13), and the activation period of the bit line (12) (13) At times other than the period, the power supply potential is applied to the pair of bit lines (12) and (13), and the bit line (1
2) (13) is initialized.

FIG. 4 is a circuit diagram showing the configuration of each memory cell (10).

Each memory cell (lO) consists of four MOS transistors (1) (2) (3) (4) and two resistors (5) (
6), the drains and gates of MOS transistors (1) and (2) are connected to each other, and the drains are connected to the power supply through the respective resistors (5) < 6), and the sources are grounded, making it bistable. A type of fritub flop is constructed. Furthermore, the drains of the MOS transistors (1) and (2) are connected to the bit line (1, 2013) via the MOS transistors (3) and (4), and the word line (11)
The gate of a MOS transistor (3H4) is connected to.

Therefore, a specific memory cell (1
0) is specified, for example, that memory cell (10)
are bit lines (12)<13) and data lines (15) (
+6) to the sense amplifier, and the stored data is read out through the sense amplifier.

(c) Problems to be Solved by the Invention However, in the memory cell <10) as described above, when the capacitance of the bit lines (12) (13) increases, the potential of the bit lines (12) (13) changes. Because it becomes slow,
A problem arises in that access time becomes long and high-speed operation becomes difficult.

Further, even when the bit lines (12) and (13) are inactive, that is, the MOS transistor (14) is turned off, the word line (11) is selected and the corresponding memory cell (10
) When the MOS l-transistors (3) and (4) of
Since the discharge current flows to the ground side through the bit line (+
2) The potential of (13) is lowered to ground potential.

Therefore, the power consumed when turning on the MOS transistors (17) and (18) to initialize the bit line (12013) increases, and the potential of the ground line increases due to the current flowing into the ground line. There is a risk that the memory cell (10) etc. may malfunction. The influence of such a discharge current flowing into the power supply line increases as the number of rows and columns of memory cells (10) increases.
This problem becomes noticeable in large-capacity memory devices. Therefore, the present invention aims to reduce power consumption, prevent the potential rise of the ground line, and further shorten access time, making it suitable for large-capacity memory devices. The purpose is to clean semiconductor memory devices.

(D) Means for Solving the Problems The present invention has been made to solve the above-mentioned problems, and is characterized in that a plurality of memory cells are arranged in columns and rows, and A semiconductor memory device in which bit lines and word lines are arranged along columns and rows of memory cells and connected to each memory cell, and the columns and rows of the memory cells are designated by selection of the bit lines and word lines. The bit line is divided into a plurality of parts, and a first bit line is connected to each column of memory cells, and a first bit line is connected to each column of memory cells. a second bit line which is selectively connected in units; and the first bit line to which unselected memory cells are connected.
The bit line is separated from the second focus line.

(E) Effect According to the present invention, the second memory cell to which unselected memory cells are connected
By electrically separating the first bit line from the first bit line, the capacitance of the bit line to which the selected memory cell is connected is reduced, and the potential of the bit line changes quickly, shortening the access time. Ru.

Furthermore, since the discharge current flowing from the bit line into unselected memory cells is reduced, the power consumed when initializing the bit line is reduced to a certain extent, and an increase in the potential of the ground line can be prevented.

(f) Example An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of the semiconductor memory device of the present invention, and FIG. 2 is a timing diagram showing its operation.

A plurality of memory cells (10) are arranged in row and column directions, and word lines (11) and bit lines (21>(22) are associated with each other along each row and column.
1) is connected to a corresponding memory cell (10), and each focus line (21) (22) is connected to a bit line (23) (24) associated with a memory cell (10) in which each column is divided into two.
) via an analog switch (25M26).

In addition, each bit line (21) (22) is provided with a precharge circuit consisting of MOS transistors (17) (18) as in FIG. 3, and a power supply potential is supplied according to the inverted clock ¥1. In addition, MOS transistor (
The data line (15H16) is connected through the data line (15H16), and the data of the memory cell (10) is
The signal is read to the sense amplifier via the . Furthermore, the bit line (23N24) is connected to a MOS transistor (27).
A precharge circuit consisting of (28) is provided, and a power supply potential is applied according to the inverted clock signal similarly to the bit lines (21) and (22).

Therefore, the bit line (
23) (24>) only those connected to the selected memory cell (10) are connected to the bit line (21>(22), and the bit lines (15) and (16) are connected to the data lines (15) and (16).
2+)(22>(23)(24) capacity is reduced.

In general, the capacitance of the bit lines (21) (22) increases as the number of contact areas with the diffusion region increases, so the capacitance can be reduced by reducing the number of transistors connected to the bit lines (21) (22). I can figure it out.

As shown in FIG. 2, the clock φ1 that sets the active period of the bit lines (21) and (22) rises shortly after the address ADH changes, and after this, the clock φ1 that sets the active period of the bit lines (11) and bit lines (22) rises. 21) Clocks φ2 and φ for operating the decoder that selects (22) rise sequentially. At this time, one of the clocks φ6 and φ8 rises following the clock φ2, depending on the address data. Therefore, the address is specified and the bit line (
21) When (22) becomes active, the word line (11)
The selection signals Y, ~Y4 are applied to the memory cells (10).
At the same time, the bit lines (23) (24>) are selectively connected to the bit lines (21022>), and selection signals X, ~X4 are then applied to the bit lines (21N22) to select the memory cells. Column (10) is specified.

At this time, the bit lines (21) and (22) are connected to the bit lines (21) and (22).
Since one of 23) and 24 is connected, the memory cell (
The number of connection points with 10) is halved, and the capacity can be reduced.

According to such a configuration, by reducing the capacitance of the bit line (21N22>) specified based on address data,
The potential fluctuations of the bit lines (21) and (22) become faster, and the access time can be shortened.

Here, clocks having different timings are applied to the analog switches (25) and (26) connected to each bit line (23) and (24), respectively, and the analog switches (
25) and (26) to operate separately, the word line (1
1), the capacitance of the bit line (23) (24) connected to the designated memory cell (10) can be reduced. That is,
In the unselected memory cell (10), the word line (1
A specific memory cell (10) designated by Since the analog switch <25026) of the memory cell (10) is off, the short bit line (23>(2
4) is connected. Therefore, unselected memory cells (
10) from the bit lines (23) (24) decreases, and the discharge current flowing into the bit lines (21) (22) (23) (24) decreases.
) is reduced.

In this embodiment, the case where two divided bit lines (23) and (24) are associated with a memory cell (lO) arranged in 4 rows and 4 columns is illustrated, but when the number of rows of memory cells (10) increases. In this case, it is also possible to divide the bit lines (23) (24) into four or eight parts, and the method of dividing the bit lines BL may be appropriately set according to the number of memory cells (10).

(G) Effects of the Invention According to the present invention, since the capacitance of the bit line connected to the memory cell can be reduced, the potential fluctuation of the bit line becomes faster and the access time is shortened. In the unselected memory cell column, the discharge current flowing from the bit line to the unselected memory cell can be reduced, the power consumed when initializing the bit line can be reduced, and each memory cell can be connected This suppresses the rise in potential of the ground line, thereby preventing memory cells from malfunctioning.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of an embodiment of the present invention, Figure 2 is a timing diagram of the operation of Figure 1, Figure 3 is a circuit diagram of a conventional semiconductor memory device, and Figure 4 is a circuit diagram of a memory cell. be.

Claims (2)

[Claims] (1) A plurality of memory cells are arranged in columns and rows, and bit lines and word lines are arranged along the columns and rows of the memory cells and connected to each memory cell, and the bit lines and word lines are arranged along the columns and rows of the memory cells. In a semiconductor memory device in which the column and row of the memory cell are designated by line selection, the bit line is connected to each memory cell in correspondence with each of the plurality of divided columns of memory cells. and a second bit line to which the first bit line is selectively connected in each column, the first bit line to which unselected memory cells are connected. A semiconductor memory device characterized in that a line is separated from the second bit line. (2) The semiconductor memory device according to claim 1, wherein the first bit line is selectively connected to the second bit line according to address information for selecting the word line.